1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
11 #include <rte_interrupts.h>
12 #include <rte_debug.h>
14 #include <rte_atomic.h>
16 #include <rte_ether.h>
17 #include <ethdev_pci.h>
18 #include <rte_kvargs.h>
19 #include <rte_malloc.h>
20 #include <rte_memzone.h>
23 #include <iavf_devids.h>
25 #include "ice_generic_flow.h"
26 #include "ice_dcf_ethdev.h"
30 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
31 struct rte_eth_udp_tunnel *udp_tunnel);
33 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
34 struct rte_eth_udp_tunnel *udp_tunnel);
37 ice_dcf_recv_pkts(__rte_unused void *rx_queue,
38 __rte_unused struct rte_mbuf **bufs,
39 __rte_unused uint16_t nb_pkts)
45 ice_dcf_xmit_pkts(__rte_unused void *tx_queue,
46 __rte_unused struct rte_mbuf **bufs,
47 __rte_unused uint16_t nb_pkts)
53 ice_dcf_init_rxq(struct rte_eth_dev *dev, struct ice_rx_queue *rxq)
55 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
56 struct rte_eth_dev_data *dev_data = dev->data;
57 struct iavf_hw *hw = &dcf_ad->real_hw.avf;
58 uint16_t buf_size, max_pkt_len, len;
60 buf_size = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
62 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
63 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
64 max_pkt_len = RTE_MIN(len, dev->data->dev_conf.rxmode.max_rx_pkt_len);
66 /* Check if the jumbo frame and maximum packet length are set
69 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
70 if (max_pkt_len <= ICE_ETH_MAX_LEN ||
71 max_pkt_len > ICE_FRAME_SIZE_MAX) {
72 PMD_DRV_LOG(ERR, "maximum packet length must be "
73 "larger than %u and smaller than %u, "
74 "as jumbo frame is enabled",
75 (uint32_t)ICE_ETH_MAX_LEN,
76 (uint32_t)ICE_FRAME_SIZE_MAX);
80 if (max_pkt_len < RTE_ETHER_MIN_LEN ||
81 max_pkt_len > ICE_ETH_MAX_LEN) {
82 PMD_DRV_LOG(ERR, "maximum packet length must be "
83 "larger than %u and smaller than %u, "
84 "as jumbo frame is disabled",
85 (uint32_t)RTE_ETHER_MIN_LEN,
86 (uint32_t)ICE_ETH_MAX_LEN);
91 rxq->max_pkt_len = max_pkt_len;
92 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
93 (rxq->max_pkt_len + 2 * ICE_VLAN_TAG_SIZE) > buf_size) {
94 dev_data->scattered_rx = 1;
96 rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
97 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
104 ice_dcf_init_rx_queues(struct rte_eth_dev *dev)
106 struct ice_rx_queue **rxq =
107 (struct ice_rx_queue **)dev->data->rx_queues;
110 for (i = 0; i < dev->data->nb_rx_queues; i++) {
111 if (!rxq[i] || !rxq[i]->q_set)
113 ret = ice_dcf_init_rxq(dev, rxq[i]);
118 ice_set_rx_function(dev);
119 ice_set_tx_function(dev);
124 #define IAVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
125 #define IAVF_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
127 #define IAVF_ITR_INDEX_DEFAULT 0
128 #define IAVF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
129 #define IAVF_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
131 static inline uint16_t
132 iavf_calc_itr_interval(int16_t interval)
134 if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX)
135 interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT;
137 /* Convert to hardware count, as writing each 1 represents 2 us */
142 ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,
143 struct rte_intr_handle *intr_handle)
145 struct ice_dcf_adapter *adapter = dev->data->dev_private;
146 struct ice_dcf_hw *hw = &adapter->real_hw;
147 uint16_t interval, i;
150 if (rte_intr_cap_multiple(intr_handle) &&
151 dev->data->dev_conf.intr_conf.rxq) {
152 if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues))
156 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
157 intr_handle->intr_vec =
158 rte_zmalloc("intr_vec",
159 dev->data->nb_rx_queues * sizeof(int), 0);
160 if (!intr_handle->intr_vec) {
161 PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec",
162 dev->data->nb_rx_queues);
167 if (!dev->data->dev_conf.intr_conf.rxq ||
168 !rte_intr_dp_is_en(intr_handle)) {
169 /* Rx interrupt disabled, Map interrupt only for writeback */
171 if (hw->vf_res->vf_cap_flags &
172 VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
173 /* If WB_ON_ITR supports, enable it */
174 hw->msix_base = IAVF_RX_VEC_START;
175 IAVF_WRITE_REG(&hw->avf,
176 IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1),
177 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
178 IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
180 /* If no WB_ON_ITR offload flags, need to set
181 * interrupt for descriptor write back.
183 hw->msix_base = IAVF_MISC_VEC_ID;
187 iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX);
188 IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01,
189 IAVF_VFINT_DYN_CTL01_INTENA_MASK |
190 (IAVF_ITR_INDEX_DEFAULT <<
191 IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
193 IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
195 IAVF_WRITE_FLUSH(&hw->avf);
196 /* map all queues to the same interrupt */
197 for (i = 0; i < dev->data->nb_rx_queues; i++)
198 hw->rxq_map[hw->msix_base] |= 1 << i;
200 if (!rte_intr_allow_others(intr_handle)) {
202 hw->msix_base = IAVF_MISC_VEC_ID;
203 for (i = 0; i < dev->data->nb_rx_queues; i++) {
204 hw->rxq_map[hw->msix_base] |= 1 << i;
205 intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID;
208 "vector %u are mapping to all Rx queues",
211 /* If Rx interrupt is reuquired, and we can use
212 * multi interrupts, then the vec is from 1
214 hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors,
215 intr_handle->nb_efd);
216 hw->msix_base = IAVF_MISC_VEC_ID;
217 vec = IAVF_MISC_VEC_ID;
218 for (i = 0; i < dev->data->nb_rx_queues; i++) {
219 hw->rxq_map[vec] |= 1 << i;
220 intr_handle->intr_vec[i] = vec++;
221 if (vec >= hw->nb_msix)
222 vec = IAVF_RX_VEC_START;
225 "%u vectors are mapping to %u Rx queues",
226 hw->nb_msix, dev->data->nb_rx_queues);
230 if (ice_dcf_config_irq_map(hw)) {
231 PMD_DRV_LOG(ERR, "config interrupt mapping failed");
238 alloc_rxq_mbufs(struct ice_rx_queue *rxq)
240 volatile union ice_rx_flex_desc *rxd;
241 struct rte_mbuf *mbuf = NULL;
245 for (i = 0; i < rxq->nb_rx_desc; i++) {
246 mbuf = rte_mbuf_raw_alloc(rxq->mp);
247 if (unlikely(!mbuf)) {
248 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
252 rte_mbuf_refcnt_set(mbuf, 1);
254 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
256 mbuf->port = rxq->port_id;
259 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
261 rxd = &rxq->rx_ring[i];
262 rxd->read.pkt_addr = dma_addr;
263 rxd->read.hdr_addr = 0;
264 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
269 rxq->sw_ring[i].mbuf = (void *)mbuf;
276 ice_dcf_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
278 struct ice_dcf_adapter *ad = dev->data->dev_private;
279 struct iavf_hw *hw = &ad->real_hw.avf;
280 struct ice_rx_queue *rxq;
283 if (rx_queue_id >= dev->data->nb_rx_queues)
286 rxq = dev->data->rx_queues[rx_queue_id];
288 err = alloc_rxq_mbufs(rxq);
290 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
296 /* Init the RX tail register. */
297 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
298 IAVF_WRITE_FLUSH(hw);
300 /* Ready to switch the queue on */
301 err = ice_dcf_switch_queue(&ad->real_hw, rx_queue_id, true, true);
303 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
308 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
314 reset_rx_queue(struct ice_rx_queue *rxq)
322 len = rxq->nb_rx_desc + ICE_RX_MAX_BURST;
324 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
325 ((volatile char *)rxq->rx_ring)[i] = 0;
327 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
329 for (i = 0; i < ICE_RX_MAX_BURST; i++)
330 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
333 rxq->rx_nb_avail = 0;
334 rxq->rx_next_avail = 0;
335 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
339 rxq->pkt_first_seg = NULL;
340 rxq->pkt_last_seg = NULL;
344 reset_tx_queue(struct ice_tx_queue *txq)
346 struct ice_tx_entry *txe;
351 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
356 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
357 for (i = 0; i < size; i++)
358 ((volatile char *)txq->tx_ring)[i] = 0;
360 prev = (uint16_t)(txq->nb_tx_desc - 1);
361 for (i = 0; i < txq->nb_tx_desc; i++) {
362 txq->tx_ring[i].cmd_type_offset_bsz =
363 rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
366 txe[prev].next_id = i;
373 txq->last_desc_cleaned = txq->nb_tx_desc - 1;
374 txq->nb_tx_free = txq->nb_tx_desc - 1;
376 txq->tx_next_dd = txq->tx_rs_thresh - 1;
377 txq->tx_next_rs = txq->tx_rs_thresh - 1;
381 ice_dcf_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
383 struct ice_dcf_adapter *ad = dev->data->dev_private;
384 struct ice_dcf_hw *hw = &ad->real_hw;
385 struct ice_rx_queue *rxq;
388 if (rx_queue_id >= dev->data->nb_rx_queues)
391 err = ice_dcf_switch_queue(hw, rx_queue_id, true, false);
393 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
398 rxq = dev->data->rx_queues[rx_queue_id];
399 rxq->rx_rel_mbufs(rxq);
401 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
407 ice_dcf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
409 struct ice_dcf_adapter *ad = dev->data->dev_private;
410 struct iavf_hw *hw = &ad->real_hw.avf;
411 struct ice_tx_queue *txq;
414 if (tx_queue_id >= dev->data->nb_tx_queues)
417 txq = dev->data->tx_queues[tx_queue_id];
419 /* Init the RX tail register. */
420 txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(tx_queue_id);
421 IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
422 IAVF_WRITE_FLUSH(hw);
424 /* Ready to switch the queue on */
425 err = ice_dcf_switch_queue(&ad->real_hw, tx_queue_id, false, true);
428 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
433 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
439 ice_dcf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
441 struct ice_dcf_adapter *ad = dev->data->dev_private;
442 struct ice_dcf_hw *hw = &ad->real_hw;
443 struct ice_tx_queue *txq;
446 if (tx_queue_id >= dev->data->nb_tx_queues)
449 err = ice_dcf_switch_queue(hw, tx_queue_id, false, false);
451 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
456 txq = dev->data->tx_queues[tx_queue_id];
457 txq->tx_rel_mbufs(txq);
459 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
465 ice_dcf_start_queues(struct rte_eth_dev *dev)
467 struct ice_rx_queue *rxq;
468 struct ice_tx_queue *txq;
472 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
473 txq = dev->data->tx_queues[nb_txq];
474 if (txq->tx_deferred_start)
476 if (ice_dcf_tx_queue_start(dev, nb_txq) != 0) {
477 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_txq);
482 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
483 rxq = dev->data->rx_queues[nb_rxq];
484 if (rxq->rx_deferred_start)
486 if (ice_dcf_rx_queue_start(dev, nb_rxq) != 0) {
487 PMD_DRV_LOG(ERR, "Fail to start queue %u", nb_rxq);
494 /* stop the started queues if failed to start all queues */
496 for (i = 0; i < nb_rxq; i++)
497 ice_dcf_rx_queue_stop(dev, i);
499 for (i = 0; i < nb_txq; i++)
500 ice_dcf_tx_queue_stop(dev, i);
506 ice_dcf_dev_start(struct rte_eth_dev *dev)
508 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
509 struct rte_intr_handle *intr_handle = dev->intr_handle;
510 struct ice_adapter *ad = &dcf_ad->parent;
511 struct ice_dcf_hw *hw = &dcf_ad->real_hw;
514 ad->pf.adapter_stopped = 0;
516 hw->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
517 dev->data->nb_tx_queues);
519 ret = ice_dcf_init_rx_queues(dev);
521 PMD_DRV_LOG(ERR, "Fail to init queues");
525 if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
526 ret = ice_dcf_init_rss(hw);
528 PMD_DRV_LOG(ERR, "Failed to configure RSS");
533 ret = ice_dcf_configure_queues(hw);
535 PMD_DRV_LOG(ERR, "Fail to config queues");
539 ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle);
541 PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs");
545 if (dev->data->dev_conf.intr_conf.rxq != 0) {
546 rte_intr_disable(intr_handle);
547 rte_intr_enable(intr_handle);
550 ret = ice_dcf_start_queues(dev);
552 PMD_DRV_LOG(ERR, "Failed to enable queues");
556 ret = ice_dcf_add_del_all_mac_addr(hw, true);
558 PMD_DRV_LOG(ERR, "Failed to add mac addr");
562 dev->data->dev_link.link_status = ETH_LINK_UP;
568 ice_dcf_stop_queues(struct rte_eth_dev *dev)
570 struct ice_dcf_adapter *ad = dev->data->dev_private;
571 struct ice_dcf_hw *hw = &ad->real_hw;
572 struct ice_rx_queue *rxq;
573 struct ice_tx_queue *txq;
576 /* Stop All queues */
577 ret = ice_dcf_disable_queues(hw);
579 PMD_DRV_LOG(WARNING, "Fail to stop queues");
581 for (i = 0; i < dev->data->nb_tx_queues; i++) {
582 txq = dev->data->tx_queues[i];
585 txq->tx_rel_mbufs(txq);
587 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
589 for (i = 0; i < dev->data->nb_rx_queues; i++) {
590 rxq = dev->data->rx_queues[i];
593 rxq->rx_rel_mbufs(rxq);
595 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
600 ice_dcf_dev_stop(struct rte_eth_dev *dev)
602 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
603 struct rte_intr_handle *intr_handle = dev->intr_handle;
604 struct ice_adapter *ad = &dcf_ad->parent;
606 if (ad->pf.adapter_stopped == 1) {
607 PMD_DRV_LOG(DEBUG, "Port is already stopped");
611 /* Stop the VF representors for this device */
612 ice_dcf_vf_repr_stop_all(dcf_ad);
614 ice_dcf_stop_queues(dev);
616 rte_intr_efd_disable(intr_handle);
617 if (intr_handle->intr_vec) {
618 rte_free(intr_handle->intr_vec);
619 intr_handle->intr_vec = NULL;
622 ice_dcf_add_del_all_mac_addr(&dcf_ad->real_hw, false);
623 dev->data->dev_link.link_status = ETH_LINK_DOWN;
624 ad->pf.adapter_stopped = 1;
630 ice_dcf_dev_configure(struct rte_eth_dev *dev)
632 struct ice_dcf_adapter *dcf_ad = dev->data->dev_private;
633 struct ice_adapter *ad = &dcf_ad->parent;
635 ad->rx_bulk_alloc_allowed = true;
636 ad->tx_simple_allowed = true;
638 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
639 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
645 ice_dcf_dev_info_get(struct rte_eth_dev *dev,
646 struct rte_eth_dev_info *dev_info)
648 struct ice_dcf_adapter *adapter = dev->data->dev_private;
649 struct ice_dcf_hw *hw = &adapter->real_hw;
651 dev_info->max_mac_addrs = 1;
652 dev_info->max_rx_queues = hw->vsi_res->num_queue_pairs;
653 dev_info->max_tx_queues = hw->vsi_res->num_queue_pairs;
654 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
655 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
656 dev_info->hash_key_size = hw->vf_res->rss_key_size;
657 dev_info->reta_size = hw->vf_res->rss_lut_size;
658 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
660 dev_info->rx_offload_capa =
661 DEV_RX_OFFLOAD_VLAN_STRIP |
662 DEV_RX_OFFLOAD_IPV4_CKSUM |
663 DEV_RX_OFFLOAD_UDP_CKSUM |
664 DEV_RX_OFFLOAD_TCP_CKSUM |
665 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
666 DEV_RX_OFFLOAD_SCATTER |
667 DEV_RX_OFFLOAD_JUMBO_FRAME |
668 DEV_RX_OFFLOAD_VLAN_FILTER |
669 DEV_RX_OFFLOAD_RSS_HASH;
670 dev_info->tx_offload_capa =
671 DEV_TX_OFFLOAD_VLAN_INSERT |
672 DEV_TX_OFFLOAD_IPV4_CKSUM |
673 DEV_TX_OFFLOAD_UDP_CKSUM |
674 DEV_TX_OFFLOAD_TCP_CKSUM |
675 DEV_TX_OFFLOAD_SCTP_CKSUM |
676 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
677 DEV_TX_OFFLOAD_TCP_TSO |
678 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
679 DEV_TX_OFFLOAD_GRE_TNL_TSO |
680 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
681 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
682 DEV_TX_OFFLOAD_MULTI_SEGS;
684 dev_info->default_rxconf = (struct rte_eth_rxconf) {
686 .pthresh = ICE_DEFAULT_RX_PTHRESH,
687 .hthresh = ICE_DEFAULT_RX_HTHRESH,
688 .wthresh = ICE_DEFAULT_RX_WTHRESH,
690 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
695 dev_info->default_txconf = (struct rte_eth_txconf) {
697 .pthresh = ICE_DEFAULT_TX_PTHRESH,
698 .hthresh = ICE_DEFAULT_TX_HTHRESH,
699 .wthresh = ICE_DEFAULT_TX_WTHRESH,
701 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
702 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
706 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
707 .nb_max = ICE_MAX_RING_DESC,
708 .nb_min = ICE_MIN_RING_DESC,
709 .nb_align = ICE_ALIGN_RING_DESC,
712 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
713 .nb_max = ICE_MAX_RING_DESC,
714 .nb_min = ICE_MIN_RING_DESC,
715 .nb_align = ICE_ALIGN_RING_DESC,
722 ice_dcf_dev_promiscuous_enable(__rte_unused struct rte_eth_dev *dev)
728 ice_dcf_dev_promiscuous_disable(__rte_unused struct rte_eth_dev *dev)
734 ice_dcf_dev_allmulticast_enable(__rte_unused struct rte_eth_dev *dev)
740 ice_dcf_dev_allmulticast_disable(__rte_unused struct rte_eth_dev *dev)
746 ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev,
747 const struct rte_flow_ops **ops)
752 *ops = &ice_flow_ops;
756 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4)
757 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6)
758 #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t)
761 ice_dcf_stat_update_48(uint64_t *offset, uint64_t *stat)
763 if (*stat >= *offset)
764 *stat = *stat - *offset;
766 *stat = (uint64_t)((*stat +
767 ((uint64_t)1 << ICE_DCF_48_BIT_WIDTH)) - *offset);
769 *stat &= ICE_DCF_48_BIT_MASK;
773 ice_dcf_stat_update_32(uint64_t *offset, uint64_t *stat)
775 if (*stat >= *offset)
776 *stat = (uint64_t)(*stat - *offset);
778 *stat = (uint64_t)((*stat +
779 ((uint64_t)1 << ICE_DCF_32_BIT_WIDTH)) - *offset);
783 ice_dcf_update_stats(struct virtchnl_eth_stats *oes,
784 struct virtchnl_eth_stats *nes)
786 ice_dcf_stat_update_48(&oes->rx_bytes, &nes->rx_bytes);
787 ice_dcf_stat_update_48(&oes->rx_unicast, &nes->rx_unicast);
788 ice_dcf_stat_update_48(&oes->rx_multicast, &nes->rx_multicast);
789 ice_dcf_stat_update_48(&oes->rx_broadcast, &nes->rx_broadcast);
790 ice_dcf_stat_update_32(&oes->rx_discards, &nes->rx_discards);
791 ice_dcf_stat_update_48(&oes->tx_bytes, &nes->tx_bytes);
792 ice_dcf_stat_update_48(&oes->tx_unicast, &nes->tx_unicast);
793 ice_dcf_stat_update_48(&oes->tx_multicast, &nes->tx_multicast);
794 ice_dcf_stat_update_48(&oes->tx_broadcast, &nes->tx_broadcast);
795 ice_dcf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
796 ice_dcf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
801 ice_dcf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
803 struct ice_dcf_adapter *ad = dev->data->dev_private;
804 struct ice_dcf_hw *hw = &ad->real_hw;
805 struct virtchnl_eth_stats pstats;
808 ret = ice_dcf_query_stats(hw, &pstats);
810 ice_dcf_update_stats(&hw->eth_stats_offset, &pstats);
811 stats->ipackets = pstats.rx_unicast + pstats.rx_multicast +
812 pstats.rx_broadcast - pstats.rx_discards;
813 stats->opackets = pstats.tx_broadcast + pstats.tx_multicast +
815 stats->imissed = pstats.rx_discards;
816 stats->oerrors = pstats.tx_errors + pstats.tx_discards;
817 stats->ibytes = pstats.rx_bytes;
818 stats->ibytes -= stats->ipackets * RTE_ETHER_CRC_LEN;
819 stats->obytes = pstats.tx_bytes;
821 PMD_DRV_LOG(ERR, "Get statistics failed");
827 ice_dcf_stats_reset(struct rte_eth_dev *dev)
829 struct ice_dcf_adapter *ad = dev->data->dev_private;
830 struct ice_dcf_hw *hw = &ad->real_hw;
831 struct virtchnl_eth_stats pstats;
834 /* read stat values to clear hardware registers */
835 ret = ice_dcf_query_stats(hw, &pstats);
839 /* set stats offset base on current values */
840 hw->eth_stats_offset = pstats;
846 ice_dcf_free_repr_info(struct ice_dcf_adapter *dcf_adapter)
848 if (dcf_adapter->repr_infos) {
849 rte_free(dcf_adapter->repr_infos);
850 dcf_adapter->repr_infos = NULL;
855 ice_dcf_init_repr_info(struct ice_dcf_adapter *dcf_adapter)
857 dcf_adapter->repr_infos =
858 rte_calloc("ice_dcf_rep_info",
859 dcf_adapter->real_hw.num_vfs,
860 sizeof(dcf_adapter->repr_infos[0]), 0);
861 if (!dcf_adapter->repr_infos) {
862 PMD_DRV_LOG(ERR, "Failed to alloc memory for VF representors\n");
870 ice_dcf_dev_close(struct rte_eth_dev *dev)
872 struct ice_dcf_adapter *adapter = dev->data->dev_private;
874 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
877 ice_dcf_free_repr_info(adapter);
878 ice_dcf_uninit_parent_adapter(dev);
879 ice_dcf_uninit_hw(dev, &adapter->real_hw);
885 ice_dcf_link_update(__rte_unused struct rte_eth_dev *dev,
886 __rte_unused int wait_to_complete)
891 /* Add UDP tunneling port */
893 ice_dcf_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
894 struct rte_eth_udp_tunnel *udp_tunnel)
896 struct ice_dcf_adapter *adapter = dev->data->dev_private;
897 struct ice_adapter *parent_adapter = &adapter->parent;
898 struct ice_hw *parent_hw = &parent_adapter->hw;
904 switch (udp_tunnel->prot_type) {
905 case RTE_TUNNEL_TYPE_VXLAN:
906 ret = ice_create_tunnel(parent_hw, TNL_VXLAN,
907 udp_tunnel->udp_port);
909 case RTE_TUNNEL_TYPE_ECPRI:
910 ret = ice_create_tunnel(parent_hw, TNL_ECPRI,
911 udp_tunnel->udp_port);
914 PMD_DRV_LOG(ERR, "Invalid tunnel type");
922 /* Delete UDP tunneling port */
924 ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
925 struct rte_eth_udp_tunnel *udp_tunnel)
927 struct ice_dcf_adapter *adapter = dev->data->dev_private;
928 struct ice_adapter *parent_adapter = &adapter->parent;
929 struct ice_hw *parent_hw = &parent_adapter->hw;
935 switch (udp_tunnel->prot_type) {
936 case RTE_TUNNEL_TYPE_VXLAN:
937 case RTE_TUNNEL_TYPE_ECPRI:
938 ret = ice_destroy_tunnel(parent_hw, udp_tunnel->udp_port, 0);
941 PMD_DRV_LOG(ERR, "Invalid tunnel type");
949 static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
950 .dev_start = ice_dcf_dev_start,
951 .dev_stop = ice_dcf_dev_stop,
952 .dev_close = ice_dcf_dev_close,
953 .dev_configure = ice_dcf_dev_configure,
954 .dev_infos_get = ice_dcf_dev_info_get,
955 .rx_queue_setup = ice_rx_queue_setup,
956 .tx_queue_setup = ice_tx_queue_setup,
957 .rx_queue_release = ice_rx_queue_release,
958 .tx_queue_release = ice_tx_queue_release,
959 .rx_queue_start = ice_dcf_rx_queue_start,
960 .tx_queue_start = ice_dcf_tx_queue_start,
961 .rx_queue_stop = ice_dcf_rx_queue_stop,
962 .tx_queue_stop = ice_dcf_tx_queue_stop,
963 .link_update = ice_dcf_link_update,
964 .stats_get = ice_dcf_stats_get,
965 .stats_reset = ice_dcf_stats_reset,
966 .promiscuous_enable = ice_dcf_dev_promiscuous_enable,
967 .promiscuous_disable = ice_dcf_dev_promiscuous_disable,
968 .allmulticast_enable = ice_dcf_dev_allmulticast_enable,
969 .allmulticast_disable = ice_dcf_dev_allmulticast_disable,
970 .flow_ops_get = ice_dcf_dev_flow_ops_get,
971 .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add,
972 .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del,
976 ice_dcf_dev_init(struct rte_eth_dev *eth_dev)
978 struct ice_dcf_adapter *adapter = eth_dev->data->dev_private;
980 eth_dev->dev_ops = &ice_dcf_eth_dev_ops;
981 eth_dev->rx_pkt_burst = ice_dcf_recv_pkts;
982 eth_dev->tx_pkt_burst = ice_dcf_xmit_pkts;
984 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
987 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
989 adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg;
990 if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) {
991 PMD_INIT_LOG(ERR, "Failed to init DCF hardware");
995 if (ice_dcf_init_parent_adapter(eth_dev) != 0) {
996 PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter");
997 ice_dcf_uninit_hw(eth_dev, &adapter->real_hw);
1005 ice_dcf_dev_uninit(struct rte_eth_dev *eth_dev)
1007 ice_dcf_dev_close(eth_dev);
1013 ice_dcf_cap_check_handler(__rte_unused const char *key,
1014 const char *value, __rte_unused void *opaque)
1016 if (strcmp(value, "dcf"))
1023 ice_dcf_cap_selected(struct rte_devargs *devargs)
1025 struct rte_kvargs *kvlist;
1026 const char *key = "cap";
1029 if (devargs == NULL)
1032 kvlist = rte_kvargs_parse(devargs->args, NULL);
1036 if (!rte_kvargs_count(kvlist, key))
1039 /* dcf capability selected when there's a key-value pair: cap=dcf */
1040 if (rte_kvargs_process(kvlist, key,
1041 ice_dcf_cap_check_handler, NULL) < 0)
1047 rte_kvargs_free(kvlist);
1052 eth_ice_dcf_pci_probe(__rte_unused struct rte_pci_driver *pci_drv,
1053 struct rte_pci_device *pci_dev)
1055 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
1056 struct ice_dcf_vf_repr_param repr_param;
1057 char repr_name[RTE_ETH_NAME_MAX_LEN];
1058 struct ice_dcf_adapter *dcf_adapter;
1059 struct rte_eth_dev *dcf_ethdev;
1060 uint16_t dcf_vsi_id;
1063 if (!ice_dcf_cap_selected(pci_dev->device.devargs))
1066 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, ð_da);
1070 ret = rte_eth_dev_pci_generic_probe(pci_dev,
1071 sizeof(struct ice_dcf_adapter),
1073 if (ret || !eth_da.nb_representor_ports)
1075 if (eth_da.type != RTE_ETH_REPRESENTOR_VF)
1078 dcf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1079 if (dcf_ethdev == NULL)
1082 dcf_adapter = dcf_ethdev->data->dev_private;
1083 ret = ice_dcf_init_repr_info(dcf_adapter);
1087 if (eth_da.nb_representor_ports > dcf_adapter->real_hw.num_vfs ||
1088 eth_da.nb_representor_ports >= RTE_MAX_ETHPORTS) {
1089 PMD_DRV_LOG(ERR, "the number of port representors is too large: %u",
1090 eth_da.nb_representor_ports);
1091 ice_dcf_free_repr_info(dcf_adapter);
1095 dcf_vsi_id = dcf_adapter->real_hw.vsi_id | VIRTCHNL_DCF_VF_VSI_VALID;
1097 repr_param.dcf_eth_dev = dcf_ethdev;
1098 repr_param.switch_domain_id = 0;
1100 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1101 uint16_t vf_id = eth_da.representor_ports[i];
1102 struct rte_eth_dev *vf_rep_eth_dev;
1104 if (vf_id >= dcf_adapter->real_hw.num_vfs) {
1105 PMD_DRV_LOG(ERR, "VF ID %u is out of range (0 ~ %u)",
1106 vf_id, dcf_adapter->real_hw.num_vfs - 1);
1111 if (dcf_adapter->real_hw.vf_vsi_map[vf_id] == dcf_vsi_id) {
1112 PMD_DRV_LOG(ERR, "VF ID %u is DCF's ID.\n", vf_id);
1117 repr_param.vf_id = vf_id;
1118 snprintf(repr_name, sizeof(repr_name), "net_%s_representor_%u",
1119 pci_dev->device.name, vf_id);
1120 ret = rte_eth_dev_create(&pci_dev->device, repr_name,
1121 sizeof(struct ice_dcf_vf_repr),
1122 NULL, NULL, ice_dcf_vf_repr_init,
1125 PMD_DRV_LOG(ERR, "failed to create DCF VF representor %s",
1130 vf_rep_eth_dev = rte_eth_dev_allocated(repr_name);
1131 if (!vf_rep_eth_dev) {
1133 "Failed to find the ethdev for DCF VF representor: %s",
1139 dcf_adapter->repr_infos[vf_id].vf_rep_eth_dev = vf_rep_eth_dev;
1140 dcf_adapter->num_reprs++;
1147 eth_ice_dcf_pci_remove(struct rte_pci_device *pci_dev)
1149 struct rte_eth_dev *eth_dev;
1151 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1155 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1156 return rte_eth_dev_pci_generic_remove(pci_dev,
1157 ice_dcf_vf_repr_uninit);
1159 return rte_eth_dev_pci_generic_remove(pci_dev,
1160 ice_dcf_dev_uninit);
1163 static const struct rte_pci_id pci_id_ice_dcf_map[] = {
1164 { RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
1165 { .vendor_id = 0, /* sentinel */ },
1168 static struct rte_pci_driver rte_ice_dcf_pmd = {
1169 .id_table = pci_id_ice_dcf_map,
1170 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1171 .probe = eth_ice_dcf_pci_probe,
1172 .remove = eth_ice_dcf_pci_remove,
1175 RTE_PMD_REGISTER_PCI(net_ice_dcf, rte_ice_dcf_pmd);
1176 RTE_PMD_REGISTER_PCI_TABLE(net_ice_dcf, pci_id_ice_dcf_map);
1177 RTE_PMD_REGISTER_KMOD_DEP(net_ice_dcf, "* igb_uio | vfio-pci");
1178 RTE_PMD_REGISTER_PARAM_STRING(net_ice_dcf, "cap=dcf");