1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_driver.h>
8 #include "rte_pmd_ice.h"
11 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
15 PKT_TX_OUTER_IP_CKSUM)
17 /* Offset of mbuf dynamic field for protocol extraction data */
18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
20 /* Mask of mbuf dynamic flags for protocol extraction type */
21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
29 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
31 static uint8_t rxdid_map[] = {
32 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
33 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
34 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
35 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
36 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
37 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
38 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
41 return xtr_type < RTE_DIM(rxdid_map) ?
42 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
46 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
48 volatile union ice_rx_flex_desc *rxdp)
50 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
51 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
52 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
56 if (desc->flow_id != 0xFFFFFFFF) {
57 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
58 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
61 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
62 stat_err = rte_le_to_cpu_16(desc->status_error0);
63 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
64 mb->ol_flags |= PKT_RX_RSS_HASH;
65 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
71 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
73 volatile union ice_rx_flex_desc *rxdp)
75 volatile struct ice_32b_rx_flex_desc_comms *desc =
76 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
79 stat_err = rte_le_to_cpu_16(desc->status_error0);
80 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
81 mb->ol_flags |= PKT_RX_RSS_HASH;
82 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
85 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
86 if (desc->flow_id != 0xFFFFFFFF) {
87 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
88 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
91 if (rxq->xtr_ol_flag) {
92 uint32_t metadata = 0;
94 stat_err = rte_le_to_cpu_16(desc->status_error1);
96 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
97 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
99 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
101 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
104 mb->ol_flags |= rxq->xtr_ol_flag;
106 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
113 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
115 volatile union ice_rx_flex_desc *rxdp)
117 volatile struct ice_32b_rx_flex_desc_comms *desc =
118 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
121 stat_err = rte_le_to_cpu_16(desc->status_error0);
122 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
123 mb->ol_flags |= PKT_RX_RSS_HASH;
124 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
127 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
128 if (desc->flow_id != 0xFFFFFFFF) {
129 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
130 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
133 if (rxq->xtr_ol_flag) {
134 uint32_t metadata = 0;
136 if (desc->flex_ts.flex.aux0 != 0xFFFF)
137 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
138 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
139 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
142 mb->ol_flags |= rxq->xtr_ol_flag;
144 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
151 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
154 case ICE_RXDID_COMMS_AUX_VLAN:
155 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
156 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
159 case ICE_RXDID_COMMS_AUX_IPV4:
160 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
161 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
164 case ICE_RXDID_COMMS_AUX_IPV6:
165 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
166 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
169 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
170 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
171 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
174 case ICE_RXDID_COMMS_AUX_TCP:
175 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
176 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
179 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
180 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
181 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
184 case ICE_RXDID_COMMS_OVS:
185 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
189 /* update this according to the RXDID for PROTO_XTR_NONE */
190 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
194 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
195 rxq->xtr_ol_flag = 0;
198 static enum ice_status
199 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
201 struct ice_vsi *vsi = rxq->vsi;
202 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
203 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
204 struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
205 struct ice_rlan_ctx rx_ctx;
207 uint16_t buf_size, len;
208 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
209 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
212 /* Set buffer size as the head split is disabled. */
213 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
214 RTE_PKTMBUF_HEADROOM);
216 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
217 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
218 rxq->max_pkt_len = RTE_MIN(len,
219 dev->data->dev_conf.rxmode.max_rx_pkt_len);
221 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
222 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
223 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
224 PMD_DRV_LOG(ERR, "maximum packet length must "
225 "be larger than %u and smaller than %u,"
226 "as jumbo frame is enabled",
227 (uint32_t)RTE_ETHER_MAX_LEN,
228 (uint32_t)ICE_FRAME_SIZE_MAX);
232 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
233 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
234 PMD_DRV_LOG(ERR, "maximum packet length must be "
235 "larger than %u and smaller than %u, "
236 "as jumbo frame is disabled",
237 (uint32_t)RTE_ETHER_MIN_LEN,
238 (uint32_t)RTE_ETHER_MAX_LEN);
243 memset(&rx_ctx, 0, sizeof(rx_ctx));
245 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
246 rx_ctx.qlen = rxq->nb_rx_desc;
247 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
248 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
249 rx_ctx.dtype = 0; /* No Header Split mode */
250 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
251 rx_ctx.dsize = 1; /* 32B descriptors */
253 rx_ctx.rxmax = rxq->max_pkt_len;
254 /* TPH: Transaction Layer Packet (TLP) processing hints */
255 rx_ctx.tphrdesc_ena = 1;
256 rx_ctx.tphwdesc_ena = 1;
257 rx_ctx.tphdata_ena = 1;
258 rx_ctx.tphhead_ena = 1;
259 /* Low Receive Queue Threshold defined in 64 descriptors units.
260 * When the number of free descriptors goes below the lrxqthresh,
261 * an immediate interrupt is triggered.
263 rx_ctx.lrxqthresh = 2;
264 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
267 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
269 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
271 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
272 rxq->port_id, rxq->queue_id, rxdid);
274 if (!(pf->supported_rxdid & BIT(rxdid))) {
275 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
280 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
282 /* Enable Flexible Descriptors in the queue context which
283 * allows this driver to select a specific receive descriptor format
285 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
286 QRXFLXP_CNTXT_RXDID_IDX_M;
288 /* increasing context priority to pick up profile ID;
289 * default is 0x01; setting to 0x03 to ensure profile
290 * is programming if prev context is of same priority
292 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
293 QRXFLXP_CNTXT_RXDID_PRIO_M;
295 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
297 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
299 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
303 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
305 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
310 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
311 RTE_PKTMBUF_HEADROOM);
313 /* Check if scattered RX needs to be used. */
314 if (rxq->max_pkt_len > buf_size)
315 dev->data->scattered_rx = 1;
317 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
319 /* Init the Rx tail register*/
320 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
325 /* Allocate mbufs for all descriptors in rx queue */
327 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
329 struct ice_rx_entry *rxe = rxq->sw_ring;
333 for (i = 0; i < rxq->nb_rx_desc; i++) {
334 volatile union ice_rx_flex_desc *rxd;
335 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
337 if (unlikely(!mbuf)) {
338 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
342 rte_mbuf_refcnt_set(mbuf, 1);
344 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
346 mbuf->port = rxq->port_id;
349 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
351 rxd = &rxq->rx_ring[i];
352 rxd->read.pkt_addr = dma_addr;
353 rxd->read.hdr_addr = 0;
354 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
364 /* Free all mbufs for descriptors in rx queue */
366 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
370 if (!rxq || !rxq->sw_ring) {
371 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
375 for (i = 0; i < rxq->nb_rx_desc; i++) {
376 if (rxq->sw_ring[i].mbuf) {
377 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
378 rxq->sw_ring[i].mbuf = NULL;
381 if (rxq->rx_nb_avail == 0)
383 for (i = 0; i < rxq->rx_nb_avail; i++)
384 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
386 rxq->rx_nb_avail = 0;
389 /* turn on or off rx queue
390 * @q_idx: queue index in pf scope
391 * @on: turn on or off the queue
394 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
399 /* QRX_CTRL = QRX_ENA */
400 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
403 if (reg & QRX_CTRL_QENA_STAT_M)
404 return 0; /* Already on, skip */
405 reg |= QRX_CTRL_QENA_REQ_M;
407 if (!(reg & QRX_CTRL_QENA_STAT_M))
408 return 0; /* Already off, skip */
409 reg &= ~QRX_CTRL_QENA_REQ_M;
412 /* Write the register */
413 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
414 /* Check the result. It is said that QENA_STAT
415 * follows the QENA_REQ not more than 10 use.
416 * TODO: need to change the wait counter later
418 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
419 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
420 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
422 if ((reg & QRX_CTRL_QENA_REQ_M) &&
423 (reg & QRX_CTRL_QENA_STAT_M))
426 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
427 !(reg & QRX_CTRL_QENA_STAT_M))
432 /* Check if it is timeout */
433 if (j >= ICE_CHK_Q_ENA_COUNT) {
434 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
435 (on ? "enable" : "disable"), q_idx);
443 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
447 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
448 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
449 "rxq->rx_free_thresh=%d, "
450 "ICE_RX_MAX_BURST=%d",
451 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
453 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
454 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
455 "rxq->rx_free_thresh=%d, "
456 "rxq->nb_rx_desc=%d",
457 rxq->rx_free_thresh, rxq->nb_rx_desc);
459 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
460 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
461 "rxq->nb_rx_desc=%d, "
462 "rxq->rx_free_thresh=%d",
463 rxq->nb_rx_desc, rxq->rx_free_thresh);
470 /* reset fields in ice_rx_queue back to default */
472 ice_reset_rx_queue(struct ice_rx_queue *rxq)
478 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
482 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
484 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
485 ((volatile char *)rxq->rx_ring)[i] = 0;
487 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
488 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
489 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
491 rxq->rx_nb_avail = 0;
492 rxq->rx_next_avail = 0;
493 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
497 rxq->pkt_first_seg = NULL;
498 rxq->pkt_last_seg = NULL;
500 rxq->rxrearm_start = 0;
505 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
507 struct ice_rx_queue *rxq;
509 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
511 PMD_INIT_FUNC_TRACE();
513 if (rx_queue_id >= dev->data->nb_rx_queues) {
514 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
515 rx_queue_id, dev->data->nb_rx_queues);
519 rxq = dev->data->rx_queues[rx_queue_id];
520 if (!rxq || !rxq->q_set) {
521 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
526 err = ice_program_hw_rx_queue(rxq);
528 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
533 err = ice_alloc_rx_queue_mbufs(rxq);
535 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
539 /* Init the RX tail register. */
540 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
542 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
544 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
547 rxq->rx_rel_mbufs(rxq);
548 ice_reset_rx_queue(rxq);
552 dev->data->rx_queue_state[rx_queue_id] =
553 RTE_ETH_QUEUE_STATE_STARTED;
559 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
561 struct ice_rx_queue *rxq;
563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565 if (rx_queue_id < dev->data->nb_rx_queues) {
566 rxq = dev->data->rx_queues[rx_queue_id];
568 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
570 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
574 rxq->rx_rel_mbufs(rxq);
575 ice_reset_rx_queue(rxq);
576 dev->data->rx_queue_state[rx_queue_id] =
577 RTE_ETH_QUEUE_STATE_STOPPED;
584 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
586 struct ice_tx_queue *txq;
590 struct ice_aqc_add_tx_qgrp *txq_elem;
591 struct ice_tlan_ctx tx_ctx;
594 PMD_INIT_FUNC_TRACE();
596 if (tx_queue_id >= dev->data->nb_tx_queues) {
597 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
598 tx_queue_id, dev->data->nb_tx_queues);
602 txq = dev->data->tx_queues[tx_queue_id];
603 if (!txq || !txq->q_set) {
604 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
609 buf_len = ice_struct_size(txq_elem, txqs, 1);
610 txq_elem = ice_malloc(hw, buf_len);
615 hw = ICE_VSI_TO_HW(vsi);
617 memset(&tx_ctx, 0, sizeof(tx_ctx));
618 txq_elem->num_txqs = 1;
619 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
621 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
622 tx_ctx.qlen = txq->nb_tx_desc;
623 tx_ctx.pf_num = hw->pf_id;
624 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
625 tx_ctx.src_vsi = vsi->vsi_id;
626 tx_ctx.port_num = hw->port_info->lport;
627 tx_ctx.tso_ena = 1; /* tso enable */
628 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
629 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
631 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
634 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
636 /* Init the Tx tail register*/
637 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
639 /* Fix me, we assume TC always 0 here */
640 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
641 txq_elem, buf_len, NULL);
643 PMD_DRV_LOG(ERR, "Failed to add lan txq");
647 /* store the schedule node id */
648 txq->q_teid = txq_elem->txqs[0].q_teid;
650 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
656 static enum ice_status
657 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
659 struct ice_vsi *vsi = rxq->vsi;
660 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
661 uint32_t rxdid = ICE_RXDID_LEGACY_1;
662 struct ice_rlan_ctx rx_ctx;
667 rxq->rx_buf_len = 1024;
669 memset(&rx_ctx, 0, sizeof(rx_ctx));
671 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
672 rx_ctx.qlen = rxq->nb_rx_desc;
673 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
674 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
675 rx_ctx.dtype = 0; /* No Header Split mode */
676 rx_ctx.dsize = 1; /* 32B descriptors */
677 rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
678 /* TPH: Transaction Layer Packet (TLP) processing hints */
679 rx_ctx.tphrdesc_ena = 1;
680 rx_ctx.tphwdesc_ena = 1;
681 rx_ctx.tphdata_ena = 1;
682 rx_ctx.tphhead_ena = 1;
683 /* Low Receive Queue Threshold defined in 64 descriptors units.
684 * When the number of free descriptors goes below the lrxqthresh,
685 * an immediate interrupt is triggered.
687 rx_ctx.lrxqthresh = 2;
688 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
691 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
693 /* Enable Flexible Descriptors in the queue context which
694 * allows this driver to select a specific receive descriptor format
696 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
697 QRXFLXP_CNTXT_RXDID_IDX_M;
699 /* increasing context priority to pick up profile ID;
700 * default is 0x01; setting to 0x03 to ensure profile
701 * is programming if prev context is of same priority
703 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
704 QRXFLXP_CNTXT_RXDID_PRIO_M;
706 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
708 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
710 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
714 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
716 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
721 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
723 /* Init the Rx tail register*/
724 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
730 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
732 struct ice_rx_queue *rxq;
734 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
735 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
737 PMD_INIT_FUNC_TRACE();
740 if (!rxq || !rxq->q_set) {
741 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
746 err = ice_fdir_program_hw_rx_queue(rxq);
748 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
753 /* Init the RX tail register. */
754 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
756 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
758 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
761 ice_reset_rx_queue(rxq);
769 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
771 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
772 struct ice_tx_queue *txq;
776 struct ice_aqc_add_tx_qgrp *txq_elem;
777 struct ice_tlan_ctx tx_ctx;
780 PMD_INIT_FUNC_TRACE();
783 if (!txq || !txq->q_set) {
784 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
789 buf_len = ice_struct_size(txq_elem, txqs, 1);
790 txq_elem = ice_malloc(hw, buf_len);
795 hw = ICE_VSI_TO_HW(vsi);
797 memset(&tx_ctx, 0, sizeof(tx_ctx));
798 txq_elem->num_txqs = 1;
799 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
801 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
802 tx_ctx.qlen = txq->nb_tx_desc;
803 tx_ctx.pf_num = hw->pf_id;
804 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
805 tx_ctx.src_vsi = vsi->vsi_id;
806 tx_ctx.port_num = hw->port_info->lport;
807 tx_ctx.tso_ena = 1; /* tso enable */
808 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
809 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
811 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
814 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
816 /* Init the Tx tail register*/
817 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
819 /* Fix me, we assume TC always 0 here */
820 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
821 txq_elem, buf_len, NULL);
823 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
827 /* store the schedule node id */
828 txq->q_teid = txq_elem->txqs[0].q_teid;
834 /* Free all mbufs for descriptors in tx queue */
836 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
840 if (!txq || !txq->sw_ring) {
841 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
845 for (i = 0; i < txq->nb_tx_desc; i++) {
846 if (txq->sw_ring[i].mbuf) {
847 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
848 txq->sw_ring[i].mbuf = NULL;
854 ice_reset_tx_queue(struct ice_tx_queue *txq)
856 struct ice_tx_entry *txe;
857 uint16_t i, prev, size;
860 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
865 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
866 for (i = 0; i < size; i++)
867 ((volatile char *)txq->tx_ring)[i] = 0;
869 prev = (uint16_t)(txq->nb_tx_desc - 1);
870 for (i = 0; i < txq->nb_tx_desc; i++) {
871 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
873 txd->cmd_type_offset_bsz =
874 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
877 txe[prev].next_id = i;
881 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
882 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
887 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
888 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
892 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
894 struct ice_tx_queue *txq;
895 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
897 struct ice_vsi *vsi = pf->main_vsi;
898 enum ice_status status;
901 uint16_t q_handle = tx_queue_id;
903 if (tx_queue_id >= dev->data->nb_tx_queues) {
904 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
905 tx_queue_id, dev->data->nb_tx_queues);
909 txq = dev->data->tx_queues[tx_queue_id];
911 PMD_DRV_LOG(ERR, "TX queue %u is not available",
916 q_ids[0] = txq->reg_idx;
917 q_teids[0] = txq->q_teid;
919 /* Fix me, we assume TC always 0 here */
920 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
921 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
922 if (status != ICE_SUCCESS) {
923 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
927 txq->tx_rel_mbufs(txq);
928 ice_reset_tx_queue(txq);
929 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
935 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
937 struct ice_rx_queue *rxq;
939 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
940 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
944 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
946 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
950 rxq->rx_rel_mbufs(rxq);
956 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
958 struct ice_tx_queue *txq;
959 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
960 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
961 struct ice_vsi *vsi = pf->main_vsi;
962 enum ice_status status;
965 uint16_t q_handle = tx_queue_id;
969 PMD_DRV_LOG(ERR, "TX queue %u is not available",
975 q_ids[0] = txq->reg_idx;
976 q_teids[0] = txq->q_teid;
978 /* Fix me, we assume TC always 0 here */
979 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
980 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
981 if (status != ICE_SUCCESS) {
982 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
986 txq->tx_rel_mbufs(txq);
992 ice_rx_queue_setup(struct rte_eth_dev *dev,
995 unsigned int socket_id,
996 const struct rte_eth_rxconf *rx_conf,
997 struct rte_mempool *mp)
999 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1000 struct ice_adapter *ad =
1001 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1002 struct ice_vsi *vsi = pf->main_vsi;
1003 struct ice_rx_queue *rxq;
1004 const struct rte_memzone *rz;
1007 int use_def_burst_func = 1;
1009 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1010 nb_desc > ICE_MAX_RING_DESC ||
1011 nb_desc < ICE_MIN_RING_DESC) {
1012 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1013 "invalid", nb_desc);
1017 /* Free memory if needed */
1018 if (dev->data->rx_queues[queue_idx]) {
1019 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1020 dev->data->rx_queues[queue_idx] = NULL;
1023 /* Allocate the rx queue data structure */
1024 rxq = rte_zmalloc_socket(NULL,
1025 sizeof(struct ice_rx_queue),
1026 RTE_CACHE_LINE_SIZE,
1029 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1030 "rx queue data structure");
1034 rxq->nb_rx_desc = nb_desc;
1035 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1036 rxq->queue_id = queue_idx;
1038 rxq->reg_idx = vsi->base_queue + queue_idx;
1039 rxq->port_id = dev->data->port_id;
1040 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1041 rxq->crc_len = RTE_ETHER_CRC_LEN;
1045 rxq->drop_en = rx_conf->rx_drop_en;
1047 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1048 rxq->proto_xtr = pf->proto_xtr != NULL ?
1049 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1051 /* Allocate the maximun number of RX ring hardware descriptor. */
1052 len = ICE_MAX_RING_DESC;
1055 * Allocating a little more memory because vectorized/bulk_alloc Rx
1056 * functions doesn't check boundaries each time.
1058 len += ICE_RX_MAX_BURST;
1060 /* Allocate the maximum number of RX ring hardware descriptor. */
1061 ring_size = sizeof(union ice_rx_flex_desc) * len;
1062 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1063 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1064 ring_size, ICE_RING_BASE_ALIGN,
1067 ice_rx_queue_release(rxq);
1068 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1072 /* Zero all the descriptors in the ring. */
1073 memset(rz->addr, 0, ring_size);
1075 rxq->rx_ring_dma = rz->iova;
1076 rxq->rx_ring = rz->addr;
1078 /* always reserve more for bulk alloc */
1079 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1081 /* Allocate the software ring. */
1082 rxq->sw_ring = rte_zmalloc_socket(NULL,
1083 sizeof(struct ice_rx_entry) * len,
1084 RTE_CACHE_LINE_SIZE,
1086 if (!rxq->sw_ring) {
1087 ice_rx_queue_release(rxq);
1088 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1092 ice_reset_rx_queue(rxq);
1094 dev->data->rx_queues[queue_idx] = rxq;
1095 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1097 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1099 if (!use_def_burst_func) {
1100 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1101 "satisfied. Rx Burst Bulk Alloc function will be "
1102 "used on port=%d, queue=%d.",
1103 rxq->port_id, rxq->queue_id);
1105 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1106 "not satisfied, Scattered Rx is requested. "
1107 "on port=%d, queue=%d.",
1108 rxq->port_id, rxq->queue_id);
1109 ad->rx_bulk_alloc_allowed = false;
1116 ice_rx_queue_release(void *rxq)
1118 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1121 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1126 rte_free(q->sw_ring);
1131 ice_tx_queue_setup(struct rte_eth_dev *dev,
1134 unsigned int socket_id,
1135 const struct rte_eth_txconf *tx_conf)
1137 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1138 struct ice_vsi *vsi = pf->main_vsi;
1139 struct ice_tx_queue *txq;
1140 const struct rte_memzone *tz;
1142 uint16_t tx_rs_thresh, tx_free_thresh;
1145 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1147 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1148 nb_desc > ICE_MAX_RING_DESC ||
1149 nb_desc < ICE_MIN_RING_DESC) {
1150 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1151 "invalid", nb_desc);
1156 * The following two parameters control the setting of the RS bit on
1157 * transmit descriptors. TX descriptors will have their RS bit set
1158 * after txq->tx_rs_thresh descriptors have been used. The TX
1159 * descriptor ring will be cleaned after txq->tx_free_thresh
1160 * descriptors are used or if the number of descriptors required to
1161 * transmit a packet is greater than the number of free TX descriptors.
1163 * The following constraints must be satisfied:
1164 * - tx_rs_thresh must be greater than 0.
1165 * - tx_rs_thresh must be less than the size of the ring minus 2.
1166 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1167 * - tx_rs_thresh must be a divisor of the ring size.
1168 * - tx_free_thresh must be greater than 0.
1169 * - tx_free_thresh must be less than the size of the ring minus 3.
1170 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1172 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1173 * race condition, hence the maximum threshold constraints. When set
1174 * to zero use default values.
1176 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1177 tx_conf->tx_free_thresh :
1178 ICE_DEFAULT_TX_FREE_THRESH);
1179 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1181 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1182 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1183 if (tx_conf->tx_rs_thresh)
1184 tx_rs_thresh = tx_conf->tx_rs_thresh;
1185 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1186 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1187 "exceed nb_desc. (tx_rs_thresh=%u "
1188 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1189 (unsigned int)tx_rs_thresh,
1190 (unsigned int)tx_free_thresh,
1191 (unsigned int)nb_desc,
1192 (int)dev->data->port_id,
1196 if (tx_rs_thresh >= (nb_desc - 2)) {
1197 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1198 "number of TX descriptors minus 2. "
1199 "(tx_rs_thresh=%u port=%d queue=%d)",
1200 (unsigned int)tx_rs_thresh,
1201 (int)dev->data->port_id,
1205 if (tx_free_thresh >= (nb_desc - 3)) {
1206 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1207 "tx_free_thresh must be less than the "
1208 "number of TX descriptors minus 3. "
1209 "(tx_free_thresh=%u port=%d queue=%d)",
1210 (unsigned int)tx_free_thresh,
1211 (int)dev->data->port_id,
1215 if (tx_rs_thresh > tx_free_thresh) {
1216 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1217 "equal to tx_free_thresh. (tx_free_thresh=%u"
1218 " tx_rs_thresh=%u port=%d queue=%d)",
1219 (unsigned int)tx_free_thresh,
1220 (unsigned int)tx_rs_thresh,
1221 (int)dev->data->port_id,
1225 if ((nb_desc % tx_rs_thresh) != 0) {
1226 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1227 "number of TX descriptors. (tx_rs_thresh=%u"
1228 " port=%d queue=%d)",
1229 (unsigned int)tx_rs_thresh,
1230 (int)dev->data->port_id,
1234 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1235 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1236 "tx_rs_thresh is greater than 1. "
1237 "(tx_rs_thresh=%u port=%d queue=%d)",
1238 (unsigned int)tx_rs_thresh,
1239 (int)dev->data->port_id,
1244 /* Free memory if needed. */
1245 if (dev->data->tx_queues[queue_idx]) {
1246 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1247 dev->data->tx_queues[queue_idx] = NULL;
1250 /* Allocate the TX queue data structure. */
1251 txq = rte_zmalloc_socket(NULL,
1252 sizeof(struct ice_tx_queue),
1253 RTE_CACHE_LINE_SIZE,
1256 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1257 "tx queue structure");
1261 /* Allocate TX hardware ring descriptors. */
1262 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1263 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1264 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1265 ring_size, ICE_RING_BASE_ALIGN,
1268 ice_tx_queue_release(txq);
1269 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1273 txq->nb_tx_desc = nb_desc;
1274 txq->tx_rs_thresh = tx_rs_thresh;
1275 txq->tx_free_thresh = tx_free_thresh;
1276 txq->pthresh = tx_conf->tx_thresh.pthresh;
1277 txq->hthresh = tx_conf->tx_thresh.hthresh;
1278 txq->wthresh = tx_conf->tx_thresh.wthresh;
1279 txq->queue_id = queue_idx;
1281 txq->reg_idx = vsi->base_queue + queue_idx;
1282 txq->port_id = dev->data->port_id;
1283 txq->offloads = offloads;
1285 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1287 txq->tx_ring_dma = tz->iova;
1288 txq->tx_ring = tz->addr;
1290 /* Allocate software ring */
1292 rte_zmalloc_socket(NULL,
1293 sizeof(struct ice_tx_entry) * nb_desc,
1294 RTE_CACHE_LINE_SIZE,
1296 if (!txq->sw_ring) {
1297 ice_tx_queue_release(txq);
1298 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1302 ice_reset_tx_queue(txq);
1304 dev->data->tx_queues[queue_idx] = txq;
1305 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1306 ice_set_tx_function_flag(dev, txq);
1312 ice_tx_queue_release(void *txq)
1314 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1317 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1322 rte_free(q->sw_ring);
1327 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1328 struct rte_eth_rxq_info *qinfo)
1330 struct ice_rx_queue *rxq;
1332 rxq = dev->data->rx_queues[queue_id];
1334 qinfo->mp = rxq->mp;
1335 qinfo->scattered_rx = dev->data->scattered_rx;
1336 qinfo->nb_desc = rxq->nb_rx_desc;
1338 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1339 qinfo->conf.rx_drop_en = rxq->drop_en;
1340 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1344 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1345 struct rte_eth_txq_info *qinfo)
1347 struct ice_tx_queue *txq;
1349 txq = dev->data->tx_queues[queue_id];
1351 qinfo->nb_desc = txq->nb_tx_desc;
1353 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1354 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1355 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1357 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1358 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1359 qinfo->conf.offloads = txq->offloads;
1360 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1364 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1366 #define ICE_RXQ_SCAN_INTERVAL 4
1367 volatile union ice_rx_flex_desc *rxdp;
1368 struct ice_rx_queue *rxq;
1371 rxq = dev->data->rx_queues[rx_queue_id];
1372 rxdp = &rxq->rx_ring[rxq->rx_tail];
1373 while ((desc < rxq->nb_rx_desc) &&
1374 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1375 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1377 * Check the DD bit of a rx descriptor of each 4 in a group,
1378 * to avoid checking too frequently and downgrading performance
1381 desc += ICE_RXQ_SCAN_INTERVAL;
1382 rxdp += ICE_RXQ_SCAN_INTERVAL;
1383 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1384 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1385 desc - rxq->nb_rx_desc]);
1391 #define ICE_RX_FLEX_ERR0_BITS \
1392 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1393 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1394 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1395 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1396 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1397 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1399 /* Rx L3/L4 checksum */
1400 static inline uint64_t
1401 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1405 /* check if HW has decoded the packet and checksum */
1406 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1409 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1410 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1414 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1415 flags |= PKT_RX_IP_CKSUM_BAD;
1417 flags |= PKT_RX_IP_CKSUM_GOOD;
1419 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1420 flags |= PKT_RX_L4_CKSUM_BAD;
1422 flags |= PKT_RX_L4_CKSUM_GOOD;
1424 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1425 flags |= PKT_RX_EIP_CKSUM_BAD;
1431 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1433 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1434 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1435 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1437 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1438 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1439 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1444 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1445 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1446 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1447 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1448 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1449 mb->vlan_tci_outer = mb->vlan_tci;
1450 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1451 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1452 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1453 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1455 mb->vlan_tci_outer = 0;
1458 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1459 mb->vlan_tci, mb->vlan_tci_outer);
1462 #define ICE_LOOK_AHEAD 8
1463 #if (ICE_LOOK_AHEAD != 8)
1464 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1467 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1469 volatile union ice_rx_flex_desc *rxdp;
1470 struct ice_rx_entry *rxep;
1471 struct rte_mbuf *mb;
1474 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1475 int32_t i, j, nb_rx = 0;
1476 uint64_t pkt_flags = 0;
1477 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1479 rxdp = &rxq->rx_ring[rxq->rx_tail];
1480 rxep = &rxq->sw_ring[rxq->rx_tail];
1482 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1484 /* Make sure there is at least 1 packet to receive */
1485 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1489 * Scan LOOK_AHEAD descriptors at a time to determine which
1490 * descriptors reference packets that are ready to be received.
1492 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1493 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1494 /* Read desc statuses backwards to avoid race condition */
1495 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1496 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1500 /* Compute how many status bits were set */
1501 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1502 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1506 /* Translate descriptor info to mbuf parameters */
1507 for (j = 0; j < nb_dd; j++) {
1509 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1510 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1511 mb->data_len = pkt_len;
1512 mb->pkt_len = pkt_len;
1514 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1515 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1516 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1517 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1518 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1519 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1521 mb->ol_flags |= pkt_flags;
1524 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1525 rxq->rx_stage[i + j] = rxep[j].mbuf;
1527 if (nb_dd != ICE_LOOK_AHEAD)
1531 /* Clear software ring entries */
1532 for (i = 0; i < nb_rx; i++)
1533 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1535 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1536 "port_id=%u, queue_id=%u, nb_rx=%d",
1537 rxq->port_id, rxq->queue_id, nb_rx);
1542 static inline uint16_t
1543 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1544 struct rte_mbuf **rx_pkts,
1548 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1550 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1552 for (i = 0; i < nb_pkts; i++)
1553 rx_pkts[i] = stage[i];
1555 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1556 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1562 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1564 volatile union ice_rx_flex_desc *rxdp;
1565 struct ice_rx_entry *rxep;
1566 struct rte_mbuf *mb;
1567 uint16_t alloc_idx, i;
1571 /* Allocate buffers in bulk */
1572 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1573 (rxq->rx_free_thresh - 1));
1574 rxep = &rxq->sw_ring[alloc_idx];
1575 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1576 rxq->rx_free_thresh);
1577 if (unlikely(diag != 0)) {
1578 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1582 rxdp = &rxq->rx_ring[alloc_idx];
1583 for (i = 0; i < rxq->rx_free_thresh; i++) {
1584 if (likely(i < (rxq->rx_free_thresh - 1)))
1585 /* Prefetch next mbuf */
1586 rte_prefetch0(rxep[i + 1].mbuf);
1589 rte_mbuf_refcnt_set(mb, 1);
1591 mb->data_off = RTE_PKTMBUF_HEADROOM;
1593 mb->port = rxq->port_id;
1594 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1595 rxdp[i].read.hdr_addr = 0;
1596 rxdp[i].read.pkt_addr = dma_addr;
1599 /* Update rx tail regsiter */
1600 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1602 rxq->rx_free_trigger =
1603 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1604 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1605 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1610 static inline uint16_t
1611 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1613 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1615 struct rte_eth_dev *dev;
1620 if (rxq->rx_nb_avail)
1621 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1623 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1624 rxq->rx_next_avail = 0;
1625 rxq->rx_nb_avail = nb_rx;
1626 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1628 if (rxq->rx_tail > rxq->rx_free_trigger) {
1629 if (ice_rx_alloc_bufs(rxq) != 0) {
1632 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1633 dev->data->rx_mbuf_alloc_failed +=
1634 rxq->rx_free_thresh;
1635 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1636 "port_id=%u, queue_id=%u",
1637 rxq->port_id, rxq->queue_id);
1638 rxq->rx_nb_avail = 0;
1639 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1640 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1641 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1647 if (rxq->rx_tail >= rxq->nb_rx_desc)
1650 if (rxq->rx_nb_avail)
1651 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1657 ice_recv_pkts_bulk_alloc(void *rx_queue,
1658 struct rte_mbuf **rx_pkts,
1665 if (unlikely(nb_pkts == 0))
1668 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1669 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1672 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1673 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1674 nb_rx = (uint16_t)(nb_rx + count);
1675 nb_pkts = (uint16_t)(nb_pkts - count);
1684 ice_recv_scattered_pkts(void *rx_queue,
1685 struct rte_mbuf **rx_pkts,
1688 struct ice_rx_queue *rxq = rx_queue;
1689 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1690 volatile union ice_rx_flex_desc *rxdp;
1691 union ice_rx_flex_desc rxd;
1692 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1693 struct ice_rx_entry *rxe;
1694 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1695 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1696 struct rte_mbuf *nmb; /* new allocated mbuf */
1697 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1698 uint16_t rx_id = rxq->rx_tail;
1700 uint16_t nb_hold = 0;
1701 uint16_t rx_packet_len;
1702 uint16_t rx_stat_err0;
1705 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1706 struct rte_eth_dev *dev;
1708 while (nb_rx < nb_pkts) {
1709 rxdp = &rx_ring[rx_id];
1710 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1712 /* Check the DD bit first */
1713 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1717 nmb = rte_mbuf_raw_alloc(rxq->mp);
1718 if (unlikely(!nmb)) {
1719 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1720 dev->data->rx_mbuf_alloc_failed++;
1723 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1726 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1728 if (unlikely(rx_id == rxq->nb_rx_desc))
1731 /* Prefetch next mbuf */
1732 rte_prefetch0(sw_ring[rx_id].mbuf);
1735 * When next RX descriptor is on a cache line boundary,
1736 * prefetch the next 4 RX descriptors and next 8 pointers
1739 if ((rx_id & 0x3) == 0) {
1740 rte_prefetch0(&rx_ring[rx_id]);
1741 rte_prefetch0(&sw_ring[rx_id]);
1747 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1749 /* Set data buffer address and data length of the mbuf */
1750 rxdp->read.hdr_addr = 0;
1751 rxdp->read.pkt_addr = dma_addr;
1752 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1753 ICE_RX_FLX_DESC_PKT_LEN_M;
1754 rxm->data_len = rx_packet_len;
1755 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1758 * If this is the first buffer of the received packet, set the
1759 * pointer to the first mbuf of the packet and initialize its
1760 * context. Otherwise, update the total length and the number
1761 * of segments of the current scattered packet, and update the
1762 * pointer to the last mbuf of the current packet.
1766 first_seg->nb_segs = 1;
1767 first_seg->pkt_len = rx_packet_len;
1769 first_seg->pkt_len =
1770 (uint16_t)(first_seg->pkt_len +
1772 first_seg->nb_segs++;
1773 last_seg->next = rxm;
1777 * If this is not the last buffer of the received packet,
1778 * update the pointer to the last mbuf of the current scattered
1779 * packet and continue to parse the RX ring.
1781 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1787 * This is the last buffer of the received packet. If the CRC
1788 * is not stripped by the hardware:
1789 * - Subtract the CRC length from the total packet length.
1790 * - If the last buffer only contains the whole CRC or a part
1791 * of it, free the mbuf associated to the last buffer. If part
1792 * of the CRC is also contained in the previous mbuf, subtract
1793 * the length of that CRC part from the data length of the
1797 if (unlikely(rxq->crc_len > 0)) {
1798 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1799 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1800 rte_pktmbuf_free_seg(rxm);
1801 first_seg->nb_segs--;
1802 last_seg->data_len =
1803 (uint16_t)(last_seg->data_len -
1804 (RTE_ETHER_CRC_LEN - rx_packet_len));
1805 last_seg->next = NULL;
1807 rxm->data_len = (uint16_t)(rx_packet_len -
1811 first_seg->port = rxq->port_id;
1812 first_seg->ol_flags = 0;
1813 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1814 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1815 ice_rxd_to_vlan_tci(first_seg, &rxd);
1816 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1817 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1818 first_seg->ol_flags |= pkt_flags;
1819 /* Prefetch data of first segment, if configured to do so. */
1820 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1821 first_seg->data_off));
1822 rx_pkts[nb_rx++] = first_seg;
1826 /* Record index of the next RX descriptor to probe. */
1827 rxq->rx_tail = rx_id;
1828 rxq->pkt_first_seg = first_seg;
1829 rxq->pkt_last_seg = last_seg;
1832 * If the number of free RX descriptors is greater than the RX free
1833 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1834 * register. Update the RDT with the value of the last processed RX
1835 * descriptor minus 1, to guarantee that the RDT register is never
1836 * equal to the RDH register, which creates a "full" ring situtation
1837 * from the hardware point of view.
1839 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1840 if (nb_hold > rxq->rx_free_thresh) {
1841 rx_id = (uint16_t)(rx_id == 0 ?
1842 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1843 /* write TAIL register */
1844 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1847 rxq->nb_rx_hold = nb_hold;
1849 /* return received packet in the burst */
1854 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1856 struct ice_adapter *ad =
1857 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1858 const uint32_t *ptypes;
1860 static const uint32_t ptypes_os[] = {
1861 /* refers to ice_get_default_pkt_type() */
1863 RTE_PTYPE_L2_ETHER_TIMESYNC,
1864 RTE_PTYPE_L2_ETHER_LLDP,
1865 RTE_PTYPE_L2_ETHER_ARP,
1866 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1867 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1870 RTE_PTYPE_L4_NONFRAG,
1874 RTE_PTYPE_TUNNEL_GRENAT,
1875 RTE_PTYPE_TUNNEL_IP,
1876 RTE_PTYPE_INNER_L2_ETHER,
1877 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1878 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1879 RTE_PTYPE_INNER_L4_FRAG,
1880 RTE_PTYPE_INNER_L4_ICMP,
1881 RTE_PTYPE_INNER_L4_NONFRAG,
1882 RTE_PTYPE_INNER_L4_SCTP,
1883 RTE_PTYPE_INNER_L4_TCP,
1884 RTE_PTYPE_INNER_L4_UDP,
1888 static const uint32_t ptypes_comms[] = {
1889 /* refers to ice_get_default_pkt_type() */
1891 RTE_PTYPE_L2_ETHER_TIMESYNC,
1892 RTE_PTYPE_L2_ETHER_LLDP,
1893 RTE_PTYPE_L2_ETHER_ARP,
1894 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1895 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1898 RTE_PTYPE_L4_NONFRAG,
1902 RTE_PTYPE_TUNNEL_GRENAT,
1903 RTE_PTYPE_TUNNEL_IP,
1904 RTE_PTYPE_INNER_L2_ETHER,
1905 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1906 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1907 RTE_PTYPE_INNER_L4_FRAG,
1908 RTE_PTYPE_INNER_L4_ICMP,
1909 RTE_PTYPE_INNER_L4_NONFRAG,
1910 RTE_PTYPE_INNER_L4_SCTP,
1911 RTE_PTYPE_INNER_L4_TCP,
1912 RTE_PTYPE_INNER_L4_UDP,
1913 RTE_PTYPE_TUNNEL_GTPC,
1914 RTE_PTYPE_TUNNEL_GTPU,
1915 RTE_PTYPE_L2_ETHER_PPPOE,
1919 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1920 ptypes = ptypes_comms;
1924 if (dev->rx_pkt_burst == ice_recv_pkts ||
1925 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1926 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1930 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1931 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1932 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1933 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1941 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1943 volatile union ice_rx_flex_desc *rxdp;
1944 struct ice_rx_queue *rxq = rx_queue;
1947 if (unlikely(offset >= rxq->nb_rx_desc))
1950 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1951 return RTE_ETH_RX_DESC_UNAVAIL;
1953 desc = rxq->rx_tail + offset;
1954 if (desc >= rxq->nb_rx_desc)
1955 desc -= rxq->nb_rx_desc;
1957 rxdp = &rxq->rx_ring[desc];
1958 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1959 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1960 return RTE_ETH_RX_DESC_DONE;
1962 return RTE_ETH_RX_DESC_AVAIL;
1966 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1968 struct ice_tx_queue *txq = tx_queue;
1969 volatile uint64_t *status;
1970 uint64_t mask, expect;
1973 if (unlikely(offset >= txq->nb_tx_desc))
1976 desc = txq->tx_tail + offset;
1977 /* go to next desc that has the RS bit */
1978 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1980 if (desc >= txq->nb_tx_desc) {
1981 desc -= txq->nb_tx_desc;
1982 if (desc >= txq->nb_tx_desc)
1983 desc -= txq->nb_tx_desc;
1986 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1987 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1988 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1989 ICE_TXD_QW1_DTYPE_S);
1990 if ((*status & mask) == expect)
1991 return RTE_ETH_TX_DESC_DONE;
1993 return RTE_ETH_TX_DESC_FULL;
1997 ice_free_queues(struct rte_eth_dev *dev)
2001 PMD_INIT_FUNC_TRACE();
2003 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2004 if (!dev->data->rx_queues[i])
2006 ice_rx_queue_release(dev->data->rx_queues[i]);
2007 dev->data->rx_queues[i] = NULL;
2008 rte_eth_dma_zone_free(dev, "rx_ring", i);
2010 dev->data->nb_rx_queues = 0;
2012 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2013 if (!dev->data->tx_queues[i])
2015 ice_tx_queue_release(dev->data->tx_queues[i]);
2016 dev->data->tx_queues[i] = NULL;
2017 rte_eth_dma_zone_free(dev, "tx_ring", i);
2019 dev->data->nb_tx_queues = 0;
2022 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2023 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2026 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2028 struct ice_tx_queue *txq;
2029 const struct rte_memzone *tz = NULL;
2031 struct rte_eth_dev *dev;
2034 PMD_DRV_LOG(ERR, "PF is not available");
2038 dev = pf->adapter->eth_dev;
2040 /* Allocate the TX queue data structure. */
2041 txq = rte_zmalloc_socket("ice fdir tx queue",
2042 sizeof(struct ice_tx_queue),
2043 RTE_CACHE_LINE_SIZE,
2046 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2047 "tx queue structure.");
2051 /* Allocate TX hardware ring descriptors. */
2052 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2053 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2055 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2056 ICE_FDIR_QUEUE_ID, ring_size,
2057 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2059 ice_tx_queue_release(txq);
2060 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2064 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2065 txq->queue_id = ICE_FDIR_QUEUE_ID;
2066 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2067 txq->vsi = pf->fdir.fdir_vsi;
2069 txq->tx_ring_dma = tz->iova;
2070 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2072 * don't need to allocate software ring and reset for the fdir
2073 * program queue just set the queue has been configured.
2078 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2084 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2086 struct ice_rx_queue *rxq;
2087 const struct rte_memzone *rz = NULL;
2089 struct rte_eth_dev *dev;
2092 PMD_DRV_LOG(ERR, "PF is not available");
2096 dev = pf->adapter->eth_dev;
2098 /* Allocate the RX queue data structure. */
2099 rxq = rte_zmalloc_socket("ice fdir rx queue",
2100 sizeof(struct ice_rx_queue),
2101 RTE_CACHE_LINE_SIZE,
2104 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2105 "rx queue structure.");
2109 /* Allocate RX hardware ring descriptors. */
2110 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2111 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2113 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2114 ICE_FDIR_QUEUE_ID, ring_size,
2115 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2117 ice_rx_queue_release(rxq);
2118 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2122 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2123 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2124 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2125 rxq->vsi = pf->fdir.fdir_vsi;
2127 rxq->rx_ring_dma = rz->iova;
2128 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2129 sizeof(union ice_32byte_rx_desc));
2130 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2133 * Don't need to allocate software ring and reset for the fdir
2134 * rx queue, just set the queue has been configured.
2139 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2145 ice_recv_pkts(void *rx_queue,
2146 struct rte_mbuf **rx_pkts,
2149 struct ice_rx_queue *rxq = rx_queue;
2150 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2151 volatile union ice_rx_flex_desc *rxdp;
2152 union ice_rx_flex_desc rxd;
2153 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2154 struct ice_rx_entry *rxe;
2155 struct rte_mbuf *nmb; /* new allocated mbuf */
2156 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2157 uint16_t rx_id = rxq->rx_tail;
2159 uint16_t nb_hold = 0;
2160 uint16_t rx_packet_len;
2161 uint16_t rx_stat_err0;
2164 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2165 struct rte_eth_dev *dev;
2167 while (nb_rx < nb_pkts) {
2168 rxdp = &rx_ring[rx_id];
2169 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2171 /* Check the DD bit first */
2172 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2176 nmb = rte_mbuf_raw_alloc(rxq->mp);
2177 if (unlikely(!nmb)) {
2178 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2179 dev->data->rx_mbuf_alloc_failed++;
2182 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2185 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2187 if (unlikely(rx_id == rxq->nb_rx_desc))
2192 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2195 * fill the read format of descriptor with physic address in
2196 * new allocated mbuf: nmb
2198 rxdp->read.hdr_addr = 0;
2199 rxdp->read.pkt_addr = dma_addr;
2201 /* calculate rx_packet_len of the received pkt */
2202 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2203 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2205 /* fill old mbuf with received descriptor: rxd */
2206 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2207 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2210 rxm->pkt_len = rx_packet_len;
2211 rxm->data_len = rx_packet_len;
2212 rxm->port = rxq->port_id;
2213 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2214 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2215 ice_rxd_to_vlan_tci(rxm, &rxd);
2216 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2217 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2218 rxm->ol_flags |= pkt_flags;
2219 /* copy old mbuf to rx_pkts */
2220 rx_pkts[nb_rx++] = rxm;
2222 rxq->rx_tail = rx_id;
2224 * If the number of free RX descriptors is greater than the RX free
2225 * threshold of the queue, advance the receive tail register of queue.
2226 * Update that register with the value of the last processed RX
2227 * descriptor minus 1.
2229 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2230 if (nb_hold > rxq->rx_free_thresh) {
2231 rx_id = (uint16_t)(rx_id == 0 ?
2232 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2233 /* write TAIL register */
2234 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2237 rxq->nb_rx_hold = nb_hold;
2239 /* return received packet in the burst */
2244 ice_parse_tunneling_params(uint64_t ol_flags,
2245 union ice_tx_offload tx_offload,
2246 uint32_t *cd_tunneling)
2248 /* EIPT: External (outer) IP header type */
2249 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2250 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2251 else if (ol_flags & PKT_TX_OUTER_IPV4)
2252 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2253 else if (ol_flags & PKT_TX_OUTER_IPV6)
2254 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2256 /* EIPLEN: External (outer) IP header length, in DWords */
2257 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2258 ICE_TXD_CTX_QW0_EIPLEN_S;
2260 /* L4TUNT: L4 Tunneling Type */
2261 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2262 case PKT_TX_TUNNEL_IPIP:
2263 /* for non UDP / GRE tunneling, set to 00b */
2265 case PKT_TX_TUNNEL_VXLAN:
2266 case PKT_TX_TUNNEL_GTP:
2267 case PKT_TX_TUNNEL_GENEVE:
2268 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2270 case PKT_TX_TUNNEL_GRE:
2271 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2274 PMD_TX_LOG(ERR, "Tunnel type not supported");
2278 /* L4TUNLEN: L4 Tunneling Length, in Words
2280 * We depend on app to set rte_mbuf.l2_len correctly.
2281 * For IP in GRE it should be set to the length of the GRE
2283 * For MAC in GRE or MAC in UDP it should be set to the length
2284 * of the GRE or UDP headers plus the inner MAC up to including
2285 * its last Ethertype.
2286 * If MPLS labels exists, it should include them as well.
2288 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2289 ICE_TXD_CTX_QW0_NATLEN_S;
2291 if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2292 (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2293 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2294 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2298 ice_txd_enable_checksum(uint64_t ol_flags,
2300 uint32_t *td_offset,
2301 union ice_tx_offload tx_offload)
2304 if (ol_flags & PKT_TX_TUNNEL_MASK)
2305 *td_offset |= (tx_offload.outer_l2_len >> 1)
2306 << ICE_TX_DESC_LEN_MACLEN_S;
2308 *td_offset |= (tx_offload.l2_len >> 1)
2309 << ICE_TX_DESC_LEN_MACLEN_S;
2311 /* Enable L3 checksum offloads */
2312 if (ol_flags & PKT_TX_IP_CKSUM) {
2313 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2314 *td_offset |= (tx_offload.l3_len >> 2) <<
2315 ICE_TX_DESC_LEN_IPLEN_S;
2316 } else if (ol_flags & PKT_TX_IPV4) {
2317 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2318 *td_offset |= (tx_offload.l3_len >> 2) <<
2319 ICE_TX_DESC_LEN_IPLEN_S;
2320 } else if (ol_flags & PKT_TX_IPV6) {
2321 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2322 *td_offset |= (tx_offload.l3_len >> 2) <<
2323 ICE_TX_DESC_LEN_IPLEN_S;
2326 if (ol_flags & PKT_TX_TCP_SEG) {
2327 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2328 *td_offset |= (tx_offload.l4_len >> 2) <<
2329 ICE_TX_DESC_LEN_L4_LEN_S;
2333 /* Enable L4 checksum offloads */
2334 switch (ol_flags & PKT_TX_L4_MASK) {
2335 case PKT_TX_TCP_CKSUM:
2336 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2337 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2338 ICE_TX_DESC_LEN_L4_LEN_S;
2340 case PKT_TX_SCTP_CKSUM:
2341 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2342 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2343 ICE_TX_DESC_LEN_L4_LEN_S;
2345 case PKT_TX_UDP_CKSUM:
2346 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2347 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2348 ICE_TX_DESC_LEN_L4_LEN_S;
2356 ice_xmit_cleanup(struct ice_tx_queue *txq)
2358 struct ice_tx_entry *sw_ring = txq->sw_ring;
2359 volatile struct ice_tx_desc *txd = txq->tx_ring;
2360 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2361 uint16_t nb_tx_desc = txq->nb_tx_desc;
2362 uint16_t desc_to_clean_to;
2363 uint16_t nb_tx_to_clean;
2365 /* Determine the last descriptor needing to be cleaned */
2366 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2367 if (desc_to_clean_to >= nb_tx_desc)
2368 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2370 /* Check to make sure the last descriptor to clean is done */
2371 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2372 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2373 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2374 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2375 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2377 txq->port_id, txq->queue_id,
2378 txd[desc_to_clean_to].cmd_type_offset_bsz);
2379 /* Failed to clean any descriptors */
2383 /* Figure out how many descriptors will be cleaned */
2384 if (last_desc_cleaned > desc_to_clean_to)
2385 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2388 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2391 /* The last descriptor to clean is done, so that means all the
2392 * descriptors from the last descriptor that was cleaned
2393 * up to the last descriptor with the RS bit set
2394 * are done. Only reset the threshold descriptor.
2396 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2398 /* Update the txq to reflect the last descriptor that was cleaned */
2399 txq->last_desc_cleaned = desc_to_clean_to;
2400 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2405 /* Construct the tx flags */
2406 static inline uint64_t
2407 ice_build_ctob(uint32_t td_cmd,
2412 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2413 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2414 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2415 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2416 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2419 /* Check if the context descriptor is needed for TX offloading */
2420 static inline uint16_t
2421 ice_calc_context_desc(uint64_t flags)
2423 static uint64_t mask = PKT_TX_TCP_SEG |
2425 PKT_TX_OUTER_IP_CKSUM |
2428 return (flags & mask) ? 1 : 0;
2431 /* set ice TSO context descriptor */
2432 static inline uint64_t
2433 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2435 uint64_t ctx_desc = 0;
2436 uint32_t cd_cmd, hdr_len, cd_tso_len;
2438 if (!tx_offload.l4_len) {
2439 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2443 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2444 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2445 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2447 cd_cmd = ICE_TX_CTX_DESC_TSO;
2448 cd_tso_len = mbuf->pkt_len - hdr_len;
2449 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2450 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2451 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2456 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2457 #define ICE_MAX_DATA_PER_TXD \
2458 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2459 /* Calculate the number of TX descriptors needed for each pkt */
2460 static inline uint16_t
2461 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2463 struct rte_mbuf *txd = tx_pkt;
2466 while (txd != NULL) {
2467 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2475 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2477 struct ice_tx_queue *txq;
2478 volatile struct ice_tx_desc *tx_ring;
2479 volatile struct ice_tx_desc *txd;
2480 struct ice_tx_entry *sw_ring;
2481 struct ice_tx_entry *txe, *txn;
2482 struct rte_mbuf *tx_pkt;
2483 struct rte_mbuf *m_seg;
2484 uint32_t cd_tunneling_params;
2489 uint32_t td_cmd = 0;
2490 uint32_t td_offset = 0;
2491 uint32_t td_tag = 0;
2494 uint64_t buf_dma_addr;
2496 union ice_tx_offload tx_offload = {0};
2499 sw_ring = txq->sw_ring;
2500 tx_ring = txq->tx_ring;
2501 tx_id = txq->tx_tail;
2502 txe = &sw_ring[tx_id];
2504 /* Check if the descriptor ring needs to be cleaned. */
2505 if (txq->nb_tx_free < txq->tx_free_thresh)
2506 (void)ice_xmit_cleanup(txq);
2508 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2509 tx_pkt = *tx_pkts++;
2514 ol_flags = tx_pkt->ol_flags;
2515 tx_offload.l2_len = tx_pkt->l2_len;
2516 tx_offload.l3_len = tx_pkt->l3_len;
2517 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2518 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2519 tx_offload.l4_len = tx_pkt->l4_len;
2520 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2521 /* Calculate the number of context descriptors needed. */
2522 nb_ctx = ice_calc_context_desc(ol_flags);
2524 /* The number of descriptors that must be allocated for
2525 * a packet equals to the number of the segments of that
2526 * packet plus the number of context descriptor if needed.
2527 * Recalculate the needed tx descs when TSO enabled in case
2528 * the mbuf data size exceeds max data size that hw allows
2531 if (ol_flags & PKT_TX_TCP_SEG)
2532 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2535 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2536 tx_last = (uint16_t)(tx_id + nb_used - 1);
2539 if (tx_last >= txq->nb_tx_desc)
2540 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2542 if (nb_used > txq->nb_tx_free) {
2543 if (ice_xmit_cleanup(txq) != 0) {
2548 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2549 while (nb_used > txq->nb_tx_free) {
2550 if (ice_xmit_cleanup(txq) != 0) {
2559 /* Descriptor based VLAN insertion */
2560 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2561 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2562 td_tag = tx_pkt->vlan_tci;
2565 /* Fill in tunneling parameters if necessary */
2566 cd_tunneling_params = 0;
2567 if (ol_flags & PKT_TX_TUNNEL_MASK)
2568 ice_parse_tunneling_params(ol_flags, tx_offload,
2569 &cd_tunneling_params);
2571 /* Enable checksum offloading */
2572 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2573 ice_txd_enable_checksum(ol_flags, &td_cmd,
2574 &td_offset, tx_offload);
2577 /* Setup TX context descriptor if required */
2578 volatile struct ice_tx_ctx_desc *ctx_txd =
2579 (volatile struct ice_tx_ctx_desc *)
2581 uint16_t cd_l2tag2 = 0;
2582 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2584 txn = &sw_ring[txe->next_id];
2585 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2587 rte_pktmbuf_free_seg(txe->mbuf);
2591 if (ol_flags & PKT_TX_TCP_SEG)
2592 cd_type_cmd_tso_mss |=
2593 ice_set_tso_ctx(tx_pkt, tx_offload);
2595 ctx_txd->tunneling_params =
2596 rte_cpu_to_le_32(cd_tunneling_params);
2598 /* TX context descriptor based double VLAN insert */
2599 if (ol_flags & PKT_TX_QINQ) {
2600 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2601 cd_type_cmd_tso_mss |=
2602 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2603 ICE_TXD_CTX_QW1_CMD_S);
2605 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2607 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2609 txe->last_id = tx_last;
2610 tx_id = txe->next_id;
2616 txd = &tx_ring[tx_id];
2617 txn = &sw_ring[txe->next_id];
2620 rte_pktmbuf_free_seg(txe->mbuf);
2623 /* Setup TX Descriptor */
2624 slen = m_seg->data_len;
2625 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2627 while ((ol_flags & PKT_TX_TCP_SEG) &&
2628 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2629 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2630 txd->cmd_type_offset_bsz =
2631 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2632 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2633 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2634 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2635 ICE_TXD_QW1_TX_BUF_SZ_S) |
2636 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2638 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2639 slen -= ICE_MAX_DATA_PER_TXD;
2641 txe->last_id = tx_last;
2642 tx_id = txe->next_id;
2644 txd = &tx_ring[tx_id];
2645 txn = &sw_ring[txe->next_id];
2648 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2649 txd->cmd_type_offset_bsz =
2650 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2651 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2652 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2653 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2654 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2656 txe->last_id = tx_last;
2657 tx_id = txe->next_id;
2659 m_seg = m_seg->next;
2662 /* fill the last descriptor with End of Packet (EOP) bit */
2663 td_cmd |= ICE_TX_DESC_CMD_EOP;
2664 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2665 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2667 /* set RS bit on the last descriptor of one packet */
2668 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2669 PMD_TX_FREE_LOG(DEBUG,
2670 "Setting RS bit on TXD id="
2671 "%4u (port=%d queue=%d)",
2672 tx_last, txq->port_id, txq->queue_id);
2674 td_cmd |= ICE_TX_DESC_CMD_RS;
2676 /* Update txq RS bit counters */
2677 txq->nb_tx_used = 0;
2679 txd->cmd_type_offset_bsz |=
2680 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2684 /* update Tail register */
2685 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2686 txq->tx_tail = tx_id;
2691 static __rte_always_inline int
2692 ice_tx_free_bufs(struct ice_tx_queue *txq)
2694 struct ice_tx_entry *txep;
2697 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2698 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2699 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2702 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2704 for (i = 0; i < txq->tx_rs_thresh; i++)
2705 rte_prefetch0((txep + i)->mbuf);
2707 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2708 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2709 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2713 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2714 rte_pktmbuf_free_seg(txep->mbuf);
2719 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2720 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2721 if (txq->tx_next_dd >= txq->nb_tx_desc)
2722 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2724 return txq->tx_rs_thresh;
2728 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2731 struct ice_tx_entry *swr_ring = txq->sw_ring;
2732 uint16_t i, tx_last, tx_id;
2733 uint16_t nb_tx_free_last;
2734 uint16_t nb_tx_to_clean;
2737 /* Start free mbuf from the next of tx_tail */
2738 tx_last = txq->tx_tail;
2739 tx_id = swr_ring[tx_last].next_id;
2741 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2744 nb_tx_to_clean = txq->nb_tx_free;
2745 nb_tx_free_last = txq->nb_tx_free;
2747 free_cnt = txq->nb_tx_desc;
2749 /* Loop through swr_ring to count the amount of
2750 * freeable mubfs and packets.
2752 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2753 for (i = 0; i < nb_tx_to_clean &&
2754 pkt_cnt < free_cnt &&
2755 tx_id != tx_last; i++) {
2756 if (swr_ring[tx_id].mbuf != NULL) {
2757 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2758 swr_ring[tx_id].mbuf = NULL;
2761 * last segment in the packet,
2762 * increment packet count
2764 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2767 tx_id = swr_ring[tx_id].next_id;
2770 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2771 txq->nb_tx_free || tx_id == tx_last)
2774 if (pkt_cnt < free_cnt) {
2775 if (ice_xmit_cleanup(txq))
2778 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2779 nb_tx_free_last = txq->nb_tx_free;
2783 return (int)pkt_cnt;
2788 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2789 uint32_t free_cnt __rte_unused)
2796 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2801 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2802 free_cnt = txq->nb_tx_desc;
2804 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2806 for (i = 0; i < cnt; i += n) {
2807 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2810 n = ice_tx_free_bufs(txq);
2820 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2822 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2823 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2824 struct ice_adapter *ad =
2825 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2828 if (ad->tx_vec_allowed)
2829 return ice_tx_done_cleanup_vec(q, free_cnt);
2831 if (ad->tx_simple_allowed)
2832 return ice_tx_done_cleanup_simple(q, free_cnt);
2834 return ice_tx_done_cleanup_full(q, free_cnt);
2837 /* Populate 4 descriptors with data from 4 mbufs */
2839 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2844 for (i = 0; i < 4; i++, txdp++, pkts++) {
2845 dma_addr = rte_mbuf_data_iova(*pkts);
2846 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2847 txdp->cmd_type_offset_bsz =
2848 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2849 (*pkts)->data_len, 0);
2853 /* Populate 1 descriptor with data from 1 mbuf */
2855 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2859 dma_addr = rte_mbuf_data_iova(*pkts);
2860 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2861 txdp->cmd_type_offset_bsz =
2862 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2863 (*pkts)->data_len, 0);
2867 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2870 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2871 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2872 const int N_PER_LOOP = 4;
2873 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2874 int mainpart, leftover;
2878 * Process most of the packets in chunks of N pkts. Any
2879 * leftover packets will get processed one at a time.
2881 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2882 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2883 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2884 /* Copy N mbuf pointers to the S/W ring */
2885 for (j = 0; j < N_PER_LOOP; ++j)
2886 (txep + i + j)->mbuf = *(pkts + i + j);
2887 tx4(txdp + i, pkts + i);
2890 if (unlikely(leftover > 0)) {
2891 for (i = 0; i < leftover; ++i) {
2892 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2893 tx1(txdp + mainpart + i, pkts + mainpart + i);
2898 static inline uint16_t
2899 tx_xmit_pkts(struct ice_tx_queue *txq,
2900 struct rte_mbuf **tx_pkts,
2903 volatile struct ice_tx_desc *txr = txq->tx_ring;
2907 * Begin scanning the H/W ring for done descriptors when the number
2908 * of available descriptors drops below tx_free_thresh. For each done
2909 * descriptor, free the associated buffer.
2911 if (txq->nb_tx_free < txq->tx_free_thresh)
2912 ice_tx_free_bufs(txq);
2914 /* Use available descriptor only */
2915 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2916 if (unlikely(!nb_pkts))
2919 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2920 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2921 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2922 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2923 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2924 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2926 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2930 /* Fill hardware descriptor ring with mbuf data */
2931 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2932 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2934 /* Determin if RS bit needs to be set */
2935 if (txq->tx_tail > txq->tx_next_rs) {
2936 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2937 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2940 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2941 if (txq->tx_next_rs >= txq->nb_tx_desc)
2942 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2945 if (txq->tx_tail >= txq->nb_tx_desc)
2948 /* Update the tx tail register */
2949 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
2955 ice_xmit_pkts_simple(void *tx_queue,
2956 struct rte_mbuf **tx_pkts,
2961 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2962 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2966 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2969 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2970 &tx_pkts[nb_tx], num);
2971 nb_tx = (uint16_t)(nb_tx + ret);
2972 nb_pkts = (uint16_t)(nb_pkts - ret);
2981 ice_set_rx_function(struct rte_eth_dev *dev)
2983 PMD_INIT_FUNC_TRACE();
2984 struct ice_adapter *ad =
2985 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2987 struct ice_rx_queue *rxq;
2989 bool use_avx2 = false;
2991 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2992 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2993 ad->rx_vec_allowed = true;
2994 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2995 rxq = dev->data->rx_queues[i];
2996 if (rxq && ice_rxq_vec_setup(rxq)) {
2997 ad->rx_vec_allowed = false;
3002 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3003 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3007 ad->rx_vec_allowed = false;
3011 if (ad->rx_vec_allowed) {
3012 if (dev->data->scattered_rx) {
3014 "Using %sVector Scattered Rx (port %d).",
3015 use_avx2 ? "avx2 " : "",
3016 dev->data->port_id);
3017 dev->rx_pkt_burst = use_avx2 ?
3018 ice_recv_scattered_pkts_vec_avx2 :
3019 ice_recv_scattered_pkts_vec;
3021 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
3022 use_avx2 ? "avx2 " : "",
3023 dev->data->port_id);
3024 dev->rx_pkt_burst = use_avx2 ?
3025 ice_recv_pkts_vec_avx2 :
3033 if (dev->data->scattered_rx) {
3034 /* Set the non-LRO scattered function */
3036 "Using a Scattered function on port %d.",
3037 dev->data->port_id);
3038 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3039 } else if (ad->rx_bulk_alloc_allowed) {
3041 "Rx Burst Bulk Alloc Preconditions are "
3042 "satisfied. Rx Burst Bulk Alloc function "
3043 "will be used on port %d.",
3044 dev->data->port_id);
3045 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3048 "Rx Burst Bulk Alloc Preconditions are not "
3049 "satisfied, Normal Rx will be used on port %d.",
3050 dev->data->port_id);
3051 dev->rx_pkt_burst = ice_recv_pkts;
3055 static const struct {
3056 eth_rx_burst_t pkt_burst;
3058 } ice_rx_burst_infos[] = {
3059 { ice_recv_scattered_pkts, "Scalar Scattered" },
3060 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3061 { ice_recv_pkts, "Scalar" },
3063 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3064 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3065 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3066 { ice_recv_pkts_vec, "Vector SSE" },
3071 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3072 struct rte_eth_burst_mode *mode)
3074 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3078 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3079 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3080 snprintf(mode->info, sizeof(mode->info), "%s",
3081 ice_rx_burst_infos[i].info);
3091 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3093 struct ice_adapter *ad =
3094 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3096 /* Use a simple Tx queue if possible (only fast free is allowed) */
3097 ad->tx_simple_allowed =
3099 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3100 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3102 if (ad->tx_simple_allowed)
3103 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3107 "Simple Tx can NOT be enabled on Tx queue %u.",
3111 /*********************************************************************
3115 **********************************************************************/
3116 /* The default values of TSO MSS */
3117 #define ICE_MIN_TSO_MSS 64
3118 #define ICE_MAX_TSO_MSS 9728
3119 #define ICE_MAX_TSO_FRAME_SIZE 262144
3121 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3128 for (i = 0; i < nb_pkts; i++) {
3130 ol_flags = m->ol_flags;
3132 if (ol_flags & PKT_TX_TCP_SEG &&
3133 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3134 m->tso_segsz > ICE_MAX_TSO_MSS ||
3135 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3137 * MSS outside the range are considered malicious
3143 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3144 ret = rte_validate_tx_offload(m);
3150 ret = rte_net_intel_cksum_prepare(m);
3160 ice_set_tx_function(struct rte_eth_dev *dev)
3162 struct ice_adapter *ad =
3163 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3165 struct ice_tx_queue *txq;
3167 bool use_avx2 = false;
3169 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3170 if (!ice_tx_vec_dev_check(dev)) {
3171 ad->tx_vec_allowed = true;
3172 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3173 txq = dev->data->tx_queues[i];
3174 if (txq && ice_txq_vec_setup(txq)) {
3175 ad->tx_vec_allowed = false;
3180 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3181 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3185 ad->tx_vec_allowed = false;
3189 if (ad->tx_vec_allowed) {
3190 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3191 use_avx2 ? "avx2 " : "",
3192 dev->data->port_id);
3193 dev->tx_pkt_burst = use_avx2 ?
3194 ice_xmit_pkts_vec_avx2 :
3196 dev->tx_pkt_prepare = NULL;
3202 if (ad->tx_simple_allowed) {
3203 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3204 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3205 dev->tx_pkt_prepare = NULL;
3207 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3208 dev->tx_pkt_burst = ice_xmit_pkts;
3209 dev->tx_pkt_prepare = ice_prep_pkts;
3213 static const struct {
3214 eth_tx_burst_t pkt_burst;
3216 } ice_tx_burst_infos[] = {
3217 { ice_xmit_pkts_simple, "Scalar Simple" },
3218 { ice_xmit_pkts, "Scalar" },
3220 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3221 { ice_xmit_pkts_vec, "Vector SSE" },
3226 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3227 struct rte_eth_burst_mode *mode)
3229 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3233 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3234 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3235 snprintf(mode->info, sizeof(mode->info), "%s",
3236 ice_tx_burst_infos[i].info);
3245 /* For each value it means, datasheet of hardware can tell more details
3247 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3249 static inline uint32_t
3250 ice_get_default_pkt_type(uint16_t ptype)
3252 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3253 __rte_cache_aligned = {
3256 [1] = RTE_PTYPE_L2_ETHER,
3257 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3258 /* [3] - [5] reserved */
3259 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3260 /* [7] - [10] reserved */
3261 [11] = RTE_PTYPE_L2_ETHER_ARP,
3262 /* [12] - [21] reserved */
3264 /* Non tunneled IPv4 */
3265 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3267 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3268 RTE_PTYPE_L4_NONFRAG,
3269 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3272 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3274 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3276 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3280 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3281 RTE_PTYPE_TUNNEL_IP |
3282 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3283 RTE_PTYPE_INNER_L4_FRAG,
3284 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3285 RTE_PTYPE_TUNNEL_IP |
3286 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3287 RTE_PTYPE_INNER_L4_NONFRAG,
3288 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3289 RTE_PTYPE_TUNNEL_IP |
3290 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3291 RTE_PTYPE_INNER_L4_UDP,
3293 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3294 RTE_PTYPE_TUNNEL_IP |
3295 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3296 RTE_PTYPE_INNER_L4_TCP,
3297 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3298 RTE_PTYPE_TUNNEL_IP |
3299 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3300 RTE_PTYPE_INNER_L4_SCTP,
3301 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3302 RTE_PTYPE_TUNNEL_IP |
3303 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3304 RTE_PTYPE_INNER_L4_ICMP,
3307 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3308 RTE_PTYPE_TUNNEL_IP |
3309 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3310 RTE_PTYPE_INNER_L4_FRAG,
3311 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3312 RTE_PTYPE_TUNNEL_IP |
3313 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3314 RTE_PTYPE_INNER_L4_NONFRAG,
3315 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3316 RTE_PTYPE_TUNNEL_IP |
3317 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3318 RTE_PTYPE_INNER_L4_UDP,
3320 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3321 RTE_PTYPE_TUNNEL_IP |
3322 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3323 RTE_PTYPE_INNER_L4_TCP,
3324 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3325 RTE_PTYPE_TUNNEL_IP |
3326 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3327 RTE_PTYPE_INNER_L4_SCTP,
3328 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3329 RTE_PTYPE_TUNNEL_IP |
3330 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3331 RTE_PTYPE_INNER_L4_ICMP,
3333 /* IPv4 --> GRE/Teredo/VXLAN */
3334 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3335 RTE_PTYPE_TUNNEL_GRENAT,
3337 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3338 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3339 RTE_PTYPE_TUNNEL_GRENAT |
3340 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3341 RTE_PTYPE_INNER_L4_FRAG,
3342 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3343 RTE_PTYPE_TUNNEL_GRENAT |
3344 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3345 RTE_PTYPE_INNER_L4_NONFRAG,
3346 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3347 RTE_PTYPE_TUNNEL_GRENAT |
3348 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3349 RTE_PTYPE_INNER_L4_UDP,
3351 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352 RTE_PTYPE_TUNNEL_GRENAT |
3353 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354 RTE_PTYPE_INNER_L4_TCP,
3355 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3356 RTE_PTYPE_TUNNEL_GRENAT |
3357 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3358 RTE_PTYPE_INNER_L4_SCTP,
3359 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3360 RTE_PTYPE_TUNNEL_GRENAT |
3361 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3362 RTE_PTYPE_INNER_L4_ICMP,
3364 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3365 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3366 RTE_PTYPE_TUNNEL_GRENAT |
3367 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3368 RTE_PTYPE_INNER_L4_FRAG,
3369 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3370 RTE_PTYPE_TUNNEL_GRENAT |
3371 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3372 RTE_PTYPE_INNER_L4_NONFRAG,
3373 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3374 RTE_PTYPE_TUNNEL_GRENAT |
3375 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3376 RTE_PTYPE_INNER_L4_UDP,
3378 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3379 RTE_PTYPE_TUNNEL_GRENAT |
3380 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3381 RTE_PTYPE_INNER_L4_TCP,
3382 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3383 RTE_PTYPE_TUNNEL_GRENAT |
3384 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3385 RTE_PTYPE_INNER_L4_SCTP,
3386 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3387 RTE_PTYPE_TUNNEL_GRENAT |
3388 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3389 RTE_PTYPE_INNER_L4_ICMP,
3391 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3392 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3393 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3395 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3396 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3397 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3398 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3399 RTE_PTYPE_INNER_L4_FRAG,
3400 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3401 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3402 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3403 RTE_PTYPE_INNER_L4_NONFRAG,
3404 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3405 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3406 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3407 RTE_PTYPE_INNER_L4_UDP,
3409 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3410 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3411 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3412 RTE_PTYPE_INNER_L4_TCP,
3413 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3414 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3415 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3416 RTE_PTYPE_INNER_L4_SCTP,
3417 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3418 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3419 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3420 RTE_PTYPE_INNER_L4_ICMP,
3422 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3423 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3424 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3425 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3426 RTE_PTYPE_INNER_L4_FRAG,
3427 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3428 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3429 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3430 RTE_PTYPE_INNER_L4_NONFRAG,
3431 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3432 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3433 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3434 RTE_PTYPE_INNER_L4_UDP,
3436 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3437 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3438 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3439 RTE_PTYPE_INNER_L4_TCP,
3440 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3441 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3442 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3443 RTE_PTYPE_INNER_L4_SCTP,
3444 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3445 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3446 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3447 RTE_PTYPE_INNER_L4_ICMP,
3448 /* [73] - [87] reserved */
3450 /* Non tunneled IPv6 */
3451 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3454 RTE_PTYPE_L4_NONFRAG,
3455 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3458 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3460 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3462 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3466 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3467 RTE_PTYPE_TUNNEL_IP |
3468 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3469 RTE_PTYPE_INNER_L4_FRAG,
3470 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3471 RTE_PTYPE_TUNNEL_IP |
3472 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3473 RTE_PTYPE_INNER_L4_NONFRAG,
3474 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3475 RTE_PTYPE_TUNNEL_IP |
3476 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3477 RTE_PTYPE_INNER_L4_UDP,
3479 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3480 RTE_PTYPE_TUNNEL_IP |
3481 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3482 RTE_PTYPE_INNER_L4_TCP,
3483 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3484 RTE_PTYPE_TUNNEL_IP |
3485 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3486 RTE_PTYPE_INNER_L4_SCTP,
3487 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3488 RTE_PTYPE_TUNNEL_IP |
3489 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3490 RTE_PTYPE_INNER_L4_ICMP,
3493 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3494 RTE_PTYPE_TUNNEL_IP |
3495 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3496 RTE_PTYPE_INNER_L4_FRAG,
3497 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3498 RTE_PTYPE_TUNNEL_IP |
3499 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3500 RTE_PTYPE_INNER_L4_NONFRAG,
3501 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3502 RTE_PTYPE_TUNNEL_IP |
3503 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3504 RTE_PTYPE_INNER_L4_UDP,
3505 /* [105] reserved */
3506 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3507 RTE_PTYPE_TUNNEL_IP |
3508 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3509 RTE_PTYPE_INNER_L4_TCP,
3510 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3511 RTE_PTYPE_TUNNEL_IP |
3512 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3513 RTE_PTYPE_INNER_L4_SCTP,
3514 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3515 RTE_PTYPE_TUNNEL_IP |
3516 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3517 RTE_PTYPE_INNER_L4_ICMP,
3519 /* IPv6 --> GRE/Teredo/VXLAN */
3520 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3521 RTE_PTYPE_TUNNEL_GRENAT,
3523 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3524 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3525 RTE_PTYPE_TUNNEL_GRENAT |
3526 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3527 RTE_PTYPE_INNER_L4_FRAG,
3528 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3529 RTE_PTYPE_TUNNEL_GRENAT |
3530 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3531 RTE_PTYPE_INNER_L4_NONFRAG,
3532 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3533 RTE_PTYPE_TUNNEL_GRENAT |
3534 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3535 RTE_PTYPE_INNER_L4_UDP,
3536 /* [113] reserved */
3537 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538 RTE_PTYPE_TUNNEL_GRENAT |
3539 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540 RTE_PTYPE_INNER_L4_TCP,
3541 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3542 RTE_PTYPE_TUNNEL_GRENAT |
3543 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3544 RTE_PTYPE_INNER_L4_SCTP,
3545 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3546 RTE_PTYPE_TUNNEL_GRENAT |
3547 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3548 RTE_PTYPE_INNER_L4_ICMP,
3550 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3551 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3552 RTE_PTYPE_TUNNEL_GRENAT |
3553 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3554 RTE_PTYPE_INNER_L4_FRAG,
3555 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3556 RTE_PTYPE_TUNNEL_GRENAT |
3557 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3558 RTE_PTYPE_INNER_L4_NONFRAG,
3559 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3560 RTE_PTYPE_TUNNEL_GRENAT |
3561 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3562 RTE_PTYPE_INNER_L4_UDP,
3563 /* [120] reserved */
3564 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3565 RTE_PTYPE_TUNNEL_GRENAT |
3566 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3567 RTE_PTYPE_INNER_L4_TCP,
3568 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3569 RTE_PTYPE_TUNNEL_GRENAT |
3570 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3571 RTE_PTYPE_INNER_L4_SCTP,
3572 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3573 RTE_PTYPE_TUNNEL_GRENAT |
3574 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3575 RTE_PTYPE_INNER_L4_ICMP,
3577 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3578 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3579 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3581 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3582 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3583 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3584 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3585 RTE_PTYPE_INNER_L4_FRAG,
3586 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3587 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3588 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3589 RTE_PTYPE_INNER_L4_NONFRAG,
3590 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3591 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3592 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3593 RTE_PTYPE_INNER_L4_UDP,
3594 /* [128] reserved */
3595 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3596 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3597 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3598 RTE_PTYPE_INNER_L4_TCP,
3599 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3600 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3601 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3602 RTE_PTYPE_INNER_L4_SCTP,
3603 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3604 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3605 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3606 RTE_PTYPE_INNER_L4_ICMP,
3608 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3609 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3610 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3611 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3612 RTE_PTYPE_INNER_L4_FRAG,
3613 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3614 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3615 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3616 RTE_PTYPE_INNER_L4_NONFRAG,
3617 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3618 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3619 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3620 RTE_PTYPE_INNER_L4_UDP,
3621 /* [135] reserved */
3622 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3624 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3625 RTE_PTYPE_INNER_L4_TCP,
3626 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3627 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3628 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3629 RTE_PTYPE_INNER_L4_SCTP,
3630 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3631 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3632 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3633 RTE_PTYPE_INNER_L4_ICMP,
3634 /* [139] - [299] reserved */
3637 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3638 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3640 /* PPPoE --> IPv4 */
3641 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3642 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3644 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3645 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3646 RTE_PTYPE_L4_NONFRAG,
3647 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3648 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3651 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3653 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3654 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3657 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660 /* PPPoE --> IPv6 */
3661 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3662 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3664 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3665 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3666 RTE_PTYPE_L4_NONFRAG,
3667 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3668 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3670 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3671 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3674 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3676 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3677 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3679 /* [314] - [324] reserved */
3681 /* IPv4/IPv6 --> GTPC/GTPU */
3682 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683 RTE_PTYPE_TUNNEL_GTPC,
3684 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685 RTE_PTYPE_TUNNEL_GTPC,
3686 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687 RTE_PTYPE_TUNNEL_GTPC,
3688 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3689 RTE_PTYPE_TUNNEL_GTPC,
3690 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691 RTE_PTYPE_TUNNEL_GTPU,
3692 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3693 RTE_PTYPE_TUNNEL_GTPU,
3695 /* IPv4 --> GTPU --> IPv4 */
3696 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3697 RTE_PTYPE_TUNNEL_GTPU |
3698 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3699 RTE_PTYPE_INNER_L4_FRAG,
3700 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701 RTE_PTYPE_TUNNEL_GTPU |
3702 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3703 RTE_PTYPE_INNER_L4_NONFRAG,
3704 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3705 RTE_PTYPE_TUNNEL_GTPU |
3706 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3707 RTE_PTYPE_INNER_L4_UDP,
3708 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3709 RTE_PTYPE_TUNNEL_GTPU |
3710 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3711 RTE_PTYPE_INNER_L4_TCP,
3712 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3713 RTE_PTYPE_TUNNEL_GTPU |
3714 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3715 RTE_PTYPE_INNER_L4_ICMP,
3717 /* IPv6 --> GTPU --> IPv4 */
3718 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3719 RTE_PTYPE_TUNNEL_GTPU |
3720 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3721 RTE_PTYPE_INNER_L4_FRAG,
3722 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3723 RTE_PTYPE_TUNNEL_GTPU |
3724 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3725 RTE_PTYPE_INNER_L4_NONFRAG,
3726 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3727 RTE_PTYPE_TUNNEL_GTPU |
3728 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3729 RTE_PTYPE_INNER_L4_UDP,
3730 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3731 RTE_PTYPE_TUNNEL_GTPU |
3732 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3733 RTE_PTYPE_INNER_L4_TCP,
3734 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3735 RTE_PTYPE_TUNNEL_GTPU |
3736 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3737 RTE_PTYPE_INNER_L4_ICMP,
3739 /* IPv4 --> GTPU --> IPv6 */
3740 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741 RTE_PTYPE_TUNNEL_GTPU |
3742 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3743 RTE_PTYPE_INNER_L4_FRAG,
3744 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745 RTE_PTYPE_TUNNEL_GTPU |
3746 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3747 RTE_PTYPE_INNER_L4_NONFRAG,
3748 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749 RTE_PTYPE_TUNNEL_GTPU |
3750 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3751 RTE_PTYPE_INNER_L4_UDP,
3752 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3753 RTE_PTYPE_TUNNEL_GTPU |
3754 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3755 RTE_PTYPE_INNER_L4_TCP,
3756 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3757 RTE_PTYPE_TUNNEL_GTPU |
3758 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3759 RTE_PTYPE_INNER_L4_ICMP,
3761 /* IPv6 --> GTPU --> IPv6 */
3762 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3763 RTE_PTYPE_TUNNEL_GTPU |
3764 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3765 RTE_PTYPE_INNER_L4_FRAG,
3766 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3767 RTE_PTYPE_TUNNEL_GTPU |
3768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3769 RTE_PTYPE_INNER_L4_NONFRAG,
3770 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3771 RTE_PTYPE_TUNNEL_GTPU |
3772 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3773 RTE_PTYPE_INNER_L4_UDP,
3774 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3775 RTE_PTYPE_TUNNEL_GTPU |
3776 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3777 RTE_PTYPE_INNER_L4_TCP,
3778 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3779 RTE_PTYPE_TUNNEL_GTPU |
3780 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3781 RTE_PTYPE_INNER_L4_ICMP,
3782 /* All others reserved */
3785 return type_table[ptype];
3789 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3791 struct ice_adapter *ad =
3792 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3795 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3796 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3799 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3800 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3801 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3802 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3803 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3805 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
3806 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
3807 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3808 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
3809 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
3810 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3813 * check the programming status descriptor in rx queue.
3814 * done after Programming Flow Director is programmed on
3818 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3820 volatile union ice_32byte_rx_desc *rxdp;
3827 rxdp = (volatile union ice_32byte_rx_desc *)
3828 (&rxq->rx_ring[rxq->rx_tail]);
3829 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3830 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3831 >> ICE_RXD_QW1_STATUS_S;
3833 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3835 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3836 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3837 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3838 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3840 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3841 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3842 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3843 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3847 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3848 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3850 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3854 rxdp->wb.qword1.status_error_len = 0;
3856 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3858 if (rxq->rx_tail == 0)
3859 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3861 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3867 #define ICE_FDIR_MAX_WAIT_US 10000
3870 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3872 struct ice_tx_queue *txq = pf->fdir.txq;
3873 struct ice_rx_queue *rxq = pf->fdir.rxq;
3874 volatile struct ice_fltr_desc *fdirdp;
3875 volatile struct ice_tx_desc *txdp;
3879 fdirdp = (volatile struct ice_fltr_desc *)
3880 (&txq->tx_ring[txq->tx_tail]);
3881 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3882 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3884 txdp = &txq->tx_ring[txq->tx_tail + 1];
3885 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3886 td_cmd = ICE_TX_DESC_CMD_EOP |
3887 ICE_TX_DESC_CMD_RS |
3888 ICE_TX_DESC_CMD_DUMMY;
3890 txdp->cmd_type_offset_bsz =
3891 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3894 if (txq->tx_tail >= txq->nb_tx_desc)
3896 /* Update the tx tail register */
3897 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3898 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3899 if ((txdp->cmd_type_offset_bsz &
3900 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3901 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3905 if (i >= ICE_FDIR_MAX_WAIT_US) {
3907 "Failed to program FDIR filter: time out to get DD on tx queue.");
3911 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3914 ret = ice_check_fdir_programming_status(rxq);
3922 "Failed to program FDIR filter: programming status reported.");