1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2022 Intel Corporation
13 #include <sys/eventfd.h>
14 #include <sys/ioctl.h>
17 #include <rte_malloc.h>
18 #include <rte_memcpy.h>
21 #include <rte_bus_pci.h>
22 #include <rte_bus_ifpga.h>
23 #include <rte_rawdev.h>
25 #include "afu_pmd_core.h"
26 #include "afu_pmd_he_lpbk.h"
28 static int he_lpbk_afu_config(struct afu_rawdev *dev)
30 struct he_lpbk_priv *priv = NULL;
31 struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
32 struct he_lpbk_csr_cfg v;
37 priv = (struct he_lpbk_priv *)dev->priv;
41 cfg = &priv->he_lpbk_cfg;
49 v.trput_interleave = cfg->trput_interleave;
50 if (cfg->multi_cl == 4)
53 v.multicl_len = cfg->multi_cl - 1;
55 IFPGA_RAWDEV_PMD_DEBUG("cfg: 0x%08x", v.csr);
56 rte_write32(v.csr, priv->he_lpbk_ctx.addr + CSR_CFG);
61 static void he_lpbk_report(struct afu_rawdev *dev, uint32_t cl)
63 struct he_lpbk_priv *priv = NULL;
64 struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
65 struct he_lpbk_ctx *ctx = NULL;
66 struct he_lpbk_dsm_status *stat = NULL;
67 struct he_lpbk_status0 stat0;
68 struct he_lpbk_status1 stat1;
69 uint64_t swtest_msg = 0;
72 double num, rd_bw, wr_bw;
74 if (!dev || !dev->priv)
77 priv = (struct he_lpbk_priv *)dev->priv;
78 cfg = &priv->he_lpbk_cfg;
79 ctx = &priv->he_lpbk_ctx;
81 stat = ctx->status_ptr;
83 swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
84 stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
85 stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
88 ticks = stat->num_clocks - stat->start_overhead;
90 ticks = stat->num_clocks -
91 (stat->start_overhead + stat->end_overhead);
93 if (cfg->freq_mhz == 0) {
94 info = rte_read64(ctx->addr + CSR_HE_INFO0);
95 IFPGA_RAWDEV_PMD_INFO("API version: %"PRIx64, info >> 16);
96 cfg->freq_mhz = info & 0xffff;
97 if (cfg->freq_mhz == 0) {
98 IFPGA_RAWDEV_PMD_INFO("Frequency of AFU clock is unknown."
99 " Assuming 350 MHz.");
104 num = (double)stat0.num_reads;
105 rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
106 num = (double)stat0.num_writes;
107 wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
109 printf("Cachelines Read_Count Write_Count Pend_Read Pend_Write "
110 "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n",
112 printf("%10u %10u %10u %10u %10u %12"PRIu64
113 " %7.3f GB/s %7.3f GB/s\n",
114 cl, stat0.num_reads, stat0.num_writes,
115 stat1.num_pend_reads, stat1.num_pend_writes,
116 ticks, rd_bw / 1e9, wr_bw / 1e9);
117 printf("Test Message: 0x%"PRIx64"\n", swtest_msg);
120 static int he_lpbk_test(struct afu_rawdev *dev)
122 struct he_lpbk_priv *priv = NULL;
123 struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
124 struct he_lpbk_ctx *ctx = NULL;
125 struct he_lpbk_csr_ctl ctl;
126 uint32_t *ptr = NULL;
127 uint32_t i, j, cl, val = 0;
134 priv = (struct he_lpbk_priv *)dev->priv;
138 cfg = &priv->he_lpbk_cfg;
139 ctx = &priv->he_lpbk_ctx;
142 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
145 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
147 /* initialize DMA addresses */
148 IFPGA_RAWDEV_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova);
149 rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + CSR_SRC_ADDR);
151 IFPGA_RAWDEV_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova);
152 rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + CSR_DST_ADDR);
154 IFPGA_RAWDEV_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova);
155 rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr + CSR_AFU_DSM_BASEL);
156 rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32,
157 ctx->addr + CSR_AFU_DSM_BASEH);
159 ret = he_lpbk_afu_config(dev);
163 /* initialize src data */
164 ptr = (uint32_t *)ctx->src_ptr;
165 j = CLS_TO_SIZE(cfg->end) >> 2;
166 for (i = 0; i < j; i++)
170 for (cl = cfg->begin; cl <= cfg->end; cl += cfg->multi_cl) {
171 memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl));
172 memset(ctx->dsm_ptr, 0, DSM_SIZE);
175 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
178 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
180 rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES);
183 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
186 rte_delay_ms(cfg->timeout * 1000);
187 ctl.force_completion = 1;
188 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
189 ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
190 val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
193 printf("DSM poll timeout\n");
197 ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
198 val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
201 printf("DSM poll timeout\n");
204 ctl.force_completion = 1;
205 rte_write32(ctl.csr, ctx->addr + CSR_CTL);
208 he_lpbk_report(dev, cl);
212 sval = rte_read64(ctx->addr + CSR_STATUS1);
218 if (cfg->mode == NLB_MODE_LPBK) {
219 ptr = (uint32_t *)ctx->dest_ptr;
220 j = CLS_TO_SIZE(cl) >> 2;
221 for (i = 0; i < j; i++) {
223 IFPGA_RAWDEV_PMD_ERR("Data mismatch @ %u", i);
234 static int he_lpbk_ctx_release(struct afu_rawdev *dev)
236 struct he_lpbk_priv *priv = NULL;
237 struct he_lpbk_ctx *ctx = NULL;
242 priv = (struct he_lpbk_priv *)dev->priv;
246 ctx = &priv->he_lpbk_ctx;
248 rte_free(ctx->dsm_ptr);
250 ctx->status_ptr = NULL;
252 rte_free(ctx->src_ptr);
255 rte_free(ctx->dest_ptr);
256 ctx->dest_ptr = NULL;
261 static int he_lpbk_ctx_init(struct afu_rawdev *dev)
263 struct he_lpbk_priv *priv = NULL;
264 struct he_lpbk_ctx *ctx = NULL;
270 priv = (struct he_lpbk_priv *)dev->priv;
274 ctx = &priv->he_lpbk_ctx;
275 ctx->addr = (uint8_t *)dev->addr;
277 ctx->dsm_ptr = (uint8_t *)rte_zmalloc(NULL, DSM_SIZE, TEST_MEM_ALIGN);
280 ctx->dsm_iova = rte_malloc_virt2iova(ctx->dsm_ptr);
281 if (ctx->dsm_iova == RTE_BAD_IOVA) {
286 ctx->src_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
292 ctx->src_iova = rte_malloc_virt2iova(ctx->src_ptr);
293 if (ctx->src_iova == RTE_BAD_IOVA) {
298 ctx->dest_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
300 if (!ctx->dest_ptr) {
304 ctx->dest_iova = rte_malloc_virt2iova(ctx->dest_ptr);
305 if (ctx->dest_iova == RTE_BAD_IOVA) {
310 ctx->status_ptr = (struct he_lpbk_dsm_status *)ctx->dsm_ptr;
314 rte_free(ctx->dest_ptr);
315 ctx->dest_ptr = NULL;
317 rte_free(ctx->src_ptr);
320 rte_free(ctx->dsm_ptr);
325 static int he_lpbk_init(struct afu_rawdev *dev)
331 dev->priv = rte_zmalloc(NULL, sizeof(struct he_lpbk_priv), 0);
336 return he_lpbk_ctx_init(dev);
339 static int he_lpbk_config(struct afu_rawdev *dev, void *config,
342 struct he_lpbk_priv *priv = NULL;
343 struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
345 if (!dev || !config || !config_size)
348 priv = (struct he_lpbk_priv *)dev->priv;
352 if (config_size != sizeof(struct rte_pmd_afu_he_lpbk_cfg))
355 cfg = (struct rte_pmd_afu_he_lpbk_cfg *)config;
356 if (cfg->mode > NLB_MODE_TRPUT)
358 if ((cfg->multi_cl != 1) && (cfg->multi_cl != 2) &&
359 (cfg->multi_cl != 4))
361 if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin > MAX_CACHE_LINES))
363 if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES))
366 rte_memcpy(&priv->he_lpbk_cfg, cfg, sizeof(priv->he_lpbk_cfg));
371 static int he_lpbk_close(struct afu_rawdev *dev)
376 he_lpbk_ctx_release(dev);
384 static int he_lpbk_dump(struct afu_rawdev *dev, FILE *f)
386 struct he_lpbk_priv *priv = NULL;
387 struct he_lpbk_ctx *ctx = NULL;
392 priv = (struct he_lpbk_priv *)dev->priv;
399 ctx = &priv->he_lpbk_ctx;
401 fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
402 fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr);
403 fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova);
404 fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr);
405 fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova);
406 fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr);
407 fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova);
408 fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr);
413 static struct afu_ops he_lpbk_ops = {
414 .init = he_lpbk_init,
415 .config = he_lpbk_config,
418 .test = he_lpbk_test,
419 .close = he_lpbk_close,
420 .dump = he_lpbk_dump,
424 struct afu_rawdev_drv he_lpbk_drv = {
425 .uuid = { HE_LPBK_UUID_L, HE_LPBK_UUID_H },
429 AFU_PMD_REGISTER(he_lpbk_drv);
431 struct afu_rawdev_drv he_mem_lpbk_drv = {
432 .uuid = { HE_MEM_LPBK_UUID_L, HE_MEM_LPBK_UUID_H },
436 AFU_PMD_REGISTER(he_mem_lpbk_drv);