1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2022 Intel Corporation
5 #ifndef AFU_PMD_HE_LPBK_H
6 #define AFU_PMD_HE_LPBK_H
12 #include "afu_pmd_core.h"
13 #include "rte_pmd_afu.h"
15 #define HE_LPBK_UUID_L 0xb94b12284c31e02b
16 #define HE_LPBK_UUID_H 0x56e203e9864f49a7
17 #define HE_MEM_LPBK_UUID_L 0xbb652a578330a8eb
18 #define HE_MEM_LPBK_UUID_H 0x8568ab4e6ba54616
20 /* HE-LBK & HE-MEM-LBK registers definition */
21 #define CSR_SCRATCHPAD0 0x100
22 #define CSR_SCRATCHPAD1 0x108
23 #define CSR_AFU_DSM_BASEL 0x110
24 #define CSR_AFU_DSM_BASEH 0x114
25 #define CSR_SRC_ADDR 0x120
26 #define CSR_DST_ADDR 0x128
27 #define CSR_NUM_LINES 0x130
30 #define CSR_INACT_THRESH 0x148
31 #define CSR_INTERRUPT0 0x150
32 #define CSR_SWTEST_MSG 0x158
33 #define CSR_STATUS0 0x160
34 #define CSR_STATUS1 0x168
35 #define CSR_ERROR 0x170
36 #define CSR_STRIDE 0x178
37 #define CSR_HE_INFO0 0x180
39 #define DSM_SIZE 0x200000
40 #define DSM_POLL_INTERVAL 5 /* ms */
41 #define DSM_TIMEOUT 1000 /* ms */
43 #define NLB_BUF_SIZE 0x400000
44 #define TEST_MEM_ALIGN 1024
46 struct he_lpbk_csr_ctl {
52 uint32_t force_completion:1;
58 struct he_lpbk_csr_cfg {
65 uint32_t multicl_len:2;
67 uint32_t trput_interleave:3;
69 uint32_t interrupt_on_error:1;
70 uint32_t interrupt_testmode:1;
76 struct he_lpbk_status0 {
86 struct he_lpbk_status1 {
90 uint32_t num_pend_writes;
91 uint32_t num_pend_reads;
96 struct he_lpbk_dsm_status {
97 uint32_t test_complete;
102 uint32_t start_overhead;
103 uint32_t end_overhead;
114 struct he_lpbk_dsm_status *status_ptr;
117 struct he_lpbk_priv {
118 struct rte_pmd_afu_he_lpbk_cfg he_lpbk_cfg;
119 struct he_lpbk_ctx he_lpbk_ctx;
126 #endif /* AFU_PMD_HE_LPBK_H */