1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2022 Intel Corporation
5 #ifndef AFU_PMD_N3000_H
6 #define AFU_PMD_N3000_H
12 #include "afu_pmd_core.h"
13 #include "rte_pmd_afu.h"
15 #define N3000_AFU_UUID_L 0xc000c9660d824272
16 #define N3000_AFU_UUID_H 0x9aeffe5f84570612
17 #define N3000_NLB0_UUID_L 0xf89e433683f9040b
18 #define N3000_NLB0_UUID_H 0xd8424dc4a4a3c413
19 #define N3000_DMA_UUID_L 0xa9149a35bace01ea
20 #define N3000_DMA_UUID_H 0xef82def7f6ec40fc
22 #define NUM_N3000_DMA 4
23 #define MAX_MSIX_VEC 7
25 /* N3000 DFL definition */
26 #define DFH_UUID_L_OFFSET 8
27 #define DFH_UUID_H_OFFSET 16
28 #define DFH_TYPE(hdr) (((hdr) >> 60) & 0xf)
29 #define DFH_TYPE_AFU 1
30 #define DFH_TYPE_BBB 2
31 #define DFH_TYPE_PRIVATE 3
32 #define DFH_EOL(hdr) (((hdr) >> 40) & 0x1)
33 #define DFH_NEXT_OFFSET(hdr) (((hdr) >> 16) & 0xffffff)
34 #define DFH_FEATURE_ID(hdr) ((hdr) & 0xfff)
35 #define PORT_ATTR_REG(n) (((n) << 3) + 0x38)
36 #define PORT_IMPLEMENTED(attr) (((attr) >> 60) & 0x1)
37 #define PORT_BAR(attr) (((attr) >> 32) & 0x7)
38 #define PORT_OFFSET(attr) ((attr) & 0xffffff)
39 #define PORT_FEATURE_UINT_ID 0x12
40 #define PORT_UINT_CAP_REG 0x8
41 #define PORT_VEC_START(cap) (((cap) >> 12) & 0xfff)
42 #define PORT_VEC_COUNT(cap) ((cap) >> 12 & 0xfff)
43 #define PORT_CTRL_REG 0x38
44 #define PORT_SOFT_RESET (0x1 << 0)
46 /* NLB registers definition */
47 #define CSR_SCRATCHPAD0 0x100
48 #define CSR_SCRATCHPAD1 0x108
49 #define CSR_AFU_DSM_BASEL 0x110
50 #define CSR_AFU_DSM_BASEH 0x114
51 #define CSR_SRC_ADDR 0x120
52 #define CSR_DST_ADDR 0x128
53 #define CSR_NUM_LINES 0x130
56 #define CSR_INACT_THRESH 0x148
57 #define CSR_INTERRUPT0 0x150
58 #define CSR_SWTEST_MSG 0x158
59 #define CSR_STATUS0 0x160
60 #define CSR_STATUS1 0x168
61 #define CSR_ERROR 0x170
62 #define CSR_STRIDE 0x178
63 #define CSR_HE_INFO0 0x180
65 #define DSM_SIZE 0x200000
66 #define DSM_STATUS 0x40
67 #define DSM_POLL_INTERVAL 5 /* ms */
68 #define DSM_TIMEOUT 1000 /* ms */
70 #define NLB_BUF_SIZE 0x400000
71 #define TEST_MEM_ALIGN 1024
79 uint32_t force_completion:1;
92 uint32_t multicl_len:2;
103 uint32_t interrupt_on_error:1;
104 uint32_t interrupt_testmode:1;
105 uint32_t wrfence_chsel:2;
124 uint32_t num_pend_writes;
125 uint32_t num_pend_reads;
130 struct nlb_dsm_status {
131 uint32_t test_complete;
136 uint32_t start_overhead;
137 uint32_t end_overhead;
140 /* DMA registers definition */
142 #define DMA_DESC 0x60
143 #define DMA_ASE_CTRL 0x200
144 #define DMA_ASE_DATA 0x1000
146 #define DMA_ASE_WINDOW 4096
147 #define DMA_ASE_WINDOW_MASK ((uint64_t)(DMA_ASE_WINDOW - 1))
148 #define INVALID_ASE_PAGE 0xffffffffffffffffULL
150 #define DMA_WF_MAGIC 0x5772745F53796E63ULL
151 #define DMA_WF_MAGIC_ROM 0x1000000000000
152 #define DMA_HOST_ADDR(addr) ((addr) | 0x2000000000000)
153 #define DMA_WF_HOST_ADDR(addr) ((addr) | 0x3000000000000)
155 #define NUM_DMA_BUF 8
156 #define HALF_DMA_BUF (NUM_DMA_BUF / 2)
158 #define DMA_MASK_32_BIT 0xFFFFFFFF
160 #define DMA_CSR_BUSY 0x1
161 #define DMA_DESC_BUFFER_EMPTY 0x2
162 #define DMA_DESC_BUFFER_FULL 0x4
164 #define DWORD_BYTES 4
165 #define IS_ALIGNED_DWORD(addr) (((addr) % DWORD_BYTES) == 0)
167 #define QWORD_BYTES 8
168 #define IS_ALIGNED_QWORD(addr) (((addr) % QWORD_BYTES) == 0)
170 #define DMA_ALIGN_BYTES 64
171 #define IS_DMA_ALIGNED(addr) (((addr) % DMA_ALIGN_BYTES) == 0)
173 #define CCIP_ALIGN_BYTES (DMA_ALIGN_BYTES << 2)
175 #define DMA_TIMEOUT_MSEC 5000
177 #define MAGIC_BUF_SIZE 64
178 #define ERR_CHECK_LIMIT 64
181 #define MIN(a, b) ((a) < (b) ? (a) : (b))
185 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
192 FPGA_MAX_TRANSFER_TYPE,
198 uint32_t tx_channel:8;
199 uint32_t generate_sop:1;
200 uint32_t generate_eop:1;
201 uint32_t park_reads:1;
202 uint32_t park_writes:1;
203 uint32_t end_on_eop:1;
204 uint32_t reserved_1:1;
205 uint32_t transfer_irq_en:1;
206 uint32_t early_term_irq_en:1;
207 uint32_t trans_error_irq_en:8;
208 uint32_t early_done_en:1;
209 uint32_t reserved_2:6;
214 typedef struct __rte_packed {
219 uint8_t rd_burst_count;
220 uint8_t wr_burst_count;
223 uint32_t rd_address_ext;
224 uint32_t wr_address_ext;
225 msgdma_desc_ctrl control;
232 uint32_t desc_buf_empty:1;
233 uint32_t desc_buf_full:1;
234 uint32_t rsp_buf_empty:1;
235 uint32_t rsp_buf_full:1;
237 uint32_t resetting:1;
238 uint32_t stopped_on_error:1;
239 uint32_t stopped_on_early_term:1;
241 uint32_t reserved:22;
248 uint32_t stop_dispatcher:1;
249 uint32_t reset_dispatcher:1;
250 uint32_t stop_on_error:1;
251 uint32_t stopped_on_early_term:1;
252 uint32_t global_intr_en_mask:1;
253 uint32_t stop_descriptors:1;
254 uint32_t reserved:22;
261 uint32_t rd_fill_level:16;
262 uint32_t wr_fill_level:16;
269 uint32_t rsp_fill_level:16;
270 uint32_t reserved:16;
277 uint32_t rd_seq_num:16;
278 uint32_t wr_seq_num:16;
282 typedef struct __rte_packed {
283 msgdma_status status;
285 msgdma_fill_level fill_level;
286 msgdma_rsp_level rsp;
287 msgdma_seq_num seq_num;
290 #define CSR_STATUS(csr) (&(((msgdma_csr *)(csr))->status))
291 #define CSR_CONTROL(csr) (&(((msgdma_csr *)(csr))->ctrl))
301 struct nlb_dsm_status *status_ptr;
309 uint8_t *ase_ctrl_addr;
310 uint8_t *ase_data_addr;
312 uint64_t cur_ase_page;
318 msgdma_ext_desc *desc_buf;
321 uint32_t dma_buf_size;
322 uint64_t *dma_buf[NUM_DMA_BUF];
323 uint64_t dma_iova[NUM_DMA_BUF];
326 struct n3000_afu_priv {
327 struct rte_pmd_afu_nlb_cfg nlb_cfg;
328 struct rte_pmd_afu_dma_cfg dma_cfg;
329 struct nlb_afu_ctx nlb_ctx;
330 struct dma_afu_ctx dma_ctx[NUM_N3000_DMA];
339 #endif /* AFU_PMD_N3000_H */