1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
8 #include "ifpga_defines.h"
9 #include "opae_ifpga_hw_api.h"
10 #include "opae_eth_group.h"
12 /** List of private feateues */
13 TAILQ_HEAD(ifpga_feature_list, ifpga_feature);
15 enum ifpga_feature_state {
16 IFPGA_FEATURE_UNUSED = 0,
17 IFPGA_FEATURE_ATTACHED,
25 struct feature_irq_ctx {
30 struct ifpga_feature {
31 TAILQ_ENTRY(ifpga_feature)next;
32 enum ifpga_feature_state state;
33 enum feature_type type;
42 struct feature_irq_ctx *ctx;
45 void *parent; /* to parent hw data structure */
47 struct ifpga_feature_ops *ops;/* callback to this private feature */
48 unsigned int vec_start;
52 struct ifpga_feature_ops {
53 int (*init)(struct ifpga_feature *feature);
54 void (*uinit)(struct ifpga_feature *feature);
55 int (*get_prop)(struct ifpga_feature *feature,
56 struct feature_prop *prop);
57 int (*set_prop)(struct ifpga_feature *feature,
58 struct feature_prop *prop);
59 int (*set_irq)(struct ifpga_feature *feature, void *irq_set);
62 enum ifpga_fme_state {
64 IFPGA_FME_IMPLEMENTED,
68 enum ifpga_fme_state state;
70 struct ifpga_feature_list feature_list;
71 spinlock_t lock; /* protect hardware access */
73 void *parent; /* pointer to ifpga_hw */
75 /* provied by HEADER feature */
77 struct uuid bitstream_id;
81 u32 fabric_version_id;
86 void *max10_dev; /* MAX10 device */
87 void *i2c_master; /* I2C Master device */
88 void *eth_dev[MAX_ETH_GROUP_DEVICES];
89 struct opae_reg_region
90 eth_group_region[MAX_ETH_GROUP_DEVICES];
91 struct opae_board_info board_info;
93 unsigned int nums_acc_region;
97 enum ifpga_port_state {
98 IFPGA_PORT_UNUSED = 0,
103 struct ifpga_port_hw {
104 enum ifpga_port_state state;
106 struct ifpga_feature_list feature_list;
107 spinlock_t lock; /* protect access to hw */
109 void *parent; /* pointer to ifpga_hw */
111 int port_id; /* provied by HEADER feature */
112 struct uuid afu_id; /* provied by User AFU feature */
114 unsigned int disable_count;
117 u32 num_umsgs; /* The number of allocated umsgs */
118 u32 num_uafu_irqs; /* The number of uafu interrupts */
123 #define AFU_MAX_REGION 1
125 struct ifpga_afu_info {
126 struct opae_reg_region region[AFU_MAX_REGION];
127 unsigned int num_regions;
128 unsigned int num_irqs;
132 struct opae_adapter *adapter;
133 struct opae_adapter_data_pci *pci_data;
135 struct ifpga_fme_hw fme;
136 struct ifpga_port_hw port[MAX_FPGA_PORT_NUM];
139 static inline bool is_ifpga_hw_pf(struct ifpga_hw *hw)
141 return hw->fme.state != IFPGA_FME_UNUSED;
144 static inline bool is_valid_port_id(struct ifpga_hw *hw, u32 port_id)
146 if (port_id >= MAX_FPGA_PORT_NUM ||
147 hw->port[port_id].state != IFPGA_PORT_ATTACHED)
152 #endif /* _IFPGA_HW_H_ */