1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define PCI_VENDOR_ID_INTEL 0x8086
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
50 #define PCIE_DEVICE_ID_PAC_N6000 0xBCCE
52 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
53 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
54 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
55 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
56 #define PCIE_DEVICE_ID_VF_PAC_N6000 0xBCCF
57 #define RTE_MAX_RAW_DEVICE 10
59 static const struct rte_pci_id pci_ifpga_map[] = {
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N6000),},
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N6000),},
70 { .vendor_id = 0, /* sentinel */ },
73 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
75 static int ifpga_monitor_refcnt;
76 static pthread_t ifpga_monitor_start_thread;
78 static struct ifpga_rawdev *
79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
80 static int set_surprise_link_check_aer(
81 struct ifpga_rawdev *ifpga_rdev, int force_disable);
82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
83 int start, uint32_t cap);
84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
85 static void fme_interrupt_handler(void *param);
88 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
90 struct ifpga_rawdev *dev;
96 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
97 dev = &ifpga_rawdevices[i];
98 if (dev->rawdev == rawdev)
105 static inline uint8_t
106 ifpga_rawdev_find_free_device_index(void)
110 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
111 if (ifpga_rawdevices[dev_id].rawdev == NULL)
115 return IFPGA_RAWDEV_NUM;
118 static struct ifpga_rawdev *
119 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
121 struct ifpga_rawdev *dev;
125 dev = ifpga_rawdev_get(rawdev);
127 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
131 dev_id = ifpga_rawdev_find_free_device_index();
132 if (dev_id == IFPGA_RAWDEV_NUM) {
133 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
137 dev = &ifpga_rawdevices[dev_id];
138 dev->rawdev = rawdev;
139 dev->dev_id = dev_id;
140 for (i = 0; i < IFPGA_MAX_IRQ; i++)
141 dev->intr_handle[i] = NULL;
142 dev->poll_enabled = 0;
143 for (i = 0; i < IFPGA_MAX_VDEV; i++)
144 dev->vdev_name[i] = NULL;
150 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
154 int pos = RTE_PCI_CFG_SPACE_SIZE;
157 /* minimum 8 bytes per capability */
158 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
162 ret = pread(fd, &header, sizeof(header), pos);
167 * If we have no capabilities, this is indicated by cap ID,
168 * cap version and next pointer all being 0.
174 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
177 pos = RTE_PCI_EXT_CAP_NEXT(header);
178 if (pos < RTE_PCI_CFG_SPACE_SIZE)
180 ret = pread(fd, &header, sizeof(header), pos);
189 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
191 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
194 static int ifpga_get_dev_vendor_id(const char *bdf,
195 uint32_t *dev_id, uint32_t *vendor_id)
202 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
203 strlcat(path, bdf, sizeof(path));
204 strlcat(path, "/config", sizeof(path));
205 fd = open(path, O_RDWR);
208 ret = pread(fd, &header, sizeof(header), 0);
213 (*vendor_id) = header & 0xffff;
214 (*dev_id) = (header >> 16) & 0xffff;
220 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev)
222 struct opae_adapter *adapter = NULL;
223 char path[1024] = "/sys/bus/pci/devices/";
224 char link[1024], link1[1024];
225 char dir[1024] = "/sys/devices/";
228 char sub_brg_bdf[4][16] = {{0}};
231 struct dirent *entry;
234 unsigned int dom, bus, dev;
237 uint32_t vendor_id = 0;
239 adapter = ifpga_dev ? ifpga_rawdev_get_priv(ifpga_dev->rawdev) : NULL;
243 strlcat(path, adapter->name, sizeof(path));
244 memset(link, 0, sizeof(link));
245 memset(link1, 0, sizeof(link1));
246 ret = readlink(path, link, (sizeof(link)-1));
247 if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
249 link[ret] = 0; /* terminate string with null character */
250 strlcpy(link1, link, sizeof(link1));
251 memset(ifpga_dev->parent_bdf, 0, 16);
252 point = strlen(link);
260 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
262 point = strlen(link1);
270 c = strchr(link1, 'p');
273 strlcat(dir, c, sizeof(dir));
280 while ((entry = readdir(dp)) != NULL) {
283 if (entry->d_name[0] == '.')
285 if (strlen(entry->d_name) > 12)
287 if (sscanf(entry->d_name, "%x:%x:%x.%d",
288 &dom, &bus, &dev, &func) < 4)
291 strlcpy(sub_brg_bdf[i],
293 sizeof(sub_brg_bdf[i]));
299 /* get fpga and fvl */
301 for (i = 0; i < 4; i++) {
302 strlcpy(link, dir, sizeof(link));
303 strlcat(link, "/", sizeof(link));
304 strlcat(link, sub_brg_bdf[i], sizeof(link));
308 while ((entry = readdir(dp)) != NULL) {
311 if (entry->d_name[0] == '.')
314 if (strlen(entry->d_name) > 12)
316 if (sscanf(entry->d_name, "%x:%x:%x.%d",
317 &dom, &bus, &dev, &func) < 4)
320 if (ifpga_get_dev_vendor_id(entry->d_name,
321 &dev_id, &vendor_id))
323 if (vendor_id == 0x8086 &&
327 strlcpy(ifpga_dev->fvl_bdf[j],
329 sizeof(ifpga_dev->fvl_bdf[j]));
340 #define HIGH_FATAL(_sens, value)\
341 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
342 (value > (_sens)->high_fatal))
344 #define HIGH_WARN(_sens, value)\
345 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
346 (value > (_sens)->high_warn))
348 #define LOW_FATAL(_sens, value)\
349 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
350 (value > (_sens)->low_fatal))
352 #define LOW_WARN(_sens, value)\
353 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
354 (value > (_sens)->low_warn))
356 #define AUX_VOLTAGE_WARN 11400
359 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
362 struct opae_adapter *adapter;
363 struct opae_manager *mgr;
364 struct opae_sensor_info *sensor;
368 adapter = ifpga_rawdev_get_priv(raw_dev);
372 mgr = opae_adapter_get_mgr(adapter);
373 if (!mgr || !mgr->sensor_list)
376 opae_mgr_for_each_sensor(mgr, sensor) {
377 if (!(sensor->flags & OPAE_SENSOR_VALID))
380 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
384 if (value == 0xdeadbeef) {
385 IFPGA_RAWDEV_PMD_DEBUG("dev_id %d sensor %s value %x\n",
386 raw_dev->dev_id, sensor->name, value);
390 /* monitor temperature sensors */
391 if (!strcmp(sensor->name, "Board Temperature") ||
392 !strcmp(sensor->name, "FPGA Die Temperature")) {
393 IFPGA_RAWDEV_PMD_DEBUG("read sensor %s %d %d %d\n",
394 sensor->name, value, sensor->high_warn,
397 if (HIGH_WARN(sensor, value) ||
398 LOW_WARN(sensor, value)) {
399 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
400 sensor->name, value);
406 /* monitor 12V AUX sensor */
407 if (!strcmp(sensor->name, "12V AUX Voltage")) {
408 if (value < AUX_VOLTAGE_WARN) {
409 IFPGA_RAWDEV_PMD_INFO(
410 "%s reach threshold %d mV\n",
411 sensor->name, value);
423 static int set_surprise_link_check_aer(
424 struct ifpga_rawdev *ifpga_rdev, int force_disable)
426 struct rte_rawdev *rdev;
433 uint32_t aer_new0, aer_new1;
435 if (!ifpga_rdev || !ifpga_rdev->rawdev) {
436 printf("\n device does not exist\n");
440 rdev = ifpga_rdev->rawdev;
441 if (ifpga_rdev->aer_enable)
443 if (ifpga_monitor_sensor(rdev, &enable))
445 if (enable || force_disable) {
446 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
447 ifpga_rdev->aer_enable = 1;
449 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
450 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
451 strlcat(path, "/config", sizeof(path));
452 fd = open(path, O_RDWR);
455 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
458 /* save previous ECAP_AER+0x08 */
459 ret = pread(fd, &data, sizeof(data), pos+0x08);
462 ifpga_rdev->aer_old[0] = data;
463 /* save previous ECAP_AER+0x14 */
464 ret = pread(fd, &data, sizeof(data), pos+0x14);
467 ifpga_rdev->aer_old[1] = data;
469 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
471 ret = pwrite(fd, &data, 4, pos+0x08);
474 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
475 ret = pwrite(fd, &data, 4, pos+0x14);
479 /* read current ECAP_AER+0x08 */
480 ret = pread(fd, &data, sizeof(data), pos+0x08);
484 /* read current ECAP_AER+0x14 */
485 ret = pread(fd, &data, sizeof(data), pos+0x14);
493 printf(">>>>>>Set AER %x,%x %x,%x\n",
494 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
507 ifpga_rawdev_gsd_handle(__rte_unused void *param)
509 struct ifpga_rawdev *ifpga_rdev;
514 while (__atomic_load_n(&ifpga_monitor_refcnt, __ATOMIC_RELAXED)) {
516 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
517 ifpga_rdev = &ifpga_rawdevices[i];
518 if (ifpga_rdev->poll_enabled) {
519 ret = set_surprise_link_check_aer(ifpga_rdev,
521 if (ret == 1 && !gsd_enable) {
529 printf(">>>>>>Pls Shutdown APP\n");
531 rte_delay_us(100 * MS);
538 ifpga_monitor_start_func(struct ifpga_rawdev *dev)
545 ret = ifpga_rawdev_fill_info(dev);
549 dev->poll_enabled = 1;
551 if (!__atomic_fetch_add(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED)) {
552 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
553 "ifpga-monitor", NULL,
554 ifpga_rawdev_gsd_handle, NULL);
556 ifpga_monitor_start_thread = 0;
557 IFPGA_RAWDEV_PMD_ERR(
558 "Fail to create ifpga monitor thread");
567 ifpga_monitor_stop_func(struct ifpga_rawdev *dev)
571 if (!dev || !dev->poll_enabled)
574 dev->poll_enabled = 0;
576 if (!__atomic_sub_fetch(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED) &&
577 ifpga_monitor_start_thread) {
578 ret = pthread_cancel(ifpga_monitor_start_thread);
580 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
582 ret = pthread_join(ifpga_monitor_start_thread, NULL);
584 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
593 ifpga_fill_afu_dev(struct opae_accelerator *acc,
594 struct rte_afu_device *afu_dev)
596 struct rte_mem_resource *res = afu_dev->mem_resource;
597 struct opae_acc_region_info region_info;
598 struct opae_acc_info info;
602 ret = opae_acc_get_info(acc, &info);
606 if (info.num_regions > PCI_MAX_RESOURCE)
609 afu_dev->num_region = info.num_regions;
611 for (i = 0; i < info.num_regions; i++) {
612 region_info.index = i;
613 ret = opae_acc_get_region_info(acc, ®ion_info);
617 if ((region_info.flags & ACC_REGION_MMIO) &&
618 (region_info.flags & ACC_REGION_READ) &&
619 (region_info.flags & ACC_REGION_WRITE)) {
620 res[i].phys_addr = region_info.phys_addr;
621 res[i].len = region_info.len;
622 res[i].addr = region_info.addr;
631 ifpga_rawdev_info_get(struct rte_rawdev *dev,
632 rte_rawdev_obj_t dev_info,
633 size_t dev_info_size)
635 struct opae_adapter *adapter;
636 struct opae_accelerator *acc;
637 struct rte_afu_device *afu_dev;
638 struct opae_manager *mgr = NULL;
639 struct opae_eth_group_region_info opae_lside_eth_info;
640 struct opae_eth_group_region_info opae_nside_eth_info;
641 int lside_bar_idx, nside_bar_idx;
643 IFPGA_RAWDEV_PMD_FUNC_TRACE();
645 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
646 IFPGA_RAWDEV_PMD_ERR("Invalid request");
650 adapter = ifpga_rawdev_get_priv(dev);
655 afu_dev->rawdev = dev;
657 /* find opae_accelerator and fill info into afu_device */
658 opae_adapter_for_each_acc(adapter, acc) {
659 if (acc->index != afu_dev->id.port)
662 if (ifpga_fill_afu_dev(acc, afu_dev)) {
663 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
668 /* get opae_manager to rawdev */
669 mgr = opae_adapter_get_mgr(adapter);
671 /* get LineSide BAR Index */
672 if (opae_manager_get_eth_group_region_info(mgr, 0,
673 &opae_lside_eth_info)) {
676 lside_bar_idx = opae_lside_eth_info.mem_idx;
678 /* get NICSide BAR Index */
679 if (opae_manager_get_eth_group_region_info(mgr, 1,
680 &opae_nside_eth_info)) {
683 nside_bar_idx = opae_nside_eth_info.mem_idx;
685 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
686 nside_bar_idx >= PCI_MAX_RESOURCE ||
687 lside_bar_idx == nside_bar_idx)
690 /* fill LineSide BAR Index */
691 afu_dev->mem_resource[lside_bar_idx].phys_addr =
692 opae_lside_eth_info.phys_addr;
693 afu_dev->mem_resource[lside_bar_idx].len =
694 opae_lside_eth_info.len;
695 afu_dev->mem_resource[lside_bar_idx].addr =
696 opae_lside_eth_info.addr;
698 /* fill NICSide BAR Index */
699 afu_dev->mem_resource[nside_bar_idx].phys_addr =
700 opae_nside_eth_info.phys_addr;
701 afu_dev->mem_resource[nside_bar_idx].len =
702 opae_nside_eth_info.len;
703 afu_dev->mem_resource[nside_bar_idx].addr =
704 opae_nside_eth_info.addr;
710 ifpga_rawdev_configure(const struct rte_rawdev *dev,
711 rte_rawdev_obj_t config,
712 size_t config_size __rte_unused)
714 IFPGA_RAWDEV_PMD_FUNC_TRACE();
716 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
718 return config ? 0 : 1;
722 ifpga_rawdev_start(struct rte_rawdev *dev)
725 struct opae_adapter *adapter;
727 IFPGA_RAWDEV_PMD_FUNC_TRACE();
729 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
731 adapter = ifpga_rawdev_get_priv(dev);
739 ifpga_rawdev_stop(struct rte_rawdev *dev)
745 ifpga_rawdev_close(struct rte_rawdev *dev)
747 struct ifpga_rawdev *ifpga_rdev = NULL;
748 struct opae_adapter *adapter;
749 struct opae_manager *mgr;
750 char *vdev_name = NULL;
754 ifpga_rdev = ifpga_rawdev_get(dev);
756 for (i = 0; i < IFPGA_MAX_VDEV; i++) {
757 vdev_name = ifpga_rdev->vdev_name[i];
759 rte_vdev_uninit(vdev_name);
761 ifpga_monitor_stop_func(ifpga_rdev);
762 ifpga_rdev->rawdev = NULL;
764 adapter = ifpga_rawdev_get_priv(dev);
766 mgr = opae_adapter_get_mgr(adapter);
767 if (ifpga_rdev && mgr) {
768 if (ifpga_unregister_msix_irq(ifpga_rdev,
770 fme_interrupt_handler, mgr) < 0)
773 opae_adapter_destroy(adapter);
774 opae_adapter_data_free(adapter->data);
782 ifpga_rawdev_reset(struct rte_rawdev *dev)
788 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
792 struct opae_adapter *adapter;
793 struct opae_manager *mgr;
794 struct opae_accelerator *acc;
795 struct opae_bridge *br;
798 adapter = ifpga_rawdev_get_priv(raw_dev);
802 mgr = opae_adapter_get_mgr(adapter);
806 acc = opae_adapter_get_acc(adapter, port_id);
810 br = opae_acc_get_br(acc);
814 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
816 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
820 ret = opae_bridge_reset(br);
822 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
823 __func__, port_id, ret);
831 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
832 const char *file_name)
834 struct stat file_stat;
838 void *buffer, *buf_to_free;
844 file_fd = open(file_name, O_RDONLY);
846 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
847 __func__, file_name);
848 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
851 ret = stat(file_name, &file_stat);
853 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
858 buffer_size = file_stat.st_size;
859 if (buffer_size <= 0) {
864 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
865 buffer = rte_malloc(NULL, buffer_size, 0);
870 buf_to_free = buffer;
872 /*read the raw data*/
873 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
879 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
880 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
881 ret ? "failed" : "success");
888 rte_free(buf_to_free);
896 ifpga_rawdev_pr(struct rte_rawdev *dev,
897 rte_rawdev_obj_t pr_conf)
899 struct opae_adapter *adapter;
900 struct opae_manager *mgr;
901 struct opae_board_info *info = NULL;
902 struct rte_afu_pr_conf *afu_pr_conf;
905 struct opae_accelerator *acc;
907 IFPGA_RAWDEV_PMD_FUNC_TRACE();
909 adapter = ifpga_rawdev_get_priv(dev);
916 afu_pr_conf = pr_conf;
918 if (afu_pr_conf->pr_enable) {
919 ret = rte_fpga_do_pr(dev,
920 afu_pr_conf->afu_id.port,
921 afu_pr_conf->bs_path);
923 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
928 mgr = opae_adapter_get_mgr(adapter);
930 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
931 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
936 if (info && info->lightweight) {
937 /* set uuid to all 0, when fpga is lightweight image */
938 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
939 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
941 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
945 ret = opae_acc_get_uuid(acc, &uuid);
949 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
951 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
954 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
956 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
957 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
963 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
964 const char *attr_name, uint64_t *attr_value)
966 struct opae_adapter *adapter;
967 struct opae_manager *mgr;
968 struct opae_retimer_info opae_rtm_info;
969 struct opae_retimer_status opae_rtm_status;
970 struct opae_eth_group_info opae_eth_grp_info;
971 struct opae_eth_group_region_info opae_eth_grp_reg_info;
972 int eth_group_num = 0;
973 uint64_t port_link_bitmap = 0, port_link_bit;
976 #define MAX_PORT_PER_RETIMER 4
978 IFPGA_RAWDEV_PMD_FUNC_TRACE();
980 if (!dev || !attr_name || !attr_value) {
981 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
985 adapter = ifpga_rawdev_get_priv(dev);
987 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
991 mgr = opae_adapter_get_mgr(adapter);
993 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
997 /* currently, eth_group_num is always 2 */
998 eth_group_num = opae_manager_get_eth_group_nums(mgr);
999 if (eth_group_num < 0)
1002 if (!strcmp(attr_name, "LineSideBaseMAC")) {
1003 /* Currently FPGA not implement, so just set all zeros*/
1004 *attr_value = (uint64_t)0;
1007 if (!strcmp(attr_name, "LineSideMACType")) {
1008 /* eth_group 0 on FPGA connect to LineSide */
1009 if (opae_manager_get_eth_group_info(mgr, 0,
1010 &opae_eth_grp_info))
1012 switch (opae_eth_grp_info.speed) {
1015 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
1019 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
1023 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
1028 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
1029 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1031 switch (opae_rtm_status.speed) {
1034 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1038 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1042 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1046 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1050 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1054 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1058 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1060 case MXD_SPEED_UNKNOWN:
1062 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1066 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1071 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1072 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1074 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1077 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1078 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1080 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1081 (uint64_t)opae_rtm_info.nums_retimer;
1085 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1086 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1088 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1092 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1093 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1094 p = i * MAX_PORT_PER_RETIMER;
1095 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1097 IFPGA_BIT_SET(port_link_bit, (p+j));
1098 port_link_bit &= port_link_bitmap;
1100 IFPGA_BIT_SET((*attr_value), q);
1106 if (!strcmp(attr_name, "LineSideBARIndex")) {
1107 /* eth_group 0 on FPGA connect to LineSide */
1108 if (opae_manager_get_eth_group_region_info(mgr, 0,
1109 &opae_eth_grp_reg_info))
1111 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1114 if (!strcmp(attr_name, "NICSideMACType")) {
1115 /* eth_group 1 on FPGA connect to NicSide */
1116 if (opae_manager_get_eth_group_info(mgr, 1,
1117 &opae_eth_grp_info))
1119 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1122 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1123 /* eth_group 1 on FPGA connect to NicSide */
1124 if (opae_manager_get_eth_group_info(mgr, 1,
1125 &opae_eth_grp_info))
1127 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1130 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1131 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1133 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1134 (uint64_t)opae_rtm_info.ports_per_fvl;
1138 if (!strcmp(attr_name, "NICSideLinkStatus"))
1140 if (!strcmp(attr_name, "NICSideBARIndex")) {
1141 /* eth_group 1 on FPGA connect to NicSide */
1142 if (opae_manager_get_eth_group_region_info(mgr, 1,
1143 &opae_eth_grp_reg_info))
1145 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1149 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1153 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1154 .dev_info_get = ifpga_rawdev_info_get,
1155 .dev_configure = ifpga_rawdev_configure,
1156 .dev_start = ifpga_rawdev_start,
1157 .dev_stop = ifpga_rawdev_stop,
1158 .dev_close = ifpga_rawdev_close,
1159 .dev_reset = ifpga_rawdev_reset,
1161 .queue_def_conf = NULL,
1162 .queue_setup = NULL,
1163 .queue_release = NULL,
1165 .attr_get = ifpga_rawdev_get_attr,
1168 .enqueue_bufs = NULL,
1169 .dequeue_bufs = NULL,
1174 .xstats_get_names = NULL,
1175 .xstats_get_by_name = NULL,
1176 .xstats_reset = NULL,
1178 .firmware_status_get = NULL,
1179 .firmware_version_get = NULL,
1180 .firmware_load = ifpga_rawdev_pr,
1181 .firmware_unload = NULL,
1183 .dev_selftest = NULL,
1187 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1188 u64 prop_id, u64 *val)
1190 struct feature_prop prop;
1192 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1193 prop.prop_id = prop_id;
1195 if (opae_manager_ifpga_get_prop(mgr, &prop))
1204 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1205 u64 prop_id, u64 val)
1207 struct feature_prop prop;
1209 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1210 prop.prop_id = prop_id;
1214 if (opae_manager_ifpga_set_prop(mgr, &prop))
1221 fme_err_read_seu_emr(struct opae_manager *mgr)
1226 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1230 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1232 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1236 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1241 static int fme_clear_warning_intr(struct opae_manager *mgr)
1245 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1248 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1250 if ((val & 0x40) != 0)
1251 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1256 static int fme_clean_fme_error(struct opae_manager *mgr)
1260 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1263 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1265 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1267 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1270 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1276 fme_err_handle_error0(struct opae_manager *mgr)
1278 struct feature_fme_error0 fme_error0;
1281 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1284 if (fme_clean_fme_error(mgr))
1287 fme_error0.csr = val;
1289 if (fme_error0.fabric_err)
1290 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1291 else if (fme_error0.fabfifo_overflow)
1292 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1293 else if (fme_error0.afu_acc_mode_err)
1294 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1295 else if (fme_error0.pcie0cdc_parity_err)
1296 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1297 else if (fme_error0.cvlcdc_parity_err)
1298 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1299 else if (fme_error0.fpgaseuerr)
1300 fme_err_read_seu_emr(mgr);
1302 /* clean the errors */
1303 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1310 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1312 struct feature_fme_ras_catfaterror fme_catfatal;
1315 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1318 fme_catfatal.csr = val;
1320 if (fme_catfatal.cci_fatal_err)
1321 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1322 else if (fme_catfatal.fabric_fatal_err)
1323 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1324 else if (fme_catfatal.pcie_poison_err)
1325 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1326 else if (fme_catfatal.inject_fata_err)
1327 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1328 else if (fme_catfatal.crc_catast_err)
1329 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1330 else if (fme_catfatal.injected_catast_err)
1331 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1332 else if (fme_catfatal.bmc_seu_catast_err)
1333 fme_err_read_seu_emr(mgr);
1339 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1341 struct feature_fme_ras_nonfaterror nonfaterr;
1344 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1347 nonfaterr.csr = val;
1349 if (nonfaterr.temp_thresh_ap1)
1350 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1351 else if (nonfaterr.temp_thresh_ap2)
1352 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1353 else if (nonfaterr.pcie_error)
1354 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1355 else if (nonfaterr.portfatal_error)
1356 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1357 else if (nonfaterr.proc_hot)
1358 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1359 else if (nonfaterr.afu_acc_mode_err)
1360 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1361 else if (nonfaterr.injected_nonfata_err) {
1362 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1363 fme_clear_warning_intr(mgr);
1364 } else if (nonfaterr.temp_thresh_AP6)
1365 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1366 else if (nonfaterr.power_thresh_AP1)
1367 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1368 else if (nonfaterr.power_thresh_AP2)
1369 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1370 else if (nonfaterr.mbp_err)
1371 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1377 fme_interrupt_handler(void *param)
1379 struct opae_manager *mgr = (struct opae_manager *)param;
1381 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1383 fme_err_handle_error0(mgr);
1384 fme_err_handle_nonfaterror(mgr);
1385 fme_err_handle_catfatal_error(mgr);
1389 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1390 int vec_start, rte_intr_callback_fn handler, void *arg)
1392 struct rte_intr_handle **intr_handle;
1394 int i = vec_start + 1;
1399 if (type == IFPGA_FME_IRQ)
1400 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1401 else if (type == IFPGA_AFU_IRQ)
1402 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1406 if ((*intr_handle) == NULL) {
1407 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1408 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1409 type == IFPGA_FME_IRQ ? 0 : vec_start);
1413 rte_intr_efd_disable(*intr_handle);
1415 rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1417 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1418 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1419 type == IFPGA_FME_IRQ ? 0 : vec_start);
1421 rte_intr_instance_free(*intr_handle);
1422 *intr_handle = NULL;
1429 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1430 enum ifpga_irq_type type, int vec_start, int count,
1431 rte_intr_callback_fn handler, const char *name,
1435 struct rte_intr_handle **intr_handle;
1436 struct opae_adapter *adapter;
1437 struct opae_manager *mgr;
1438 struct opae_accelerator *acc;
1439 int *intr_efds = NULL, nb_intr, i;
1441 if (!dev || !dev->rawdev)
1444 adapter = ifpga_rawdev_get_priv(dev->rawdev);
1448 mgr = opae_adapter_get_mgr(adapter);
1452 if (type == IFPGA_FME_IRQ) {
1453 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1455 } else if (type == IFPGA_AFU_IRQ) {
1457 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1465 *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1466 if (!(*intr_handle))
1469 if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1472 ret = rte_intr_efd_enable(*intr_handle, count);
1476 if (rte_intr_fd_set(*intr_handle,
1477 rte_intr_efds_index_get(*intr_handle, 0)))
1480 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1481 name, rte_intr_dev_fd_get(*intr_handle),
1482 rte_intr_fd_get(*intr_handle));
1484 if (type == IFPGA_FME_IRQ) {
1485 struct fpga_fme_err_irq_set err_irq_set;
1486 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1489 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1492 } else if (type == IFPGA_AFU_IRQ) {
1493 acc = opae_adapter_get_acc(adapter, port_id);
1497 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1499 intr_efds = calloc(nb_intr, sizeof(int));
1503 for (i = 0; i < nb_intr; i++)
1504 intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1506 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1513 /* register interrupt handler using DPDK API */
1514 ret = rte_intr_callback_register(*intr_handle,
1515 handler, (void *)arg);
1521 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1528 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1532 struct rte_rawdev *rawdev = NULL;
1533 struct ifpga_rawdev *dev = NULL;
1534 struct opae_adapter *adapter = NULL;
1535 struct opae_manager *mgr = NULL;
1536 struct opae_adapter_data_pci *data = NULL;
1537 char name[RTE_RAWDEV_NAME_MAX_LEN];
1541 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1546 memset(name, 0, sizeof(name));
1547 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1548 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1550 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1552 /* Allocate device structure */
1553 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1555 if (rawdev == NULL) {
1556 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1561 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1562 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1564 dev = ifpga_rawdev_allocate(rawdev);
1566 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1570 dev->aer_enable = 0;
1572 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1573 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1579 /* init opae_adapter_data_pci for device specific information */
1580 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1581 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1582 data->region[i].len = pci_dev->mem_resource[i].len;
1583 data->region[i].addr = pci_dev->mem_resource[i].addr;
1585 data->device_id = pci_dev->id.device_id;
1586 data->vendor_id = pci_dev->id.vendor_id;
1587 data->bus = pci_dev->addr.bus;
1588 data->devid = pci_dev->addr.devid;
1589 data->function = pci_dev->addr.function;
1590 data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1592 adapter = rawdev->dev_private;
1593 /* create a opae_adapter based on above device data */
1594 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1600 rawdev->dev_ops = &ifpga_rawdev_ops;
1601 rawdev->device = &pci_dev->device;
1602 rawdev->driver_name = pci_dev->driver->driver.name;
1604 /* must enumerate the adapter before use it */
1605 ret = opae_adapter_enumerate(adapter);
1609 /* get opae_manager to rawdev */
1610 mgr = opae_adapter_get_mgr(adapter);
1612 ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1613 fme_interrupt_handler, "fme_irq", mgr);
1618 ret = ifpga_monitor_start_func(dev);
1626 rte_rawdev_pmd_release(rawdev);
1632 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1635 struct rte_rawdev *rawdev;
1636 char name[RTE_RAWDEV_NAME_MAX_LEN];
1639 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1644 memset(name, 0, sizeof(name));
1645 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1646 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1648 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1649 name, rte_socket_id());
1651 rawdev = rte_rawdev_pmd_get_named_dev(name);
1653 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1657 /* rte_rawdev_close is called by pmd_release */
1658 ret = rte_rawdev_pmd_release(rawdev);
1660 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1666 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1667 struct rte_pci_device *pci_dev)
1669 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1670 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1674 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1676 IFPGA_RAWDEV_PMD_INFO("remove pci_dev %s", pci_dev->device.name);
1677 return ifpga_rawdev_destroy(pci_dev);
1680 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1681 .id_table = pci_ifpga_map,
1682 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1683 .probe = ifpga_rawdev_pci_probe,
1684 .remove = ifpga_rawdev_pci_remove,
1687 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1688 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1689 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1690 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1692 static const char * const valid_args[] = {
1693 #define IFPGA_ARG_NAME "ifpga"
1695 #define IFPGA_ARG_PORT "port"
1697 #define IFPGA_AFU_BTS "afu_bts"
1702 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1703 const char *value, void *extra_args)
1706 if (!value || !extra_args)
1709 size = strlen(value) + 1;
1710 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1711 if (!*(char **)extra_args)
1714 strlcpy(*(char **)extra_args, value, size);
1720 ifpga_vdev_parse_devargs(struct rte_devargs *devargs,
1721 struct ifpga_vdev_args *args)
1723 struct rte_kvargs *kvlist;
1728 if (!devargs || !args)
1731 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1733 IFPGA_RAWDEV_PMD_ERR("error when parsing devargs");
1737 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1738 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1739 &ifpga_rawdev_get_string_arg, &name) < 0) {
1740 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1744 strlcpy(args->bdf, name, sizeof(args->bdf));
1748 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1753 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1754 if (rte_kvargs_process(kvlist, IFPGA_ARG_PORT,
1755 &rte_ifpga_get_integer32_arg, &port) < 0) {
1756 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1763 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1771 rte_kvargs_free(kvlist);
1777 ifpga_cfg_probe(struct rte_vdev_device *vdev)
1779 struct rte_rawdev *rawdev = NULL;
1780 struct ifpga_rawdev *ifpga_dev;
1781 struct ifpga_vdev_args args;
1782 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1783 const char *vdev_name = NULL;
1786 vdev_name = rte_vdev_device_name(vdev);
1790 IFPGA_RAWDEV_PMD_INFO("probe ifpga virtual device %s", vdev_name);
1792 ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1796 memset(dev_name, 0, sizeof(dev_name));
1797 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1798 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1801 ifpga_dev = ifpga_rawdev_get(rawdev);
1805 for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1806 if (ifpga_dev->vdev_name[i] == NULL) {
1807 n = strlen(vdev_name) + 1;
1808 ifpga_dev->vdev_name[i] = rte_malloc(NULL, n, 0);
1809 if (ifpga_dev->vdev_name[i] == NULL)
1811 strlcpy(ifpga_dev->vdev_name[i], vdev_name, n);
1816 if (i >= IFPGA_MAX_VDEV) {
1817 IFPGA_RAWDEV_PMD_ERR("Can't create more virtual device!");
1821 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1822 args.port, args.bdf);
1823 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1824 dev_name, vdev->device.devargs->args);
1826 rte_free(ifpga_dev->vdev_name[i]);
1827 ifpga_dev->vdev_name[i] = NULL;
1834 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1836 struct rte_rawdev *rawdev = NULL;
1837 struct ifpga_rawdev *ifpga_dev;
1838 struct ifpga_vdev_args args;
1839 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1840 const char *vdev_name = NULL;
1841 char *tmp_vdev = NULL;
1844 vdev_name = rte_vdev_device_name(vdev);
1848 IFPGA_RAWDEV_PMD_INFO("remove ifpga virtual device %s", vdev_name);
1850 ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1854 memset(dev_name, 0, sizeof(dev_name));
1855 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1856 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1859 ifpga_dev = ifpga_rawdev_get(rawdev);
1863 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1864 args.port, args.bdf);
1865 ret = rte_eal_hotplug_remove(RTE_STR(IFPGA_BUS_NAME), dev_name);
1867 for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1868 tmp_vdev = ifpga_dev->vdev_name[i];
1869 if (tmp_vdev && !strcmp(tmp_vdev, vdev_name)) {
1871 ifpga_dev->vdev_name[i] = NULL;
1879 static struct rte_vdev_driver ifpga_cfg_driver = {
1880 .probe = ifpga_cfg_probe,
1881 .remove = ifpga_cfg_remove,
1884 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1885 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1886 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1891 struct rte_pci_bus *ifpga_get_pci_bus(void)
1893 return rte_ifpga_rawdev_pmd.bus;
1896 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1900 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1904 return rte_fpga_do_pr(dev, port, file);
1907 void ifpga_rawdev_cleanup(void)
1909 struct ifpga_rawdev *dev;
1912 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1913 dev = &ifpga_rawdevices[i];
1915 rte_rawdev_pmd_release(dev->rawdev);