2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
31 /* available timers */
33 /* overflow interrupt number */
34 #define SIG_OVERFLOW_TOTAL_NUM 0
36 /* output compare interrupt number */
37 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
40 #define PWM_TOTAL_NUM 0
42 /* input capture interrupt number */
43 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
47 #define VCOTUNE0_REG VCOTUNE
48 #define VCOTUNE1_REG VCOTUNE
49 #define VCOTUNE2_REG VCOTUNE
50 #define VCOTUNE3_REG VCOTUNE
51 #define VCOTUNE4_REG VCOTUNE
52 #define VCOVDET0_REG VCOTUNE
53 #define VCOVDET1_REG VCOTUNE
56 #define BL0_REG BL_CONFIG
57 #define BL1_REG BL_CONFIG
58 #define BL2_REG BL_CONFIG
59 #define BL3_REG BL_CONFIG
60 #define BL4_REG BL_CONFIG
61 #define BL5_REG BL_CONFIG
62 #define BLV_REG BL_CONFIG
63 #define BL_REG BL_CONFIG
76 #define WDP0_REG WDTCR
77 #define WDP1_REG WDTCR
78 #define WDP2_REG WDTCR
80 #define WDTOE_REG WDTCR
92 #define BBM_REG AVR_CONFIG
93 #define SLEEP_REG AVR_CONFIG
94 #define BLI_REG AVR_CONFIG
95 #define BD_REG AVR_CONFIG
96 #define TM_REG AVR_CONFIG
97 #define ACS0_REG AVR_CONFIG
98 #define ACS1_REG AVR_CONFIG
101 #define BD0_REG B_DET
102 #define BD1_REG B_DET
103 #define BD2_REG B_DET
104 #define BD3_REG B_DET
105 #define BD4_REG B_DET
106 #define BD5_REG B_DET
109 #define LC0_REG LOCKDET2
110 #define LC1_REG LOCKDET2
111 #define LC2_REG LOCKDET2
112 #define ULC0_REG LOCKDET2
113 #define ULC1_REG LOCKDET2
114 #define ULC2_REG LOCKDET2
115 #define LAT_REG LOCKDET2
116 #define EUD_REG LOCKDET2
119 #define LOC_REG TX_CNTL
120 #define TXK_REG TX_CNTL
121 #define TXE_REG TX_CNTL
122 #define FSK_REG TX_CNTL
161 #define DATA_REG BTCR
170 #define IOI0_REG IO_DATIN
171 #define IOI1_REG IO_DATIN
172 #define IOI2_REG IO_DATIN
173 #define IOI3_REG IO_DATIN
174 #define IOI4_REG IO_DATIN
175 #define IOI5_REG IO_DATIN
178 #define IOE0_REG IO_ENAB
179 #define IOE1_REG IO_ENAB
180 #define IOE2_REG IO_ENAB
181 #define IOE3_REG IO_ENAB
182 #define IOE4_REG IO_ENAB
183 #define IOE5_REG IO_ENAB
186 #define CS0_REG LOCKDET1
187 #define CS1_REG LOCKDET1
188 #define BOD_REG LOCKDET1
189 #define ENKO_REG LOCKDET1
190 #define UPOK_REG LOCKDET1
193 #define IOO0_REG IO_DATOUT
194 #define IOO1_REG IO_DATOUT
195 #define IOO2_REG IO_DATOUT
196 #define IOO3_REG IO_DATOUT
197 #define IOO4_REG IO_DATOUT
198 #define IOO5_REG IO_DATOUT
201 #define EER_REG DEECR
202 #define EEL_REG DEECR
203 #define EEU_REG DEECR
204 #define BSY_REG DEECR
207 #define PCF0_REG PWR_ATTEN
208 #define PCF1_REG PWR_ATTEN
209 #define PCF2_REG PWR_ATTEN
210 #define PCC0_REG PWR_ATTEN
211 #define PCC1_REG PWR_ATTEN
212 #define PCC2_REG PWR_ATTEN