2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER1_AVAILABLE
70 /* overflow interrupt number */
71 #define SIG_OVERFLOW0_NUM 0
72 #define SIG_OVERFLOW1_NUM 1
73 #define SIG_OVERFLOW_TOTAL_NUM 2
75 /* output compare interrupt number */
76 #define SIG_OUTPUT_COMPARE1_NUM 0
77 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
81 #define PWM_TOTAL_NUM 1
83 /* input capture interrupt number */
84 #define SIG_INPUT_CAPTURE1_NUM 0
85 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
89 #define WDP0_REG WDTCR
90 #define WDP1_REG WDTCR
91 #define WDP2_REG WDTCR
93 #define WDTOE_REG WDTCR
96 #define INT0_REG GIMSK
97 #define INT1_REG GIMSK
100 #define CS00_REG TCCR0
101 #define CS01_REG TCCR0
102 #define CS02_REG TCCR0
115 #define DDB0_REG DDRB
116 #define DDB1_REG DDRB
117 #define DDB2_REG DDRB
118 #define DDB3_REG DDRB
119 #define DDB4_REG DDRB
120 #define DDB5_REG DDRB
121 #define DDB6_REG DDRB
122 #define DDB7_REG DDRB
132 #define EEDR0_REG EEDR
133 #define EEDR1_REG EEDR
134 #define EEDR2_REG EEDR
135 #define EEDR3_REG EEDR
136 #define EEDR4_REG EEDR
137 #define EEDR5_REG EEDR
138 #define EEDR6_REG EEDR
139 #define EEDR7_REG EEDR
142 #define PIND0_REG PIND
143 #define PIND1_REG PIND
144 #define PIND2_REG PIND
145 #define PIND3_REG PIND
146 #define PIND4_REG PIND
147 #define PIND5_REG PIND
148 #define PIND6_REG PIND
151 #define PWM10_REG TCCR1A
152 #define PWM11_REG TCCR1A
153 #define COM1A0_REG TCCR1A
154 #define COM1A1_REG TCCR1A
157 #define DDD0_REG DDRD
158 #define DDD1_REG DDRD
159 #define DDD2_REG DDRD
160 #define DDD3_REG DDRD
161 #define DDD4_REG DDRD
162 #define DDD5_REG DDRD
163 #define DDD6_REG DDRD
166 #define CS10_REG TCCR1B
167 #define CS11_REG TCCR1B
168 #define CS12_REG TCCR1B
169 #define CTC1_REG TCCR1B
170 #define ICES1_REG TCCR1B
171 #define ICNC1_REG TCCR1B
174 #define INTF0_REG GIFR
175 #define INTF1_REG GIFR
178 #define TOIE0_REG TIMSK
179 #define TICIE1_REG TIMSK
180 #define OCIE1A_REG TIMSK
181 #define TOIE1_REG TIMSK
189 #define UDRIE_REG UCR
190 #define TXCIE_REG UCR
191 #define RXCIE_REG UCR
194 #define ACIS0_REG ACSR
195 #define ACIS1_REG ACSR
196 #define ACIC_REG ACSR
197 #define ACIE_REG ACSR
203 #define ICR1H0_REG ICR1H
204 #define ICR1H1_REG ICR1H
205 #define ICR1H2_REG ICR1H
206 #define ICR1H3_REG ICR1H
207 #define ICR1H4_REG ICR1H
208 #define ICR1H5_REG ICR1H
209 #define ICR1H6_REG ICR1H
210 #define ICR1H7_REG ICR1H
213 #define ICR1L0_REG ICR1L
214 #define ICR1L1_REG ICR1L
215 #define ICR1L2_REG ICR1L
216 #define ICR1L3_REG ICR1L
217 #define ICR1L4_REG ICR1L
218 #define ICR1L5_REG ICR1L
219 #define ICR1L6_REG ICR1L
220 #define ICR1L7_REG ICR1L
233 #define EERE_REG EECR
234 #define EEWE_REG EECR
235 #define EEMWE_REG EECR
238 #define TCNT1L0_REG TCNT1L
239 #define TCNT1L1_REG TCNT1L
240 #define TCNT1L2_REG TCNT1L
241 #define TCNT1L3_REG TCNT1L
242 #define TCNT1L4_REG TCNT1L
243 #define TCNT1L5_REG TCNT1L
244 #define TCNT1L6_REG TCNT1L
245 #define TCNT1L7_REG TCNT1L
248 #define TCNT1H0_REG TCNT1H
249 #define TCNT1H1_REG TCNT1H
250 #define TCNT1H2_REG TCNT1H
251 #define TCNT1H3_REG TCNT1H
252 #define TCNT1H4_REG TCNT1H
253 #define TCNT1H5_REG TCNT1H
254 #define TCNT1H6_REG TCNT1H
255 #define TCNT1H7_REG TCNT1H
258 #define PORTD0_REG PORTD
259 #define PORTD1_REG PORTD
260 #define PORTD2_REG PORTD
261 #define PORTD3_REG PORTD
262 #define PORTD4_REG PORTD
263 #define PORTD5_REG PORTD
264 #define PORTD6_REG PORTD
267 #define EEAR0_REG EEAR
268 #define EEAR1_REG EEAR
269 #define EEAR2_REG EEAR
270 #define EEAR3_REG EEAR
271 #define EEAR4_REG EEAR
272 #define EEAR5_REG EEAR
273 #define EEAR6_REG EEAR
276 #define PORTB0_REG PORTB
277 #define PORTB1_REG PORTB
278 #define PORTB2_REG PORTB
279 #define PORTB3_REG PORTB
280 #define PORTB4_REG PORTB
281 #define PORTB5_REG PORTB
282 #define PORTB6_REG PORTB
283 #define PORTB7_REG PORTB
286 #define TCNT00_REG TCNT0
287 #define TCNT01_REG TCNT0
288 #define TCNT02_REG TCNT0
289 #define TCNT03_REG TCNT0
290 #define TCNT04_REG TCNT0
291 #define TCNT05_REG TCNT0
292 #define TCNT06_REG TCNT0
293 #define TCNT07_REG TCNT0
296 #define UBRR0_REG UBRR
297 #define UBRR1_REG UBRR
298 #define UBRR2_REG UBRR
299 #define UBRR3_REG UBRR
300 #define UBRR4_REG UBRR
301 #define UBRR5_REG UBRR
302 #define UBRR6_REG UBRR
303 #define UBRR7_REG UBRR
306 #define TOV0_REG TIFR
307 #define ICF1_REG TIFR
308 #define OCF1A_REG TIFR
309 #define TOV1_REG TIFR
322 #define PINB0_REG PINB
323 #define PINB1_REG PINB
324 #define PINB2_REG PINB
325 #define PINB3_REG PINB
326 #define PINB4_REG PINB
327 #define PINB5_REG PINB
328 #define PINB6_REG PINB
329 #define PINB7_REG PINB
332 #define ISC00_REG MCUCR
333 #define ISC01_REG MCUCR
334 #define ISC10_REG MCUCR
335 #define ISC11_REG MCUCR
340 #define OCR1AH0_REG OCR1AH
341 #define OCR1AH1_REG OCR1AH
342 #define OCR1AH2_REG OCR1AH
343 #define OCR1AH3_REG OCR1AH
344 #define OCR1AH4_REG OCR1AH
345 #define OCR1AH5_REG OCR1AH
346 #define OCR1AH6_REG OCR1AH
347 #define OCR1AH7_REG OCR1AH
350 #define OCR1AL0_REG OCR1AL
351 #define OCR1AL1_REG OCR1AL
352 #define OCR1AL2_REG OCR1AL
353 #define OCR1AL3_REG OCR1AL
354 #define OCR1AL4_REG OCR1AL
355 #define OCR1AL5_REG OCR1AL
356 #define OCR1AL6_REG OCR1AL
357 #define OCR1AL7_REG OCR1AL
360 #define AIN0_PORT PORTB
363 #define AIN1_PORT PORTB
367 #define OC1_PORT PORTB
371 #define MOSI_PORT PORTB
374 #define MISO_PORT PORTB
377 #define SCK_PORT PORTB
380 #define RXD_PORT PORTD
383 #define TXD_PORT PORTD
386 #define INT0_PORT PORTD
389 #define INT1_PORT PORTD
392 #define T0_PORT PORTD
395 #define T1_PORT PORTD
398 #define ICP_PORT PORTD