2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE0_NUM 0
100 #define SIG_OUTPUT_COMPARE1A_NUM 1
101 #define SIG_OUTPUT_COMPARE1B_NUM 2
102 #define SIG_OUTPUT_COMPARE2_NUM 3
103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
110 #define PWM_TOTAL_NUM 4
112 /* input capture interrupt number */
113 #define SIG_INPUT_CAPTURE1_NUM 0
114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
118 #define WDP0_REG WDTCR
119 #define WDP1_REG WDTCR
120 #define WDP2_REG WDTCR
121 #define WDE_REG WDTCR
122 #define WDTOE_REG WDTCR
125 #define ICR1H0_REG ICR1H
126 #define ICR1H1_REG ICR1H
127 #define ICR1H2_REG ICR1H
128 #define ICR1H3_REG ICR1H
129 #define ICR1H4_REG ICR1H
130 #define ICR1H5_REG ICR1H
131 #define ICR1H6_REG ICR1H
132 #define ICR1H7_REG ICR1H
135 #define MUX0_REG ADMUX
136 #define MUX1_REG ADMUX
137 #define MUX2_REG ADMUX
138 #define MUX3_REG ADMUX
139 #define MUX4_REG ADMUX
140 #define ADLAR_REG ADMUX
141 #define REFS0_REG ADMUX
142 #define REFS1_REG ADMUX
145 #define CS00_REG TCCR0
146 #define CS01_REG TCCR0
147 #define CS02_REG TCCR0
148 #define WGM01_REG TCCR0
149 #define COM00_REG TCCR0
150 #define COM01_REG TCCR0
151 #define WGM00_REG TCCR0
152 #define FOC0_REG TCCR0
165 #define DDB0_REG DDRB
166 #define DDB1_REG DDRB
167 #define DDB2_REG DDRB
168 #define DDB3_REG DDRB
169 #define DDB4_REG DDRB
170 #define DDB5_REG DDRB
171 #define DDB6_REG DDRB
172 #define DDB7_REG DDRB
175 #define IVCE_REG GICR
176 #define IVSEL_REG GICR
177 #define INT2_REG GICR
178 #define INT0_REG GICR
179 #define INT1_REG GICR
182 #define SPI2X_REG SPSR
183 #define WCOL_REG SPSR
184 #define SPIF_REG SPSR
187 #define TWD0_REG TWDR
188 #define TWD1_REG TWDR
189 #define TWD2_REG TWDR
190 #define TWD3_REG TWDR
191 #define TWD4_REG TWDR
192 #define TWD5_REG TWDR
193 #define TWD6_REG TWDR
194 #define TWD7_REG TWDR
197 #define EEDR0_REG EEDR
198 #define EEDR1_REG EEDR
199 #define EEDR2_REG EEDR
200 #define EEDR3_REG EEDR
201 #define EEDR4_REG EEDR
202 #define EEDR5_REG EEDR
203 #define EEDR6_REG EEDR
204 #define EEDR7_REG EEDR
207 #define DDC0_REG DDRC
208 #define DDC1_REG DDRC
209 #define DDC2_REG DDRC
210 #define DDC3_REG DDRC
211 #define DDC4_REG DDRC
212 #define DDC5_REG DDRC
213 #define DDC6_REG DDRC
214 #define DDC7_REG DDRC
217 #define DDA0_REG DDRA
218 #define DDA1_REG DDRA
219 #define DDA2_REG DDRA
220 #define DDA3_REG DDRA
221 #define DDA4_REG DDRA
222 #define DDA5_REG DDRA
223 #define DDA6_REG DDRA
224 #define DDA7_REG DDRA
227 #define WGM10_REG TCCR1A
228 #define WGM11_REG TCCR1A
229 #define FOC1B_REG TCCR1A
230 #define FOC1A_REG TCCR1A
231 #define COM1B0_REG TCCR1A
232 #define COM1B1_REG TCCR1A
233 #define COM1A0_REG TCCR1A
234 #define COM1A1_REG TCCR1A
237 #define DDD0_REG DDRD
238 #define DDD1_REG DDRD
239 #define DDD2_REG DDRD
240 #define DDD3_REG DDRD
241 #define DDD4_REG DDRD
242 #define DDD5_REG DDRD
243 #define DDD6_REG DDRD
244 #define DDD7_REG DDRD
247 #define CS10_REG TCCR1B
248 #define CS11_REG TCCR1B
249 #define CS12_REG TCCR1B
250 #define WGM12_REG TCCR1B
251 #define WGM13_REG TCCR1B
252 #define ICES1_REG TCCR1B
253 #define ICNC1_REG TCCR1B
256 #define INTF2_REG GIFR
257 #define INTF0_REG GIFR
258 #define INTF1_REG GIFR
261 #define TOIE0_REG TIMSK
262 #define OCIE0_REG TIMSK
263 #define TOIE1_REG TIMSK
264 #define OCIE1B_REG TIMSK
265 #define OCIE1A_REG TIMSK
266 #define TICIE1_REG TIMSK
267 #define TOIE2_REG TIMSK
268 #define OCIE2_REG TIMSK
271 #define ADPS0_REG ADCSRA
272 #define ADPS1_REG ADCSRA
273 #define ADPS2_REG ADCSRA
274 #define ADIE_REG ADCSRA
275 #define ADIF_REG ADCSRA
276 #define ADATE_REG ADCSRA
277 #define ADSC_REG ADCSRA
278 #define ADEN_REG ADCSRA
281 #define MPCM_REG UCSRA
282 #define U2X_REG UCSRA
283 #define UPE_REG UCSRA
284 #define DOR_REG UCSRA
286 #define UDRE_REG UCSRA
287 #define TXC_REG UCSRA
288 #define RXC_REG UCSRA
291 #define SPDR0_REG SPDR
292 #define SPDR1_REG SPDR
293 #define SPDR2_REG SPDR
294 #define SPDR3_REG SPDR
295 #define SPDR4_REG SPDR
296 #define SPDR5_REG SPDR
297 #define SPDR6_REG SPDR
298 #define SPDR7_REG SPDR
301 #define PSR10_REG SFIOR
302 #define PSR2_REG SFIOR
303 #define PUD_REG SFIOR
304 #define ACME_REG SFIOR
305 #define ADTS0_REG SFIOR
306 #define ADTS1_REG SFIOR
307 #define ADTS2_REG SFIOR
310 #define ACIS0_REG ACSR
311 #define ACIS1_REG ACSR
312 #define ACIC_REG ACSR
313 #define ACIE_REG ACSR
316 #define ACBG_REG ACSR
330 #define OCR1BL0_REG OCR1BL
331 #define OCR1BL1_REG OCR1BL
332 #define OCR1BL2_REG OCR1BL
333 #define OCR1BL3_REG OCR1BL
334 #define OCR1BL4_REG OCR1BL
335 #define OCR1BL5_REG OCR1BL
336 #define OCR1BL6_REG OCR1BL
337 #define OCR1BL7_REG OCR1BL
340 #define TXB8_REG UCSRB
341 #define RXB8_REG UCSRB
342 #define UCSZ2_REG UCSRB
343 #define TXEN_REG UCSRB
344 #define RXEN_REG UCSRB
345 #define UDRIE_REG UCSRB
346 #define TXCIE_REG UCSRB
347 #define RXCIE_REG UCSRB
350 #define UCPOL_REG UCSRC
351 #define UCSZ0_REG UCSRC
352 #define UCSZ1_REG UCSRC
353 #define USBS_REG UCSRC
354 #define UPM0_REG UCSRC
355 #define UPM1_REG UCSRC
356 #define UMSEL_REG UCSRC
357 #define URSEL_REG UCSRC
370 #define OCR1BH0_REG OCR1BH
371 #define OCR1BH1_REG OCR1BH
372 #define OCR1BH2_REG OCR1BH
373 #define OCR1BH3_REG OCR1BH
374 #define OCR1BH4_REG OCR1BH
375 #define OCR1BH5_REG OCR1BH
376 #define OCR1BH6_REG OCR1BH
377 #define OCR1BH7_REG OCR1BH
390 #define PIND0_REG PIND
391 #define PIND1_REG PIND
392 #define PIND2_REG PIND
393 #define PIND3_REG PIND
394 #define PIND4_REG PIND
395 #define PIND5_REG PIND
396 #define PIND6_REG PIND
397 #define PIND7_REG PIND
400 #define ICR1L0_REG ICR1L
401 #define ICR1L1_REG ICR1L
402 #define ICR1L2_REG ICR1L
403 #define ICR1L3_REG ICR1L
404 #define ICR1L4_REG ICR1L
405 #define ICR1L5_REG ICR1L
406 #define ICR1L6_REG ICR1L
407 #define ICR1L7_REG ICR1L
410 #define UBRR8_REG UBRRH
411 #define UBRR9_REG UBRRH
412 #define UBRR10_REG UBRRH
413 #define UBRR11_REG UBRRH
416 #define TWBR0_REG TWBR
417 #define TWBR1_REG TWBR
418 #define TWBR2_REG TWBR
419 #define TWBR3_REG TWBR
420 #define TWBR4_REG TWBR
421 #define TWBR5_REG TWBR
422 #define TWBR6_REG TWBR
423 #define TWBR7_REG TWBR
426 #define ADCL0_REG ADCL
427 #define ADCL1_REG ADCL
428 #define ADCL2_REG ADCL
429 #define ADCL3_REG ADCL
430 #define ADCL4_REG ADCL
431 #define ADCL5_REG ADCL
432 #define ADCL6_REG ADCL
433 #define ADCL7_REG ADCL
436 #define UBRR0_REG UBRRL
437 #define UBRR1_REG UBRRL
438 #define UBRR2_REG UBRRL
439 #define UBRR3_REG UBRRL
440 #define UBRR4_REG UBRRL
441 #define UBRR5_REG UBRRL
442 #define UBRR6_REG UBRRL
443 #define UBRR7_REG UBRRL
446 #define EERE_REG EECR
447 #define EEWE_REG EECR
448 #define EEMWE_REG EECR
449 #define EERIE_REG EECR
452 #define SPMEN_REG SPMCSR
453 #define PGERS_REG SPMCSR
454 #define PGWRT_REG SPMCSR
455 #define BLBSET_REG SPMCSR
456 #define RWWSRE_REG SPMCSR
457 #define RWWSB_REG SPMCSR
458 #define SPMIE_REG SPMCSR
461 #define CAL0_REG OSCCAL
462 #define CAL1_REG OSCCAL
463 #define CAL2_REG OSCCAL
464 #define CAL3_REG OSCCAL
465 #define CAL4_REG OSCCAL
466 #define CAL5_REG OSCCAL
467 #define CAL6_REG OSCCAL
468 #define CAL7_REG OSCCAL
471 #define TCNT1L0_REG TCNT1L
472 #define TCNT1L1_REG TCNT1L
473 #define TCNT1L2_REG TCNT1L
474 #define TCNT1L3_REG TCNT1L
475 #define TCNT1L4_REG TCNT1L
476 #define TCNT1L5_REG TCNT1L
477 #define TCNT1L6_REG TCNT1L
478 #define TCNT1L7_REG TCNT1L
481 #define PORTB0_REG PORTB
482 #define PORTB1_REG PORTB
483 #define PORTB2_REG PORTB
484 #define PORTB3_REG PORTB
485 #define PORTB4_REG PORTB
486 #define PORTB5_REG PORTB
487 #define PORTB6_REG PORTB
488 #define PORTB7_REG PORTB
491 #define PORTD0_REG PORTD
492 #define PORTD1_REG PORTD
493 #define PORTD2_REG PORTD
494 #define PORTD3_REG PORTD
495 #define PORTD4_REG PORTD
496 #define PORTD5_REG PORTD
497 #define PORTD6_REG PORTD
498 #define PORTD7_REG PORTD
501 #define TCNT1H0_REG TCNT1H
502 #define TCNT1H1_REG TCNT1H
503 #define TCNT1H2_REG TCNT1H
504 #define TCNT1H3_REG TCNT1H
505 #define TCNT1H4_REG TCNT1H
506 #define TCNT1H5_REG TCNT1H
507 #define TCNT1H6_REG TCNT1H
508 #define TCNT1H7_REG TCNT1H
511 #define PORTC0_REG PORTC
512 #define PORTC1_REG PORTC
513 #define PORTC2_REG PORTC
514 #define PORTC3_REG PORTC
515 #define PORTC4_REG PORTC
516 #define PORTC5_REG PORTC
517 #define PORTC6_REG PORTC
518 #define PORTC7_REG PORTC
521 #define ADCH0_REG ADCH
522 #define ADCH1_REG ADCH
523 #define ADCH2_REG ADCH
524 #define ADCH3_REG ADCH
525 #define ADCH4_REG ADCH
526 #define ADCH5_REG ADCH
527 #define ADCH6_REG ADCH
528 #define ADCH7_REG ADCH
531 #define PORTA0_REG PORTA
532 #define PORTA1_REG PORTA
533 #define PORTA2_REG PORTA
534 #define PORTA3_REG PORTA
535 #define PORTA4_REG PORTA
536 #define PORTA5_REG PORTA
537 #define PORTA6_REG PORTA
538 #define PORTA7_REG PORTA
541 #define TWIE_REG TWCR
542 #define TWEN_REG TWCR
543 #define TWWC_REG TWCR
544 #define TWSTO_REG TWCR
545 #define TWSTA_REG TWCR
546 #define TWEA_REG TWCR
547 #define TWINT_REG TWCR
550 #define TCNT0_0_REG TCNT0
551 #define TCNT0_1_REG TCNT0
552 #define TCNT0_2_REG TCNT0
553 #define TCNT0_3_REG TCNT0
554 #define TCNT0_4_REG TCNT0
555 #define TCNT0_5_REG TCNT0
556 #define TCNT0_6_REG TCNT0
557 #define TCNT0_7_REG TCNT0
560 #define ISC2_REG MCUCSR
561 #define PORF_REG MCUCSR
562 #define EXTRF_REG MCUCSR
563 #define BORF_REG MCUCSR
564 #define WDRF_REG MCUCSR
565 #define JTRF_REG MCUCSR
566 #define JTD_REG MCUCSR
569 #define TWGCE_REG TWAR
570 #define TWA0_REG TWAR
571 #define TWA1_REG TWAR
572 #define TWA2_REG TWAR
573 #define TWA3_REG TWAR
574 #define TWA4_REG TWAR
575 #define TWA5_REG TWAR
576 #define TWA6_REG TWAR
579 #define CS20_REG TCCR2
580 #define CS21_REG TCCR2
581 #define CS22_REG TCCR2
582 #define WGM21_REG TCCR2
583 #define COM20_REG TCCR2
584 #define COM21_REG TCCR2
585 #define WGM20_REG TCCR2
586 #define FOC2_REG TCCR2
589 #define TOV0_REG TIFR
590 #define OCF0_REG TIFR
591 #define TOV1_REG TIFR
592 #define OCF1B_REG TIFR
593 #define OCF1A_REG TIFR
594 #define ICF1_REG TIFR
595 #define TOV2_REG TIFR
596 #define OCF2_REG TIFR
599 #define EEAR8_REG EEARH
602 #define TCNT2_0_REG TCNT2
603 #define TCNT2_1_REG TCNT2
604 #define TCNT2_2_REG TCNT2
605 #define TCNT2_3_REG TCNT2
606 #define TCNT2_4_REG TCNT2
607 #define TCNT2_5_REG TCNT2
608 #define TCNT2_6_REG TCNT2
609 #define TCNT2_7_REG TCNT2
612 #define EEAR0_REG EEARL
613 #define EEAR1_REG EEARL
614 #define EEAR2_REG EEARL
615 #define EEAR3_REG EEARL
616 #define EEAR4_REG EEARL
617 #define EEAR5_REG EEARL
618 #define EEAR6_REG EEARL
619 #define EEAR7_REG EEARL
622 #define TWPS0_REG TWSR
623 #define TWPS1_REG TWSR
624 #define TWS3_REG TWSR
625 #define TWS4_REG TWSR
626 #define TWS5_REG TWSR
627 #define TWS6_REG TWSR
628 #define TWS7_REG TWSR
631 #define PINC0_REG PINC
632 #define PINC1_REG PINC
633 #define PINC2_REG PINC
634 #define PINC3_REG PINC
635 #define PINC4_REG PINC
636 #define PINC5_REG PINC
637 #define PINC6_REG PINC
638 #define PINC7_REG PINC
641 #define OCR0_0_REG OCR0
642 #define OCR0_1_REG OCR0
643 #define OCR0_2_REG OCR0
644 #define OCR0_3_REG OCR0
645 #define OCR0_4_REG OCR0
646 #define OCR0_5_REG OCR0
647 #define OCR0_6_REG OCR0
648 #define OCR0_7_REG OCR0
651 #define PINA0_REG PINA
652 #define PINA1_REG PINA
653 #define PINA2_REG PINA
654 #define PINA3_REG PINA
655 #define PINA4_REG PINA
656 #define PINA5_REG PINA
657 #define PINA6_REG PINA
658 #define PINA7_REG PINA
661 #define ISC00_REG MCUCR
662 #define ISC01_REG MCUCR
663 #define ISC10_REG MCUCR
664 #define ISC11_REG MCUCR
665 #define SM0_REG MCUCR
666 #define SM1_REG MCUCR
668 #define SM2_REG MCUCR
671 #define OCR1AH0_REG OCR1AH
672 #define OCR1AH1_REG OCR1AH
673 #define OCR1AH2_REG OCR1AH
674 #define OCR1AH3_REG OCR1AH
675 #define OCR1AH4_REG OCR1AH
676 #define OCR1AH5_REG OCR1AH
677 #define OCR1AH6_REG OCR1AH
678 #define OCR1AH7_REG OCR1AH
681 #define OCR1AL0_REG OCR1AL
682 #define OCR1AL1_REG OCR1AL
683 #define OCR1AL2_REG OCR1AL
684 #define OCR1AL3_REG OCR1AL
685 #define OCR1AL4_REG OCR1AL
686 #define OCR1AL5_REG OCR1AL
687 #define OCR1AL6_REG OCR1AL
688 #define OCR1AL7_REG OCR1AL
691 #define SPR0_REG SPCR
692 #define SPR1_REG SPCR
693 #define CPHA_REG SPCR
694 #define CPOL_REG SPCR
695 #define MSTR_REG SPCR
696 #define DORD_REG SPCR
698 #define SPIE_REG SPCR
701 #define PINB0_REG PINB
702 #define PINB1_REG PINB
703 #define PINB2_REG PINB
704 #define PINB3_REG PINB
705 #define PINB4_REG PINB
706 #define PINB5_REG PINB
707 #define PINB6_REG PINB
708 #define PINB7_REG PINB
711 #define OCDR0_REG OCDR
712 #define OCDR1_REG OCDR
713 #define OCDR2_REG OCDR
714 #define OCDR3_REG OCDR
715 #define OCDR4_REG OCDR
716 #define OCDR5_REG OCDR
717 #define OCDR6_REG OCDR
718 #define OCDR7_REG OCDR
721 #define OCR2_0_REG OCR2
722 #define OCR2_1_REG OCR2
723 #define OCR2_2_REG OCR2
724 #define OCR2_3_REG OCR2
725 #define OCR2_4_REG OCR2
726 #define OCR2_5_REG OCR2
727 #define OCR2_6_REG OCR2
728 #define OCR2_7_REG OCR2
731 #define TCR2UB_REG ASSR
732 #define OCR2UB_REG ASSR
733 #define TCN2UB_REG ASSR
737 #define ADC0_PORT PORTA
740 #define ADC1_PORT PORTA
743 #define ADC2_PORT PORTA
746 #define ADC3_PORT PORTA
749 #define ADC4_PORT PORTA
752 #define ADc5_PORT PORTA
755 #define ADC6_PORT PORTA
758 #define ADC7_PORT PORTA
761 #define T0_PORT PORTB
764 #define T1_PORT PORTB
767 #define AIN0_PORT PORTB
770 #define AIN1_PORT PORTB
773 #define SS_PORT PORTB
776 #define MOSI_PORT PORTB
779 #define MISO_PORT PORTB
783 #define SCL_PORT PORTC
786 #define SDA_PORT PORTC
789 #define TMS_PORT PORTC
795 #define TOSC1_PORT PORTC
798 #define TOSC2_PORT PORTC
801 #define RXD_PORT PORTD
804 #define TXD_PORT PORTD
807 #define INT0_PORT PORTD
810 #define INT1_PORT PORTD
813 #define OC1B_PORT PORTD
816 #define OC1A_PORT PORTD
819 #define ICP_PORT PORTD
822 #define OC2_PORT PORTD