2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 3 */
66 #define TIMER3_PRESCALER_DIV_0 0
67 #define TIMER3_PRESCALER_DIV_1 1
68 #define TIMER3_PRESCALER_DIV_8 2
69 #define TIMER3_PRESCALER_DIV_64 3
70 #define TIMER3_PRESCALER_DIV_256 4
71 #define TIMER3_PRESCALER_DIV_1024 5
72 #define TIMER3_PRESCALER_DIV_FALL 6
73 #define TIMER3_PRESCALER_DIV_RISE 7
75 #define TIMER3_PRESCALER_REG_0 0
76 #define TIMER3_PRESCALER_REG_1 1
77 #define TIMER3_PRESCALER_REG_2 8
78 #define TIMER3_PRESCALER_REG_3 64
79 #define TIMER3_PRESCALER_REG_4 256
80 #define TIMER3_PRESCALER_REG_5 1024
81 #define TIMER3_PRESCALER_REG_6 -1
82 #define TIMER3_PRESCALER_REG_7 -2
84 /* prescalers timer 4 */
88 /* available timers */
89 #define TIMER0_AVAILABLE
90 #define TIMER0A_AVAILABLE
91 #define TIMER0B_AVAILABLE
92 #define TIMER1_AVAILABLE
93 #define TIMER1A_AVAILABLE
94 #define TIMER1B_AVAILABLE
95 #define TIMER1C_AVAILABLE
96 #define TIMER3_AVAILABLE
97 #define TIMER3A_AVAILABLE
98 #define TIMER3B_AVAILABLE
99 #define TIMER3C_AVAILABLE
100 #define TIMER4_AVAILABLE
101 #define TIMER4A_AVAILABLE
102 #define TIMER4B_AVAILABLE
104 /* overflow interrupt number */
105 #define SIG_OVERFLOW0_NUM 0
106 #define SIG_OVERFLOW1_NUM 1
107 #define SIG_OVERFLOW3_NUM 2
108 #define SIG_OVERFLOW4_NUM 3
109 #define SIG_OVERFLOW_TOTAL_NUM 4
111 /* output compare interrupt number */
112 #define SIG_OUTPUT_COMPARE0A_NUM 0
113 #define SIG_OUTPUT_COMPARE0B_NUM 1
114 #define SIG_OUTPUT_COMPARE1A_NUM 2
115 #define SIG_OUTPUT_COMPARE1B_NUM 3
116 #define SIG_OUTPUT_COMPARE1C_NUM 4
117 #define SIG_OUTPUT_COMPARE3A_NUM 5
118 #define SIG_OUTPUT_COMPARE3B_NUM 6
119 #define SIG_OUTPUT_COMPARE3C_NUM 7
120 #define SIG_OUTPUT_COMPARE4_NUM 8
121 #define SIG_OUTPUT_COMPARE4A_NUM 9
122 #define SIG_OUTPUT_COMPARE4B_NUM 10
123 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 11
137 #define PWM_TOTAL_NUM 11
139 /* input capture interrupt number */
140 #define SIG_INPUT_CAPTURE1_NUM 0
141 #define SIG_INPUT_CAPTURE3_NUM 1
142 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
146 #define MUX0_REG ADMUX
147 #define MUX1_REG ADMUX
148 #define MUX2_REG ADMUX
149 #define MUX3_REG ADMUX
150 #define MUX4_REG ADMUX
151 #define ADLAR_REG ADMUX
152 #define REFS0_REG ADMUX
153 #define REFS1_REG ADMUX
156 #define SUSPE_REG UDIEN
157 #define SOFE_REG UDIEN
158 #define EORSTE_REG UDIEN
159 #define WAKEUPE_REG UDIEN
160 #define EORSME_REG UDIEN
161 #define UPRSME_REG UDIEN
164 #define WDP0_REG WDTCSR
165 #define WDP1_REG WDTCSR
166 #define WDP2_REG WDTCSR
167 #define WDE_REG WDTCSR
168 #define WDCE_REG WDTCSR
169 #define WDP3_REG WDTCSR
170 #define WDIE_REG WDTCSR
171 #define WDIF_REG WDTCSR
174 #define EEDR0_REG EEDR
175 #define EEDR1_REG EEDR
176 #define EEDR2_REG EEDR
177 #define EEDR3_REG EEDR
178 #define EEDR4_REG EEDR
179 #define EEDR5_REG EEDR
180 #define EEDR6_REG EEDR
181 #define EEDR7_REG EEDR
184 #define OCR0B_0_REG OCR0B
185 #define OCR0B_1_REG OCR0B
186 #define OCR0B_2_REG OCR0B
187 #define OCR0B_3_REG OCR0B
188 #define OCR0B_4_REG OCR0B
189 #define OCR0B_5_REG OCR0B
190 #define OCR0B_6_REG OCR0B
191 #define OCR0B_7_REG OCR0B
194 #define SUSPI_REG UDINT
195 #define SOFI_REG UDINT
196 #define EORSTI_REG UDINT
197 #define WAKEUPI_REG UDINT
198 #define EORSMI_REG UDINT
199 #define UPRSMI_REG UDINT
202 #define EPRST0_REG UERST
203 #define EPRST1_REG UERST
204 #define EPRST2_REG UERST
205 #define EPRST3_REG UERST
206 #define EPRST4_REG UERST
207 #define EPRST5_REG UERST
208 #define EPRST6_REG UERST
211 #define RAMPZ0_REG RAMPZ
214 #define ALLOC_REG UECFG1X
215 #define EPBK0_REG UECFG1X
216 #define EPBK1_REG UECFG1X
217 #define EPSIZE0_REG UECFG1X
218 #define EPSIZE1_REG UECFG1X
219 #define EPSIZE2_REG UECFG1X
222 #define SPDR0_REG SPDR
223 #define SPDR1_REG SPDR
224 #define SPDR2_REG SPDR
225 #define SPDR3_REG SPDR
226 #define SPDR4_REG SPDR
227 #define SPDR5_REG SPDR
228 #define SPDR6_REG SPDR
229 #define SPDR7_REG SPDR
232 #define SPI2X_REG SPSR
233 #define WCOL_REG SPSR
234 #define SPIF_REG SPSR
247 #define ICR1L0_REG ICR1L
248 #define ICR1L1_REG ICR1L
249 #define ICR1L2_REG ICR1L
250 #define ICR1L3_REG ICR1L
251 #define ICR1L4_REG ICR1L
252 #define ICR1L5_REG ICR1L
253 #define ICR1L6_REG ICR1L
254 #define ICR1L7_REG ICR1L
257 #define EEAR8_REG EEARH
258 #define EEAR9_REG EEARH
259 #define EEAR10_REG EEARH
260 #define EEAR11_REG EEARH
263 #define TCNT1L0_REG TCNT1L
264 #define TCNT1L1_REG TCNT1L
265 #define TCNT1L2_REG TCNT1L
266 #define TCNT1L3_REG TCNT1L
267 #define TCNT1L4_REG TCNT1L
268 #define TCNT1L5_REG TCNT1L
269 #define TCNT1L6_REG TCNT1L
270 #define TCNT1L7_REG TCNT1L
273 #define PORTD0_REG PORTD
274 #define PORTD1_REG PORTD
275 #define PORTD2_REG PORTD
276 #define PORTD3_REG PORTD
277 #define PORTD4_REG PORTD
278 #define PORTD5_REG PORTD
279 #define PORTD6_REG PORTD
280 #define PORTD7_REG PORTD
283 #define PORTE2_REG PORTE
284 #define PORTE6_REG PORTE
287 #define TCNT1H0_REG TCNT1H
288 #define TCNT1H1_REG TCNT1H
289 #define TCNT1H2_REG TCNT1H
290 #define TCNT1H3_REG TCNT1H
291 #define TCNT1H4_REG TCNT1H
292 #define TCNT1H5_REG TCNT1H
293 #define TCNT1H6_REG TCNT1H
294 #define TCNT1H7_REG TCNT1H
297 #define PORTC6_REG PORTC
298 #define PORTC7_REG PORTC
301 #define INT0_REG EIMSK
302 #define INT1_REG EIMSK
303 #define INT2_REG EIMSK
304 #define INT3_REG EIMSK
305 #define INT4_REG EIMSK
306 #define INT5_REG EIMSK
307 #define INT6_REG EIMSK
308 #define INT7_REG EIMSK
311 #define UDR1_0_REG UDR1
312 #define UDR1_1_REG UDR1
313 #define UDR1_2_REG UDR1
314 #define UDR1_3_REG UDR1
315 #define UDR1_4_REG UDR1
316 #define UDR1_5_REG UDR1
317 #define UDR1_6_REG UDR1
318 #define UDR1_7_REG UDR1
321 #define ISC40_REG EICRB
322 #define ISC41_REG EICRB
323 #define ISC50_REG EICRB
324 #define ISC51_REG EICRB
325 #define ISC60_REG EICRB
326 #define ISC61_REG EICRB
327 #define ISC70_REG EICRB
328 #define ISC71_REG EICRB
331 #define DAT0_REG UEDATX
332 #define DAT1_REG UEDATX
333 #define DAT2_REG UEDATX
334 #define DAT3_REG UEDATX
335 #define DAT4_REG UEDATX
336 #define DAT5_REG UEDATX
337 #define DAT6_REG UEDATX
338 #define DAT7_REG UEDATX
341 #define ISC00_REG EICRA
342 #define ISC01_REG EICRA
343 #define ISC10_REG EICRA
344 #define ISC11_REG EICRA
345 #define ISC20_REG EICRA
346 #define ISC21_REG EICRA
347 #define ISC30_REG EICRA
348 #define ISC31_REG EICRA
351 #define EPDIR_REG UECFG0X
352 #define EPTYPE0_REG UECFG0X
353 #define EPTYPE1_REG UECFG0X
356 #define ADC0D_REG DIDR0
357 #define ADC1D_REG DIDR0
358 #define ADC2D_REG DIDR0
359 #define ADC3D_REG DIDR0
360 #define ADC4D_REG DIDR0
361 #define ADC5D_REG DIDR0
362 #define ADC6D_REG DIDR0
363 #define ADC7D_REG DIDR0
366 #define AIN0D_REG DIDR1
367 #define AIN1D_REG DIDR1
370 #define ADC8D_REG DIDR2
371 #define ADC9D_REG DIDR2
372 #define ADC10D_REG DIDR2
373 #define ADC11D_REG DIDR2
374 #define ADC12D_REG DIDR2
375 #define ADC13D_REG DIDR2
378 #define DDF0_REG DDRF
379 #define DDF1_REG DDRF
380 #define DDF4_REG DDRF
381 #define DDF5_REG DDRF
382 #define DDF6_REG DDRF
383 #define DDF7_REG DDRF
386 #define EXCKSEL0_REG CLKSEL1
387 #define EXCKSEL1_REG CLKSEL1
388 #define EXCKSEL2_REG CLKSEL1
389 #define EXCKSEL3_REG CLKSEL1
390 #define RCCKSEL0_REG CLKSEL1
391 #define RCCKSEL1_REG CLKSEL1
392 #define RCCKSEL2_REG CLKSEL1
393 #define RCCKSEL3_REG CLKSEL1
396 #define CLKS_REG CLKSEL0
397 #define EXTE_REG CLKSEL0
398 #define RCE_REG CLKSEL0
399 #define EXSUT0_REG CLKSEL0
400 #define EXSUT1_REG CLKSEL0
401 #define RCSUT0_REG CLKSEL0
402 #define RCSUT1_REG CLKSEL0
405 #define CLKPS0_REG CLKPR
406 #define CLKPS1_REG CLKPR
407 #define CLKPS2_REG CLKPR
408 #define CLKPS3_REG CLKPR
409 #define CLKPCE_REG CLKPR
422 #define UENUM_0_REG UENUM
423 #define UENUM_1_REG UENUM
424 #define UENUM_2_REG UENUM
427 #define UBRR_0_REG UBRR1L
428 #define UBRR_1_REG UBRR1L
429 #define UBRR_2_REG UBRR1L
430 #define UBRR_3_REG UBRR1L
431 #define UBRR_4_REG UBRR1L
432 #define UBRR_5_REG UBRR1L
433 #define UBRR_6_REG UBRR1L
434 #define UBRR_7_REG UBRR1L
437 #define DDC6_REG DDRC
438 #define DDC7_REG DDRC
441 #define OCR3AL0_REG OCR3AL
442 #define OCR3AL1_REG OCR3AL
443 #define OCR3AL2_REG OCR3AL
444 #define OCR3AL3_REG OCR3AL
445 #define OCR3AL4_REG OCR3AL
446 #define OCR3AL5_REG OCR3AL
447 #define OCR3AL6_REG OCR3AL
448 #define OCR3AL7_REG OCR3AL
451 #define WGM10_REG TCCR1A
452 #define WGM11_REG TCCR1A
453 #define COM1C0_REG TCCR1A
454 #define COM1C1_REG TCCR1A
455 #define COM1B0_REG TCCR1A
456 #define COM1B1_REG TCCR1A
457 #define COM1A0_REG TCCR1A
458 #define COM1A1_REG TCCR1A
461 #define OCR3AH0_REG OCR3AH
462 #define OCR3AH1_REG OCR3AH
463 #define OCR3AH2_REG OCR3AH
464 #define OCR3AH3_REG OCR3AH
465 #define OCR3AH4_REG OCR3AH
466 #define OCR3AH5_REG OCR3AH
467 #define OCR3AH6_REG OCR3AH
468 #define OCR3AH7_REG OCR3AH
471 #define CS10_REG TCCR1B
472 #define CS11_REG TCCR1B
473 #define CS12_REG TCCR1B
474 #define WGM12_REG TCCR1B
475 #define WGM13_REG TCCR1B
476 #define ICES1_REG TCCR1B
477 #define ICNC1_REG TCCR1B
480 #define CAL0_REG OSCCAL
481 #define CAL1_REG OSCCAL
482 #define CAL2_REG OSCCAL
483 #define CAL3_REG OSCCAL
484 #define CAL4_REG OSCCAL
485 #define CAL5_REG OSCCAL
486 #define CAL6_REG OSCCAL
487 #define CAL7_REG OSCCAL
490 #define DDD0_REG DDRD
491 #define DDD1_REG DDRD
492 #define DDD2_REG DDRD
493 #define DDD3_REG DDRD
494 #define DDD4_REG DDRD
495 #define DDD5_REG DDRD
496 #define DDD6_REG DDRD
497 #define DDD7_REG DDRD
500 #define OCR4A0_REG OCR4A
501 #define OCR4A1_REG OCR4A
502 #define OCR4A2_REG OCR4A
503 #define OCR4A3_REG OCR4A
504 #define OCR4A4_REG OCR4A
505 #define OCR4A5_REG OCR4A
506 #define OCR4A6_REG OCR4A
507 #define OCR4A7_REG OCR4A
510 #define OCR4C0_REG OCR4C
511 #define OCR4C1_REG OCR4C
512 #define OCR4C2_REG OCR4C
513 #define OCR4C3_REG OCR4C
514 #define OCR4C4_REG OCR4C
515 #define OCR4C5_REG OCR4C
516 #define OCR4C6_REG OCR4C
517 #define OCR4C7_REG OCR4C
520 #define OCR4B0_REG OCR4B
521 #define OCR4B1_REG OCR4B
522 #define OCR4B2_REG OCR4B
523 #define OCR4B3_REG OCR4B
524 #define OCR4B4_REG OCR4B
525 #define OCR4B5_REG OCR4B
526 #define OCR4B6_REG OCR4B
527 #define OCR4B7_REG OCR4B
530 #define OCR4D0_REG OCR4D
531 #define OCR4D1_REG OCR4D
532 #define OCR4D2_REG OCR4D
533 #define OCR4D3_REG OCR4D
534 #define OCR4D4_REG OCR4D
535 #define OCR4D5_REG OCR4D
536 #define OCR4D6_REG OCR4D
537 #define OCR4D7_REG OCR4D
540 #define GPIOR10_REG GPIOR1
541 #define GPIOR11_REG GPIOR1
542 #define GPIOR12_REG GPIOR1
543 #define GPIOR13_REG GPIOR1
544 #define GPIOR14_REG GPIOR1
545 #define GPIOR15_REG GPIOR1
546 #define GPIOR16_REG GPIOR1
547 #define GPIOR17_REG GPIOR1
550 #define GPIOR00_REG GPIOR0
551 #define GPIOR01_REG GPIOR0
552 #define GPIOR02_REG GPIOR0
553 #define GPIOR03_REG GPIOR0
554 #define GPIOR04_REG GPIOR0
555 #define GPIOR05_REG GPIOR0
556 #define GPIOR06_REG GPIOR0
557 #define GPIOR07_REG GPIOR0
560 #define GPIOR20_REG GPIOR2
561 #define GPIOR21_REG GPIOR2
562 #define GPIOR22_REG GPIOR2
563 #define GPIOR23_REG GPIOR2
564 #define GPIOR24_REG GPIOR2
565 #define GPIOR25_REG GPIOR2
566 #define GPIOR26_REG GPIOR2
567 #define GPIOR27_REG GPIOR2
570 #define RCFREQ_REG RCCTRL
573 #define DETACH_REG UDCON
574 #define RMWKUP_REG UDCON
575 #define LSM_REG UDCON
576 #define RSTCPU_REG UDCON
579 #define PCIE0_REG PCICR
582 #define VBUSTI_REG USBINT
585 #define TCNT0_0_REG TCNT0
586 #define TCNT0_1_REG TCNT0
587 #define TCNT0_2_REG TCNT0
588 #define TCNT0_3_REG TCNT0
589 #define TCNT0_4_REG TCNT0
590 #define TCNT0_5_REG TCNT0
591 #define TCNT0_6_REG TCNT0
592 #define TCNT0_7_REG TCNT0
595 #define TC40_REG TCNT4
596 #define TC41_REG TCNT4
597 #define TC42_REG TCNT4
598 #define TC43_REG TCNT4
599 #define TC44_REG TCNT4
600 #define TC45_REG TCNT4
601 #define TC46_REG TCNT4
602 #define TC47_REG TCNT4
605 #define TC48_REG TC4H
606 #define TC49_REG TC4H
607 #define TC410_REG TC4H
610 #define UVREGE_REG UHWCON
613 #define CS00_REG TCCR0B
614 #define CS01_REG TCCR0B
615 #define CS02_REG TCCR0B
616 #define WGM02_REG TCCR0B
617 #define FOC0B_REG TCCR0B
618 #define FOC0A_REG TCCR0B
621 #define FNCERR_REG UDMFN
624 #define WGM00_REG TCCR0A
625 #define WGM01_REG TCCR0A
626 #define COM0B0_REG TCCR0A
627 #define COM0B1_REG TCCR0A
628 #define COM0A0_REG TCCR0A
629 #define COM0A1_REG TCCR0A
632 #define TOV4_REG TIFR4
633 #define OCF4B_REG TIFR4
634 #define OCF4A_REG TIFR4
635 #define OCF4D_REG TIFR4
638 #define TOV3_REG TIFR3
639 #define OCF3A_REG TIFR3
640 #define OCF3B_REG TIFR3
641 #define OCF3C_REG TIFR3
642 #define ICF3_REG TIFR3
645 #define SPR0_REG SPCR
646 #define SPR1_REG SPCR
647 #define CPHA_REG SPCR
648 #define CPOL_REG SPCR
649 #define MSTR_REG SPCR
650 #define DORD_REG SPCR
652 #define SPIE_REG SPCR
655 #define TOV1_REG TIFR1
656 #define OCF1A_REG TIFR1
657 #define OCF1B_REG TIFR1
658 #define OCF1C_REG TIFR1
659 #define ICF1_REG TIFR1
662 #define BYCT0_REG UEBCLX
663 #define BYCT1_REG UEBCLX
664 #define BYCT2_REG UEBCLX
665 #define BYCT3_REG UEBCLX
666 #define BYCT4_REG UEBCLX
667 #define BYCT5_REG UEBCLX
668 #define BYCT6_REG UEBCLX
669 #define BYCT7_REG UEBCLX
672 #define OCR3CH0_REG OCR3CH
673 #define OCR3CH1_REG OCR3CH
674 #define OCR3CH2_REG OCR3CH
675 #define OCR3CH3_REG OCR3CH
676 #define OCR3CH4_REG OCR3CH
677 #define OCR3CH5_REG OCR3CH
678 #define OCR3CH6_REG OCR3CH
679 #define OCR3CH7_REG OCR3CH
682 #define CURRBK0_REG UESTA1X
683 #define CURRBK1_REG UESTA1X
684 #define CTRLDIR_REG UESTA1X
687 #define OCR3CL0_REG OCR3CL
688 #define OCR3CL1_REG OCR3CL
689 #define OCR3CL2_REG OCR3CL
690 #define OCR3CL3_REG OCR3CL
691 #define OCR3CL4_REG OCR3CL
692 #define OCR3CL5_REG OCR3CL
693 #define OCR3CL6_REG OCR3CL
694 #define OCR3CL7_REG OCR3CL
697 #define PSRSYNC_REG GTCCR
698 #define TSM_REG GTCCR
701 #define ICR1H0_REG ICR1H
702 #define ICR1H1_REG ICR1H
703 #define ICR1H2_REG ICR1H
704 #define ICR1H3_REG ICR1H
705 #define ICR1H4_REG ICR1H
706 #define ICR1H5_REG ICR1H
707 #define ICR1H6_REG ICR1H
708 #define ICR1H7_REG ICR1H
711 #define FOC3C_REG TCCR3C
712 #define FOC3B_REG TCCR3C
713 #define FOC3A_REG TCCR3C
716 #define CS30_REG TCCR3B
717 #define CS31_REG TCCR3B
718 #define CS32_REG TCCR3B
719 #define WGM32_REG TCCR3B
720 #define WGM33_REG TCCR3B
721 #define ICES3_REG TCCR3B
722 #define ICNC3_REG TCCR3B
725 #define WGM30_REG TCCR3A
726 #define WGM31_REG TCCR3A
727 #define COM3C0_REG TCCR3A
728 #define COM3C1_REG TCCR3A
729 #define COM3B0_REG TCCR3A
730 #define COM3B1_REG TCCR3A
731 #define COM3A0_REG TCCR3A
732 #define COM3A1_REG TCCR3A
735 #define TXINI_REG UEINTX
736 #define STALLEDI_REG UEINTX
737 #define RXOUTI_REG UEINTX
738 #define RXSTPI_REG UEINTX
739 #define NAKOUTI_REG UEINTX
740 #define RWAL_REG UEINTX
741 #define NAKINI_REG UEINTX
742 #define FIFOCON_REG UEINTX
745 #define OCR1BL0_REG OCR1BL
746 #define OCR1BL1_REG OCR1BL
747 #define OCR1BL2_REG OCR1BL
748 #define OCR1BL3_REG OCR1BL
749 #define OCR1BL4_REG OCR1BL
750 #define OCR1BL5_REG OCR1BL
751 #define OCR1BL6_REG OCR1BL
752 #define OCR1BL7_REG OCR1BL
755 #define TCNT3H0_REG TCNT3H
756 #define TCNT3H1_REG TCNT3H
757 #define TCNT3H2_REG TCNT3H
758 #define TCNT3H3_REG TCNT3H
759 #define TCNT3H4_REG TCNT3H
760 #define TCNT3H5_REG TCNT3H
761 #define TCNT3H6_REG TCNT3H
762 #define TCNT3H7_REG TCNT3H
765 #define OCR1BH0_REG OCR1BH
766 #define OCR1BH1_REG OCR1BH
767 #define OCR1BH2_REG OCR1BH
768 #define OCR1BH3_REG OCR1BH
769 #define OCR1BH4_REG OCR1BH
770 #define OCR1BH5_REG OCR1BH
771 #define OCR1BH6_REG OCR1BH
772 #define OCR1BH7_REG OCR1BH
775 #define TCNT3L0_REG TCNT3L
776 #define TCNT3L1_REG TCNT3L
777 #define TCNT3L2_REG TCNT3L
778 #define TCNT3L3_REG TCNT3L
779 #define TCNT3L4_REG TCNT3L
780 #define TCNT3L5_REG TCNT3L
781 #define TCNT3L6_REG TCNT3L
782 #define TCNT3L7_REG TCNT3L
795 #define VBUSTE_REG USBCON
796 #define OTGPADE_REG USBCON
797 #define FRZCLK_REG USBCON
798 #define USBE_REG USBCON
801 #define JTRF_REG MCUSR
802 #define PORF_REG MCUSR
803 #define EXTRF_REG MCUSR
804 #define BORF_REG MCUSR
805 #define WDRF_REG MCUSR
808 #define EERE_REG EECR
809 #define EEPE_REG EECR
810 #define EEMPE_REG EECR
811 #define EERIE_REG EECR
812 #define EEPM0_REG EECR
813 #define EEPM1_REG EECR
822 #define PCIF0_REG PCIFR
825 #define EPEN_REG UECONX
826 #define RSTDT_REG UECONX
827 #define STALLRQC_REG UECONX
828 #define STALLRQ_REG UECONX
831 #define PDIV0_REG PLLFRQ
832 #define PDIV1_REG PLLFRQ
833 #define PDIV2_REG PLLFRQ
834 #define PDIV3_REG PLLFRQ
835 #define PLLTM0_REG PLLFRQ
836 #define PLLTM1_REG PLLFRQ
837 #define PLLUSB_REG PLLFRQ
838 #define PINMUX_REG PLLFRQ
841 #define EPINT0_REG UEINT
842 #define EPINT1_REG UEINT
843 #define EPINT2_REG UEINT
844 #define EPINT3_REG UEINT
845 #define EPINT4_REG UEINT
846 #define EPINT5_REG UEINT
847 #define EPINT6_REG UEINT
850 #define EEAR0_REG EEARL
851 #define EEAR1_REG EEARL
852 #define EEAR2_REG EEARL
853 #define EEAR3_REG EEARL
854 #define EEAR4_REG EEARL
855 #define EEAR5_REG EEARL
856 #define EEAR6_REG EEARL
857 #define EEAR7_REG EEARL
860 #define JTD_REG MCUCR
861 #define IVCE_REG MCUCR
862 #define IVSEL_REG MCUCR
863 #define PUD_REG MCUCR
866 #define OCR1CL0_REG OCR1CL
867 #define OCR1CL1_REG OCR1CL
868 #define OCR1CL2_REG OCR1CL
869 #define OCR1CL3_REG OCR1CL
870 #define OCR1CL4_REG OCR1CL
871 #define OCR1CL5_REG OCR1CL
872 #define OCR1CL6_REG OCR1CL
873 #define OCR1CL7_REG OCR1CL
876 #define OCR1CH0_REG OCR1CH
877 #define OCR1CH1_REG OCR1CH
878 #define OCR1CH2_REG OCR1CH
879 #define OCR1CH3_REG OCR1CH
880 #define OCR1CH4_REG OCR1CH
881 #define OCR1CH5_REG OCR1CH
882 #define OCR1CH6_REG OCR1CH
883 #define OCR1CH7_REG OCR1CH
886 #define OCDR0_REG OCDR
887 #define OCDR1_REG OCDR
888 #define OCDR2_REG OCDR
889 #define OCDR3_REG OCDR
890 #define OCDR4_REG OCDR
891 #define OCDR5_REG OCDR
892 #define OCDR6_REG OCDR
893 #define OCDR7_REG OCDR
896 #define VBUS_REG USBSTA
897 #define SPEED_REG USBSTA
900 #define TXINE_REG UEIENX
901 #define STALLEDE_REG UEIENX
902 #define RXOUTE_REG UEIENX
903 #define RXSTPE_REG UEIENX
904 #define NAKOUTE_REG UEIENX
905 #define NAKINE_REG UEIENX
906 #define FLERRE_REG UEIENX
909 #define TXB81_REG UCSR1B
910 #define RXB81_REG UCSR1B
911 #define UCSZ12_REG UCSR1B
912 #define TXEN1_REG UCSR1B
913 #define RXEN1_REG UCSR1B
914 #define UDRIE1_REG UCSR1B
915 #define TXCIE1_REG UCSR1B
916 #define RXCIE1_REG UCSR1B
919 #define UCPOL1_REG UCSR1C
920 #define UCSZ10_REG UCSR1C
921 #define UCSZ11_REG UCSR1C
922 #define USBS1_REG UCSR1C
923 #define UPM10_REG UCSR1C
924 #define UPM11_REG UCSR1C
925 #define UMSEL10_REG UCSR1C
926 #define UMSEL11_REG UCSR1C
929 #define MPCM1_REG UCSR1A
930 #define U2X1_REG UCSR1A
931 #define UPE1_REG UCSR1A
932 #define DOR1_REG UCSR1A
933 #define FE1_REG UCSR1A
934 #define UDRE1_REG UCSR1A
935 #define TXC1_REG UCSR1A
936 #define RXC1_REG UCSR1A
939 #define DDB0_REG DDRB
940 #define DDB1_REG DDRB
941 #define DDB2_REG DDRB
942 #define DDB3_REG DDRB
943 #define DDB4_REG DDRB
944 #define DDB5_REG DDRB
945 #define DDB6_REG DDRB
946 #define DDB7_REG DDRB
949 #define EIND0_REG EIND
952 #define FNUM0_REG UDFNUML
953 #define FNUM1_REG UDFNUML
954 #define FNUM2_REG UDFNUML
955 #define FNUM3_REG UDFNUML
956 #define FNUM4_REG UDFNUML
957 #define FNUM5_REG UDFNUML
958 #define FNUM6_REG UDFNUML
959 #define FNUM7_REG UDFNUML
962 #define FNUM8_REG UDFNUMH
963 #define FNUM9_REG UDFNUMH
964 #define FNUM10_REG UDFNUMH
967 #define ADPS0_REG ADCSRA
968 #define ADPS1_REG ADCSRA
969 #define ADPS2_REG ADCSRA
970 #define ADIE_REG ADCSRA
971 #define ADIF_REG ADCSRA
972 #define ADATE_REG ADCSRA
973 #define ADSC_REG ADCSRA
974 #define ADEN_REG ADCSRA
977 #define ADTS0_REG ADCSRB
978 #define ADTS1_REG ADCSRB
979 #define ADTS2_REG ADCSRB
980 #define ADTS3_REG ADCSRB
981 #define MUX5_REG ADCSRB
982 #define ADHSM_REG ADCSRB
983 #define ACME_REG ADCSRB
986 #define PRADC_REG PRR0
987 #define PRUSART0_REG PRR0
988 #define PRSPI_REG PRR0
989 #define PRTIM1_REG PRR0
990 #define PRTIM0_REG PRR0
991 #define PRTIM2_REG PRR0
992 #define PRTWI_REG PRR0
995 #define UBRR_8_REG UBRR1H
996 #define UBRR_9_REG UBRR1H
997 #define UBRR_10_REG UBRR1H
998 #define UBRR_11_REG UBRR1H
1001 #define OCROA_0_REG OCR0A
1002 #define OCROA_1_REG OCR0A
1003 #define OCROA_2_REG OCR0A
1004 #define OCROA_3_REG OCR0A
1005 #define OCROA_4_REG OCR0A
1006 #define OCROA_5_REG OCR0A
1007 #define OCROA_6_REG OCR0A
1008 #define OCROA_7_REG OCR0A
1011 #define ACIS0_REG ACSR
1012 #define ACIS1_REG ACSR
1013 #define ACIC_REG ACSR
1014 #define ACIE_REG ACSR
1015 #define ACI_REG ACSR
1016 #define ACO_REG ACSR
1017 #define ACBG_REG ACSR
1018 #define ACD_REG ACSR
1021 #define PORTF0_REG PORTF
1022 #define PORTF1_REG PORTF
1023 #define PORTF4_REG PORTF
1024 #define PORTF5_REG PORTF
1025 #define PORTF6_REG PORTF
1026 #define PORTF7_REG PORTF
1029 #define FOC1C_REG TCCR1C
1030 #define FOC1B_REG TCCR1C
1031 #define FOC1A_REG TCCR1C
1034 #define ICR3H0_REG ICR3H
1035 #define ICR3H1_REG ICR3H
1036 #define ICR3H2_REG ICR3H
1037 #define ICR3H3_REG ICR3H
1038 #define ICR3H4_REG ICR3H
1039 #define ICR3H5_REG ICR3H
1040 #define ICR3H6_REG ICR3H
1041 #define ICR3H7_REG ICR3H
1044 #define DDE2_REG DDRE
1045 #define DDE6_REG DDRE
1048 #define UADD0_REG UDADDR
1049 #define UADD1_REG UDADDR
1050 #define UADD2_REG UDADDR
1051 #define UADD3_REG UDADDR
1052 #define UADD4_REG UDADDR
1053 #define UADD5_REG UDADDR
1054 #define UADD6_REG UDADDR
1055 #define ADDEN_REG UDADDR
1058 #define ICR3L0_REG ICR3L
1059 #define ICR3L1_REG ICR3L
1060 #define ICR3L2_REG ICR3L
1061 #define ICR3L3_REG ICR3L
1062 #define ICR3L4_REG ICR3L
1063 #define ICR3L5_REG ICR3L
1064 #define ICR3L6_REG ICR3L
1065 #define ICR3L7_REG ICR3L
1068 #define SPMEN_REG SPMCSR
1069 #define PGERS_REG SPMCSR
1070 #define PGWRT_REG SPMCSR
1071 #define BLBSET_REG SPMCSR
1072 #define RWWSRE_REG SPMCSR
1073 #define SIGRD_REG SPMCSR
1074 #define RWWSB_REG SPMCSR
1075 #define SPMIE_REG SPMCSR
1078 #define NBUSYBK0_REG UESTA0X
1079 #define NBUSYBK1_REG UESTA0X
1080 #define DTSEQ0_REG UESTA0X
1081 #define DTSEQ1_REG UESTA0X
1082 #define UNDERFI_REG UESTA0X
1083 #define OVERFI_REG UESTA0X
1084 #define CFGOK_REG UESTA0X
1087 #define PORTB0_REG PORTB
1088 #define PORTB1_REG PORTB
1089 #define PORTB2_REG PORTB
1090 #define PORTB3_REG PORTB
1091 #define PORTB4_REG PORTB
1092 #define PORTB5_REG PORTB
1093 #define PORTB6_REG PORTB
1094 #define PORTB7_REG PORTB
1097 #define ADCL0_REG ADCL
1098 #define ADCL1_REG ADCL
1099 #define ADCL2_REG ADCL
1100 #define ADCL3_REG ADCL
1101 #define ADCL4_REG ADCL
1102 #define ADCL5_REG ADCL
1103 #define ADCL6_REG ADCL
1104 #define ADCL7_REG ADCL
1107 #define ADCH0_REG ADCH
1108 #define ADCH1_REG ADCH
1109 #define ADCH2_REG ADCH
1110 #define ADCH3_REG ADCH
1111 #define ADCH4_REG ADCH
1112 #define ADCH5_REG ADCH
1113 #define ADCH6_REG ADCH
1114 #define ADCH7_REG ADCH
1117 #define OCR3BL0_REG OCR3BL
1118 #define OCR3BL1_REG OCR3BL
1119 #define OCR3BL2_REG OCR3BL
1120 #define OCR3BL3_REG OCR3BL
1121 #define OCR3BL4_REG OCR3BL
1122 #define OCR3BL5_REG OCR3BL
1123 #define OCR3BL6_REG OCR3BL
1124 #define OCR3BL7_REG OCR3BL
1127 #define OCR3BH0_REG OCR3BH
1128 #define OCR3BH1_REG OCR3BH
1129 #define OCR3BH2_REG OCR3BH
1130 #define OCR3BH3_REG OCR3BH
1131 #define OCR3BH4_REG OCR3BH
1132 #define OCR3BH5_REG OCR3BH
1133 #define OCR3BH6_REG OCR3BH
1134 #define OCR3BH7_REG OCR3BH
1137 #define TOIE3_REG TIMSK3
1138 #define OCIE3A_REG TIMSK3
1139 #define OCIE3B_REG TIMSK3
1140 #define OCIE3C_REG TIMSK3
1141 #define ICIE3_REG TIMSK3
1144 #define TOIE0_REG TIMSK0
1145 #define OCIE0A_REG TIMSK0
1146 #define OCIE0B_REG TIMSK0
1149 #define TOIE1_REG TIMSK1
1150 #define OCIE1A_REG TIMSK1
1151 #define OCIE1B_REG TIMSK1
1152 #define OCIE1C_REG TIMSK1
1153 #define ICIE1_REG TIMSK1
1156 #define EXTON_REG CLKSTA
1157 #define RCON_REG CLKSTA
1160 #define TOIE4_REG TIMSK4
1161 #define OCIE4B_REG TIMSK4
1162 #define OCIE4A_REG TIMSK4
1163 #define OCIE4D_REG TIMSK4
1166 #define CS40_REG TCCR4B
1167 #define CS41_REG TCCR4B
1168 #define CS42_REG TCCR4B
1169 #define CS43_REG TCCR4B
1170 #define DTPS40_REG TCCR4B
1171 #define DTPS41_REG TCCR4B
1172 #define PSR4_REG TCCR4B
1173 #define PWM4X_REG TCCR4B
1176 #define PWM4D_REG TCCR4C
1177 #define FOC4D_REG TCCR4C
1178 #define COM4D0_REG TCCR4C
1179 #define COM4D1_REG TCCR4C
1180 #define COM4B0S_REG TCCR4C
1181 #define COM4B1S_REG TCCR4C
1182 #define COM4A0S_REG TCCR4C
1183 #define COM4A1S_REG TCCR4C
1186 #define PLOCK_REG PLLCSR
1187 #define PLLE_REG PLLCSR
1188 #define PINDIV_REG PLLCSR
1191 #define PWM4B_REG TCCR4A
1192 #define PWM4A_REG TCCR4A
1193 #define FOC4B_REG TCCR4A
1194 #define FOC4A_REG TCCR4A
1195 #define COM4B0_REG TCCR4A
1196 #define COM4B1_REG TCCR4A
1197 #define COM4A0_REG TCCR4A
1198 #define COM4A1_REG TCCR4A
1201 #define PCINT0_REG PCMSK0
1202 #define PCINT1_REG PCMSK0
1203 #define PCINT2_REG PCMSK0
1204 #define PCINT3_REG PCMSK0
1205 #define PCINT4_REG PCMSK0
1206 #define PCINT5_REG PCMSK0
1207 #define PCINT6_REG PCMSK0
1208 #define PCINT7_REG PCMSK0
1211 #define WGM40_REG TCCR4D
1212 #define WGM41_REG TCCR4D
1213 #define FPF4_REG TCCR4D
1214 #define FPAC4_REG TCCR4D
1215 #define FPES4_REG TCCR4D
1216 #define FPNC4_REG TCCR4D
1217 #define FPEN4_REG TCCR4D
1218 #define FPIE4_REG TCCR4D
1221 #define OC4OE0_REG TCCR4E
1222 #define OC4OE1_REG TCCR4E
1223 #define OC4OE2_REG TCCR4E
1224 #define OC4OE3_REG TCCR4E
1225 #define OC4OE4_REG TCCR4E
1226 #define OC4OE5_REG TCCR4E
1227 #define ENHC4_REG TCCR4E
1228 #define TLOCK4_REG TCCR4E
1231 #define PINC6_REG PINC
1232 #define PINC7_REG PINC
1235 #define PINB0_REG PINB
1236 #define PINB1_REG PINB
1237 #define PINB2_REG PINB
1238 #define PINB3_REG PINB
1239 #define PINB4_REG PINB
1240 #define PINB5_REG PINB
1241 #define PINB6_REG PINB
1242 #define PINB7_REG PINB
1245 #define INTF0_REG EIFR
1246 #define INTF1_REG EIFR
1247 #define INTF2_REG EIFR
1248 #define INTF3_REG EIFR
1249 #define INTF4_REG EIFR
1250 #define INTF5_REG EIFR
1251 #define INTF6_REG EIFR
1252 #define INTF7_REG EIFR
1255 #define PINF0_REG PINF
1256 #define PINF1_REG PINF
1257 #define PINF4_REG PINF
1258 #define PINF5_REG PINF
1259 #define PINF6_REG PINF
1260 #define PINF7_REG PINF
1263 #define PINE2_REG PINE
1264 #define PINE6_REG PINE
1267 #define PIND0_REG PIND
1268 #define PIND1_REG PIND
1269 #define PIND2_REG PIND
1270 #define PIND3_REG PIND
1271 #define PIND4_REG PIND
1272 #define PIND5_REG PIND
1273 #define PIND6_REG PIND
1274 #define PIND7_REG PIND
1277 #define OCR1AH0_REG OCR1AH
1278 #define OCR1AH1_REG OCR1AH
1279 #define OCR1AH2_REG OCR1AH
1280 #define OCR1AH3_REG OCR1AH
1281 #define OCR1AH4_REG OCR1AH
1282 #define OCR1AH5_REG OCR1AH
1283 #define OCR1AH6_REG OCR1AH
1284 #define OCR1AH7_REG OCR1AH
1287 #define OCR1AL0_REG OCR1AL
1288 #define OCR1AL1_REG OCR1AL
1289 #define OCR1AL2_REG OCR1AL
1290 #define OCR1AL3_REG OCR1AL
1291 #define OCR1AL4_REG OCR1AL
1292 #define OCR1AL5_REG OCR1AL
1293 #define OCR1AL6_REG OCR1AL
1294 #define OCR1AL7_REG OCR1AL
1297 #define TOV0_REG TIFR0
1298 #define OCF0A_REG TIFR0
1299 #define OCF0B_REG TIFR0
1302 #define PRUSART1_REG PRR1
1303 #define PRTIM3_REG PRR1
1304 #define PRUSB_REG PRR1
1307 #define DT4L0_REG DT4
1308 #define DT4L1_REG DT4
1309 #define DT4L2_REG DT4
1310 #define DT4L3_REG DT4
1311 #define DT4L4_REG DT4
1312 #define DT4L5_REG DT4
1313 #define DT4L6_REG DT4
1314 #define DT4L7_REG DT4