2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
85 /* available timers */
86 #define TIMER0_AVAILABLE
87 #define TIMER1_AVAILABLE
88 #define TIMER1A_AVAILABLE
89 #define TIMER1B_AVAILABLE
90 #define TIMER2_AVAILABLE
92 /* overflow interrupt number */
93 #define SIG_OVERFLOW0_NUM 0
94 #define SIG_OVERFLOW1_NUM 1
95 #define SIG_OVERFLOW2_NUM 2
96 #define SIG_OVERFLOW_TOTAL_NUM 3
98 /* output compare interrupt number */
99 #define SIG_OUTPUT_COMPARE1A_NUM 0
100 #define SIG_OUTPUT_COMPARE1B_NUM 1
101 #define SIG_OUTPUT_COMPARE2_NUM 2
102 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
108 #define PWM_TOTAL_NUM 3
110 /* input capture interrupt number */
111 #define SIG_INPUT_CAPTURE1_NUM 0
112 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
116 #define WDP0_REG WDTCR
117 #define WDP1_REG WDTCR
118 #define WDP2_REG WDTCR
119 #define WDE_REG WDTCR
120 #define WDCE_REG WDTCR
123 #define ICR1H0_REG ICR1H
124 #define ICR1H1_REG ICR1H
125 #define ICR1H2_REG ICR1H
126 #define ICR1H3_REG ICR1H
127 #define ICR1H4_REG ICR1H
128 #define ICR1H5_REG ICR1H
129 #define ICR1H6_REG ICR1H
130 #define ICR1H7_REG ICR1H
133 #define MUX0_REG ADMUX
134 #define MUX1_REG ADMUX
135 #define MUX2_REG ADMUX
136 #define MUX3_REG ADMUX
137 #define ADLAR_REG ADMUX
138 #define REFS0_REG ADMUX
139 #define REFS1_REG ADMUX
142 #define CS00_REG TCCR0
143 #define CS01_REG TCCR0
144 #define CS02_REG TCCR0
157 #define DDB0_REG DDRB
158 #define DDB1_REG DDRB
159 #define DDB2_REG DDRB
160 #define DDB3_REG DDRB
161 #define DDB4_REG DDRB
162 #define DDB5_REG DDRB
163 #define DDB6_REG DDRB
164 #define DDB7_REG DDRB
167 #define IVCE_REG GICR
168 #define IVSEL_REG GICR
169 #define INT0_REG GICR
170 #define INT1_REG GICR
173 #define SPI2X_REG SPSR
174 #define WCOL_REG SPSR
175 #define SPIF_REG SPSR
178 #define TWD0_REG TWDR
179 #define TWD1_REG TWDR
180 #define TWD2_REG TWDR
181 #define TWD3_REG TWDR
182 #define TWD4_REG TWDR
183 #define TWD5_REG TWDR
184 #define TWD6_REG TWDR
185 #define TWD7_REG TWDR
188 #define EEDR0_REG EEDR
189 #define EEDR1_REG EEDR
190 #define EEDR2_REG EEDR
191 #define EEDR3_REG EEDR
192 #define EEDR4_REG EEDR
193 #define EEDR5_REG EEDR
194 #define EEDR6_REG EEDR
195 #define EEDR7_REG EEDR
198 #define DDC0_REG DDRC
199 #define DDC1_REG DDRC
200 #define DDC2_REG DDRC
201 #define DDC3_REG DDRC
202 #define DDC4_REG DDRC
203 #define DDC5_REG DDRC
204 #define DDC6_REG DDRC
207 #define PIND0_REG PIND
208 #define PIND1_REG PIND
209 #define PIND2_REG PIND
210 #define PIND3_REG PIND
211 #define PIND4_REG PIND
212 #define PIND5_REG PIND
213 #define PIND6_REG PIND
214 #define PIND7_REG PIND
217 #define WGM10_REG TCCR1A
218 #define WGM11_REG TCCR1A
219 #define FOC1B_REG TCCR1A
220 #define FOC1A_REG TCCR1A
221 #define COM1B0_REG TCCR1A
222 #define COM1B1_REG TCCR1A
223 #define COM1A0_REG TCCR1A
224 #define COM1A1_REG TCCR1A
227 #define DDD0_REG DDRD
228 #define DDD1_REG DDRD
229 #define DDD2_REG DDRD
230 #define DDD3_REG DDRD
231 #define DDD4_REG DDRD
232 #define DDD5_REG DDRD
233 #define DDD6_REG DDRD
234 #define DDD7_REG DDRD
237 #define CS10_REG TCCR1B
238 #define CS11_REG TCCR1B
239 #define CS12_REG TCCR1B
240 #define WGM12_REG TCCR1B
241 #define WGM13_REG TCCR1B
242 #define ICES1_REG TCCR1B
243 #define ICNC1_REG TCCR1B
246 #define INTF0_REG GIFR
247 #define INTF1_REG GIFR
250 #define TOIE0_REG TIMSK
251 #define TOIE1_REG TIMSK
252 #define OCIE1B_REG TIMSK
253 #define OCIE1A_REG TIMSK
254 #define TICIE1_REG TIMSK
255 #define TOIE2_REG TIMSK
256 #define OCIE2_REG TIMSK
259 #define ADPS0_REG ADCSRA
260 #define ADPS1_REG ADCSRA
261 #define ADPS2_REG ADCSRA
262 #define ADIE_REG ADCSRA
263 #define ADIF_REG ADCSRA
264 #define ADFR_REG ADCSRA
265 #define ADSC_REG ADCSRA
266 #define ADEN_REG ADCSRA
269 #define MPCM_REG UCSRA
270 #define U2X_REG UCSRA
271 #define UPE_REG UCSRA
272 #define DOR_REG UCSRA
274 #define UDRE_REG UCSRA
275 #define TXC_REG UCSRA
276 #define RXC_REG UCSRA
279 #define SPDR0_REG SPDR
280 #define SPDR1_REG SPDR
281 #define SPDR2_REG SPDR
282 #define SPDR3_REG SPDR
283 #define SPDR4_REG SPDR
284 #define SPDR5_REG SPDR
285 #define SPDR6_REG SPDR
286 #define SPDR7_REG SPDR
289 #define ACME_REG SFIOR
290 #define PSR2_REG SFIOR
291 #define PSR10_REG SFIOR
292 #define PUD_REG SFIOR
293 #define ADHSM_REG SFIOR
296 #define ACIS0_REG ACSR
297 #define ACIS1_REG ACSR
298 #define ACIC_REG ACSR
299 #define ACIE_REG ACSR
302 #define ACBG_REG ACSR
311 #define OCR1BL0_REG OCR1BL
312 #define OCR1BL1_REG OCR1BL
313 #define OCR1BL2_REG OCR1BL
314 #define OCR1BL3_REG OCR1BL
315 #define OCR1BL4_REG OCR1BL
316 #define OCR1BL5_REG OCR1BL
317 #define OCR1BL6_REG OCR1BL
318 #define OCR1BL7_REG OCR1BL
321 #define TXB8_REG UCSRB
322 #define RXB8_REG UCSRB
323 #define UCSZ2_REG UCSRB
324 #define TXEN_REG UCSRB
325 #define RXEN_REG UCSRB
326 #define UDRIE_REG UCSRB
327 #define TXCIE_REG UCSRB
328 #define RXCIE_REG UCSRB
331 #define UCPOL_REG UCSRC
332 #define UCSZ0_REG UCSRC
333 #define UCSZ1_REG UCSRC
334 #define USBS_REG UCSRC
335 #define UPM0_REG UCSRC
336 #define UPM1_REG UCSRC
337 #define UMSEL_REG UCSRC
338 #define URSEL_REG UCSRC
351 #define OCR1BH0_REG OCR1BH
352 #define OCR1BH1_REG OCR1BH
353 #define OCR1BH2_REG OCR1BH
354 #define OCR1BH3_REG OCR1BH
355 #define OCR1BH4_REG OCR1BH
356 #define OCR1BH5_REG OCR1BH
357 #define OCR1BH6_REG OCR1BH
358 #define OCR1BH7_REG OCR1BH
371 #define SPMEN_REG SPMCR
372 #define PGERS_REG SPMCR
373 #define PGWRT_REG SPMCR
374 #define BLBSET_REG SPMCR
375 #define RWWSRE_REG SPMCR
376 #define RWWSB_REG SPMCR
377 #define SPMIE_REG SPMCR
380 #define UBRR8_REG UBRRH
381 #define UBRR9_REG UBRRH
382 #define UBRR10_REG UBRRH
383 #define UBRR11_REG UBRRH
386 #define TWBR0_REG TWBR
387 #define TWBR1_REG TWBR
388 #define TWBR2_REG TWBR
389 #define TWBR3_REG TWBR
390 #define TWBR4_REG TWBR
391 #define TWBR5_REG TWBR
392 #define TWBR6_REG TWBR
393 #define TWBR7_REG TWBR
396 #define ADCL0_REG ADCL
397 #define ADCL1_REG ADCL
398 #define ADCL2_REG ADCL
399 #define ADCL3_REG ADCL
400 #define ADCL4_REG ADCL
401 #define ADCL5_REG ADCL
402 #define ADCL6_REG ADCL
403 #define ADCL7_REG ADCL
406 #define UBRR0_REG UBRRL
407 #define UBRR1_REG UBRRL
408 #define UBRR2_REG UBRRL
409 #define UBRR3_REG UBRRL
410 #define UBRR4_REG UBRRL
411 #define UBRR5_REG UBRRL
412 #define UBRR6_REG UBRRL
413 #define UBRR7_REG UBRRL
416 #define EERE_REG EECR
417 #define EEWE_REG EECR
418 #define EEMWE_REG EECR
419 #define EERIE_REG EECR
422 #define CAL0_REG OSCCAL
423 #define CAL1_REG OSCCAL
424 #define CAL2_REG OSCCAL
425 #define CAL3_REG OSCCAL
426 #define CAL4_REG OSCCAL
427 #define CAL5_REG OSCCAL
428 #define CAL6_REG OSCCAL
429 #define CAL7_REG OSCCAL
432 #define TCNT1L0_REG TCNT1L
433 #define TCNT1L1_REG TCNT1L
434 #define TCNT1L2_REG TCNT1L
435 #define TCNT1L3_REG TCNT1L
436 #define TCNT1L4_REG TCNT1L
437 #define TCNT1L5_REG TCNT1L
438 #define TCNT1L6_REG TCNT1L
439 #define TCNT1L7_REG TCNT1L
442 #define PORTB0_REG PORTB
443 #define PORTB1_REG PORTB
444 #define PORTB2_REG PORTB
445 #define PORTB3_REG PORTB
446 #define PORTB4_REG PORTB
447 #define PORTB5_REG PORTB
448 #define PORTB6_REG PORTB
449 #define PORTB7_REG PORTB
452 #define PORTD0_REG PORTD
453 #define PORTD1_REG PORTD
454 #define PORTD2_REG PORTD
455 #define PORTD3_REG PORTD
456 #define PORTD4_REG PORTD
457 #define PORTD5_REG PORTD
458 #define PORTD6_REG PORTD
459 #define PORTD7_REG PORTD
462 #define TCNT1H0_REG TCNT1H
463 #define TCNT1H1_REG TCNT1H
464 #define TCNT1H2_REG TCNT1H
465 #define TCNT1H3_REG TCNT1H
466 #define TCNT1H4_REG TCNT1H
467 #define TCNT1H5_REG TCNT1H
468 #define TCNT1H6_REG TCNT1H
469 #define TCNT1H7_REG TCNT1H
472 #define PORTC0_REG PORTC
473 #define PORTC1_REG PORTC
474 #define PORTC2_REG PORTC
475 #define PORTC3_REG PORTC
476 #define PORTC4_REG PORTC
477 #define PORTC5_REG PORTC
478 #define PORTC6_REG PORTC
481 #define ADCH0_REG ADCH
482 #define ADCH1_REG ADCH
483 #define ADCH2_REG ADCH
484 #define ADCH3_REG ADCH
485 #define ADCH4_REG ADCH
486 #define ADCH5_REG ADCH
487 #define ADCH6_REG ADCH
488 #define ADCH7_REG ADCH
491 #define TWIE_REG TWCR
492 #define TWEN_REG TWCR
493 #define TWWC_REG TWCR
494 #define TWSTO_REG TWCR
495 #define TWSTA_REG TWCR
496 #define TWEA_REG TWCR
497 #define TWINT_REG TWCR
500 #define TCNT00_REG TCNT0
501 #define TCNT01_REG TCNT0
502 #define TCNT02_REG TCNT0
503 #define TCNT03_REG TCNT0
504 #define TCNT04_REG TCNT0
505 #define TCNT05_REG TCNT0
506 #define TCNT06_REG TCNT0
507 #define TCNT07_REG TCNT0
510 #define PORF_REG MCUCSR
511 #define EXTRF_REG MCUCSR
512 #define BORF_REG MCUCSR
513 #define WDRF_REG MCUCSR
516 #define TWGCE_REG TWAR
517 #define TWA0_REG TWAR
518 #define TWA1_REG TWAR
519 #define TWA2_REG TWAR
520 #define TWA3_REG TWAR
521 #define TWA4_REG TWAR
522 #define TWA5_REG TWAR
523 #define TWA6_REG TWAR
526 #define CS20_REG TCCR2
527 #define CS21_REG TCCR2
528 #define CS22_REG TCCR2
529 #define WGM21_REG TCCR2
530 #define COM20_REG TCCR2
531 #define COM21_REG TCCR2
532 #define WGM20_REG TCCR2
533 #define FOC2_REG TCCR2
536 #define TOV0_REG TIFR
537 #define TOV1_REG TIFR
538 #define OCF1B_REG TIFR
539 #define OCF1A_REG TIFR
540 #define ICF1_REG TIFR
541 #define TOV2_REG TIFR
542 #define OCF2_REG TIFR
545 #define EEAR8_REG EEARH
548 #define TCNT2_0_REG TCNT2
549 #define TCNT2_1_REG TCNT2
550 #define TCNT2_2_REG TCNT2
551 #define TCNT2_3_REG TCNT2
552 #define TCNT2_4_REG TCNT2
553 #define TCNT2_5_REG TCNT2
554 #define TCNT2_6_REG TCNT2
555 #define TCNT2_7_REG TCNT2
558 #define EEAR0_REG EEARL
559 #define EEAR1_REG EEARL
560 #define EEAR2_REG EEARL
561 #define EEAR3_REG EEARL
562 #define EEAR4_REG EEARL
563 #define EEAR5_REG EEARL
564 #define EEAR6_REG EEARL
565 #define EEAR7_REG EEARL
568 #define TWPS0_REG TWSR
569 #define TWPS1_REG TWSR
570 #define TWS3_REG TWSR
571 #define TWS4_REG TWSR
572 #define TWS5_REG TWSR
573 #define TWS6_REG TWSR
574 #define TWS7_REG TWSR
577 #define PINC0_REG PINC
578 #define PINC1_REG PINC
579 #define PINC2_REG PINC
580 #define PINC3_REG PINC
581 #define PINC4_REG PINC
582 #define PINC5_REG PINC
583 #define PINC6_REG PINC
586 #define PINB0_REG PINB
587 #define PINB1_REG PINB
588 #define PINB2_REG PINB
589 #define PINB3_REG PINB
590 #define PINB4_REG PINB
591 #define PINB5_REG PINB
592 #define PINB6_REG PINB
593 #define PINB7_REG PINB
596 #define ISC00_REG MCUCR
597 #define ISC01_REG MCUCR
598 #define ISC10_REG MCUCR
599 #define ISC11_REG MCUCR
600 #define SM0_REG MCUCR
601 #define SM1_REG MCUCR
602 #define SM2_REG MCUCR
606 #define OCR1AH0_REG OCR1AH
607 #define OCR1AH1_REG OCR1AH
608 #define OCR1AH2_REG OCR1AH
609 #define OCR1AH3_REG OCR1AH
610 #define OCR1AH4_REG OCR1AH
611 #define OCR1AH5_REG OCR1AH
612 #define OCR1AH6_REG OCR1AH
613 #define OCR1AH7_REG OCR1AH
616 #define OCR1AL0_REG OCR1AL
617 #define OCR1AL1_REG OCR1AL
618 #define OCR1AL2_REG OCR1AL
619 #define OCR1AL3_REG OCR1AL
620 #define OCR1AL4_REG OCR1AL
621 #define OCR1AL5_REG OCR1AL
622 #define OCR1AL6_REG OCR1AL
623 #define OCR1AL7_REG OCR1AL
626 #define SPR0_REG SPCR
627 #define SPR1_REG SPCR
628 #define CPHA_REG SPCR
629 #define CPOL_REG SPCR
630 #define MSTR_REG SPCR
631 #define DORD_REG SPCR
633 #define SPIE_REG SPCR
636 #define TCR2UB_REG ASSR
637 #define OCR2UB_REG ASSR
638 #define TCN2UB_REG ASSR
642 #define OCR2_0_REG OCR2
643 #define OCR2_1_REG OCR2
644 #define OCR2_2_REG OCR2
645 #define OCR2_3_REG OCR2
646 #define OCR2_4_REG OCR2
647 #define OCR2_5_REG OCR2
648 #define OCR2_6_REG OCR2
649 #define OCR2_7_REG OCR2
652 #define ICR1L0_REG ICR1L
653 #define ICR1L1_REG ICR1L
654 #define ICR1L2_REG ICR1L
655 #define ICR1L3_REG ICR1L
656 #define ICR1L4_REG ICR1L
657 #define ICR1L5_REG ICR1L
658 #define ICR1L6_REG ICR1L
659 #define ICR1L7_REG ICR1L
662 #define ICP_PORT PORTB
665 #define OC1A_PORT PORTB
668 #define SS_PORT PORTB
670 #define OC1B_PORT PORTB
673 #define MOSI_PORT PORTB
675 #define OC2_PORT PORTB
678 #define MISO_PORT PORTB
681 #define SCK_PORT PORTB
684 #define XTAL1_PORT PORTB
686 #define TOSC1_PORT PORTB
689 #define XTAL2_PORT PORTB
691 #define TOSC2_PORT PORTB
694 #define ADC0_PORT PORTC
697 #define ADC1_PORT PORTC
700 #define ADC2_PORT PORTC
703 #define ADC3_PORT PORTC
706 #define ADC4_PORT PORTC
708 #define SDA_PORT PORTC
711 #define ADC5_PORT PORTC
713 #define SCL_PORT PORTC
716 #define RESET_PORT PORTC
719 #define RXD_PORT PORTD
722 #define TXD_PORT PORTD
725 #define INT0_PORT PORTD
728 #define IN1_PORT PORTD
731 #define XCK_PORT PORTD
733 #define T0_PORT PORTD
736 #define T1_PORT PORTD
739 #define AIN0_PORT PORTD
742 #define AIN1_PORT PORTD