2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
47 /* available timers */
49 /* overflow interrupt number */
50 #define SIG_OVERFLOW_TOTAL_NUM 0
52 /* output compare interrupt number */
53 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
56 #define PWM_TOTAL_NUM 0
58 /* input capture interrupt number */
59 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
63 #define CLKPS0_REG CLKPSR
64 #define CLKPS1_REG CLKPSR
65 #define CLKPS2_REG CLKPSR
66 #define CLKPS3_REG CLKPSR
69 #define VLM0_REG VLMCSR
70 #define VLM1_REG VLMCSR
71 #define VLMIE_REG VLMCSR
72 #define VLMF_REG VLMCSR
75 #define MUX0_REG ADMUX
76 #define MUX1_REG ADMUX
79 #define TCNT0_8_REG TCNT0H
80 #define TCNT0_9_REG TCNT0H
81 #define TCNT0_10_REG TCNT0H
82 #define TCNT0_11_REG TCNT0H
83 #define TCNT0_12_REG TCNT0H
84 #define TCNT0_13_REG TCNT0H
85 #define TCNT0_14_REG TCNT0H
86 #define TCNT0_15_REG TCNT0H
89 #define BBMB_REG PORTCR
102 #define TCNT0_0_REG TCNT0L
103 #define TCNT0_1_REG TCNT0L
104 #define TCNT0_2_REG TCNT0L
105 #define TCNT0_3_REG TCNT0L
106 #define TCNT0_4_REG TCNT0L
107 #define TCNT0_5_REG TCNT0L
108 #define TCNT0_6_REG TCNT0L
109 #define TCNT0_7_REG TCNT0L
112 #define WDP0_REG WDTCSR
113 #define WDP1_REG WDTCSR
114 #define WDP2_REG WDTCSR
115 #define WDE_REG WDTCSR
116 #define WDP3_REG WDTCSR
117 #define WDIE_REG WDTCSR
118 #define WDIF_REG WDTCSR
121 #define DDB0_REG DDRB
122 #define DDB1_REG DDRB
123 #define DDB2_REG DDRB
124 #define DDB3_REG DDRB
127 #define ACIS0_REG ACSR
128 #define ACIS1_REG ACSR
129 #define ACIC_REG ACSR
130 #define ACIE_REG ACSR
136 #define PSR_REG GTCCR
137 #define TSM_REG GTCCR
140 #define CAL0_REG OSCCAL
141 #define CAL1_REG OSCCAL
142 #define CAL2_REG OSCCAL
143 #define CAL3_REG OSCCAL
144 #define CAL4_REG OSCCAL
145 #define CAL5_REG OSCCAL
146 #define CAL6_REG OSCCAL
147 #define CAL7_REG OSCCAL
150 #define ADPS0_REG ADCSRA
151 #define ADPS1_REG ADCSRA
152 #define ADPS2_REG ADCSRA
153 #define ADIE_REG ADCSRA
154 #define ADIF_REG ADCSRA
155 #define ADATE_REG ADCSRA
156 #define ADSC_REG ADCSRA
157 #define ADEN_REG ADCSRA
160 #define ADTS0_REG ADCSRB
161 #define ADTS1_REG ADCSRB
162 #define ADTS2_REG ADCSRB
165 #define PORF_REG RSTFLR
166 #define EXTRF_REG RSTFLR
167 #define WDRF_REG RSTFLR
190 #define PCIF0_REG PCIFR
193 #define PRTIM0_REG PRR
194 #define PRADC_REG PRR
197 #define OCR0B0_REG OCR0BL
198 #define OCR0B1_REG OCR0BL
199 #define OCR0B2_REG OCR0BL
200 #define OCR0B3_REG OCR0BL
201 #define OCR0B4_REG OCR0BL
202 #define OCR0B5_REG OCR0BL
203 #define OCR0B6_REG OCR0BL
204 #define OCR0B7_REG OCR0BL
207 #define PCINT0_REG PCMSK
208 #define PCINT1_REG PCMSK
209 #define PCINT2_REG PCMSK
210 #define PCINT3_REG PCMSK
213 #define ADC0_REG ADCL
214 #define ADC1_REG ADCL
215 #define ADC2_REG ADCL
216 #define ADC3_REG ADCL
217 #define ADC4_REG ADCL
218 #define ADC5_REG ADCL
219 #define ADC6_REG ADCL
220 #define ADC7_REG ADCL
229 #define PORTB0_REG PORTB
230 #define PORTB1_REG PORTB
231 #define PORTB2_REG PORTB
232 #define PORTB3_REG PORTB
235 #define PCIE0_REG PCICR
238 #define NVMBSY_REG NVMCSR
241 #define INT0_REG EIMSK
244 #define TOIE0_REG TIMSK0
245 #define OCIE0A_REG TIMSK0
246 #define OCIE0B_REG TIMSK0
247 #define ICIE0_REG TIMSK0
260 #define CS00_REG TCCR0B
261 #define CS01_REG TCCR0B
262 #define CS02_REG TCCR0B
263 #define WGM02_REG TCCR0B
264 #define WGM03_REG TCCR0B
265 #define ICES0_REG TCCR0B
266 #define ICNC0_REG TCCR0B
269 #define FOC0B_REG TCCR0C
270 #define FOC0A_REG TCCR0C
273 #define WGM00_REG TCCR0A
274 #define WGM01_REG TCCR0A
275 #define COM0B0_REG TCCR0A
276 #define COM0B1_REG TCCR0A
277 #define COM0A0_REG TCCR0A
278 #define COM0A1_REG TCCR0A
281 #define CLKMS0_REG CLKMSR
282 #define CLKMS1_REG CLKMSR
285 #define ISC00_REG EICRA
286 #define ISC01_REG EICRA
289 #define PINB0_REG PINB
290 #define PINB1_REG PINB
291 #define PINB2_REG PINB
292 #define PINB3_REG PINB
295 #define INTF0_REG EIFR
298 #define ADC0D_REG DIDR0
299 #define ADC1D_REG DIDR0
300 #define ADC2D_REG DIDR0
301 #define ADC3D_REG DIDR0
302 #define AIN0D_REG DIDR0
303 #define AIN1D_REG DIDR0
306 #define OCR0A0_REG OCR0AL
307 #define OCR0A1_REG OCR0AL
308 #define OCR0A2_REG OCR0AL
309 #define OCR0A3_REG OCR0AL
310 #define OCR0A4_REG OCR0AL
311 #define OCR0A5_REG OCR0AL
312 #define OCR0A6_REG OCR0AL
313 #define OCR0A7_REG OCR0AL
316 #define NVMCMD0_REG NVMCMD
317 #define NVMCMD1_REG NVMCMD
318 #define NVMCMD2_REG NVMCMD
319 #define NVMCMD3_REG NVMCMD
320 #define NVMCMD4_REG NVMCMD
321 #define NVMCMD5_REG NVMCMD
324 #define ICR0_0_REG ICR0L
325 #define ICR0_1_REG ICR0L
326 #define ICR0_2_REG ICR0L
327 #define ICR0_3_REG ICR0L
328 #define ICR0_4_REG ICR0L
329 #define ICR0_5_REG ICR0L
330 #define ICR0_6_REG ICR0L
331 #define ICR0_7_REG ICR0L
334 #define OCR0A8_REG OCR0AH
335 #define OCR0A9_REG OCR0AH
336 #define OCR0A10_REG OCR0AH
337 #define OCR0A11_REG OCR0AH
338 #define OCR0A12_REG OCR0AH
339 #define OCR0A13_REG OCR0AH
340 #define OCR0A14_REG OCR0AH
341 #define OCR0A15_REG OCR0AH
344 #define ICR0_8_REG ICR0H
345 #define ICR0_9_REG ICR0H
346 #define ICR0_10_REG ICR0H
347 #define ICR0_11_REG ICR0H
348 #define ICR0_12_REG ICR0H
349 #define ICR0_13_REG ICR0H
350 #define ICR0_14_REG ICR0H
351 #define ICR0_15_REG ICR0H
354 #define PUEB0_REG PUEB
355 #define PUEB1_REG PUEB
356 #define PUEB2_REG PUEB
357 #define PUEB3_REG PUEB
360 #define OCR0B8_REG OCR0BH
361 #define OCR0B9_REG OCR0BH
362 #define OCR0B10_REG OCR0BH
363 #define OCR0B11_REG OCR0BH
364 #define OCR0B12_REG OCR0BH
365 #define OCR0B13_REG OCR0BH
366 #define OCR0B14_REG OCR0BH
367 #define OCR0B15_REG OCR0BH
370 #define TOV0_REG TIFR0
371 #define OCF0A_REG TIFR0
372 #define OCF0B_REG TIFR0
373 #define ICF0_REG TIFR0