2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
47 /* available timers */
48 #define TIMER0_AVAILABLE
50 /* overflow interrupt number */
51 #define SIG_OVERFLOW0_NUM 0
52 #define SIG_OVERFLOW_TOTAL_NUM 1
54 /* output compare interrupt number */
55 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
58 #define PWM_TOTAL_NUM 0
60 /* input capture interrupt number */
61 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
66 #define INTF0_REG GIFR
69 #define TOIE0_REG TIMSK
72 #define WDP0_REG WDTCR
73 #define WDP1_REG WDTCR
74 #define WDP2_REG WDTCR
76 #define WDTOE_REG WDTCR
79 #define PCIE_REG GIMSK
80 #define INT0_REG GIMSK
83 #define PINB0_REG PINB
84 #define PINB1_REG PINB
85 #define PINB2_REG PINB
86 #define PINB3_REG PINB
87 #define PINB4_REG PINB
88 #define PINB5_REG PINB
91 #define PORTB0_REG PORTB
92 #define PORTB1_REG PORTB
93 #define PORTB2_REG PORTB
94 #define PORTB3_REG PORTB
95 #define PORTB4_REG PORTB
98 #define CS00_REG TCCR0
99 #define CS01_REG TCCR0
100 #define CS02_REG TCCR0
103 #define ISC00_REG MCUCR
104 #define ISC01_REG MCUCR
109 #define TCNT00_REG TCNT0
110 #define TCNT01_REG TCNT0
111 #define TCNT02_REG TCNT0
112 #define TCNT03_REG TCNT0
113 #define TCNT04_REG TCNT0
114 #define TCNT05_REG TCNT0
115 #define TCNT06_REG TCNT0
116 #define TCNT07_REG TCNT0
119 #define ACIS0_REG ACSR
120 #define ACIS1_REG ACSR
121 #define ACIE_REG ACSR
127 #define DDB0_REG DDRB
128 #define DDB1_REG DDRB
129 #define DDB2_REG DDRB
130 #define DDB3_REG DDRB
131 #define DDB4_REG DDRB
144 #define TOV0_REG TIFR
147 #define PORF_REG MCUSR
148 #define EXTRF_REG MCUSR
151 #define AIN0_PORT PORTB
154 #define INT0_PORT PORTB
156 #define AIN1_PORT PORTB
159 #define T0_PORT PORTB
162 #define XTAL1_PORT PORTB
165 #define XTAL2_PORT PORTB
168 #define RESET_PORT PORTB