1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
6 #include <rte_bus_pci.h>
7 #include <rte_ethdev.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_malloc.h>
10 #include <rte_ethdev_pci.h>
12 #include "ionic_logs.h"
14 #include "ionic_dev.h"
15 #include "ionic_mac_api.h"
16 #include "ionic_lif.h"
17 #include "ionic_ethdev.h"
18 #include "ionic_rxtx.h"
20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev);
22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev,
23 struct rte_eth_dev_info *dev_info);
24 static int ionic_dev_configure(struct rte_eth_dev *dev);
25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
26 static int ionic_dev_start(struct rte_eth_dev *dev);
27 static void ionic_dev_stop(struct rte_eth_dev *dev);
28 static int ionic_dev_close(struct rte_eth_dev *dev);
29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev);
30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev);
31 static int ionic_dev_link_update(struct rte_eth_dev *eth_dev,
32 int wait_to_complete);
33 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
34 struct rte_eth_fc_conf *fc_conf);
35 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
36 struct rte_eth_fc_conf *fc_conf);
37 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
38 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
40 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
41 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
42 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
43 struct rte_eth_rss_conf *rss_conf);
44 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
45 struct rte_eth_rss_conf *rss_conf);
46 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
47 struct rte_eth_stats *stats);
48 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev);
49 static int ionic_dev_xstats_get(struct rte_eth_dev *dev,
50 struct rte_eth_xstat *xstats, unsigned int n);
51 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev,
52 const uint64_t *ids, uint64_t *values, unsigned int n);
53 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev);
54 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev,
55 struct rte_eth_xstat_name *xstats_names, unsigned int size);
56 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
57 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
59 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
60 char *fw_version, size_t fw_size);
62 static const struct rte_pci_id pci_id_ionic_map[] = {
63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) },
64 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) },
65 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) },
66 { .vendor_id = 0, /* sentinel */ },
69 static const struct rte_eth_desc_lim rx_desc_lim = {
70 .nb_max = IONIC_MAX_RING_DESC,
71 .nb_min = IONIC_MIN_RING_DESC,
75 static const struct rte_eth_desc_lim tx_desc_lim = {
76 .nb_max = IONIC_MAX_RING_DESC,
77 .nb_min = IONIC_MIN_RING_DESC,
79 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS,
80 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS,
83 static const struct eth_dev_ops ionic_eth_dev_ops = {
84 .dev_infos_get = ionic_dev_info_get,
85 .dev_configure = ionic_dev_configure,
86 .mtu_set = ionic_dev_mtu_set,
87 .dev_start = ionic_dev_start,
88 .dev_stop = ionic_dev_stop,
89 .dev_close = ionic_dev_close,
90 .link_update = ionic_dev_link_update,
91 .dev_set_link_up = ionic_dev_set_link_up,
92 .dev_set_link_down = ionic_dev_set_link_down,
93 .mac_addr_add = ionic_dev_add_mac,
94 .mac_addr_remove = ionic_dev_remove_mac,
95 .mac_addr_set = ionic_dev_set_mac,
96 .vlan_filter_set = ionic_dev_vlan_filter_set,
97 .promiscuous_enable = ionic_dev_promiscuous_enable,
98 .promiscuous_disable = ionic_dev_promiscuous_disable,
99 .allmulticast_enable = ionic_dev_allmulticast_enable,
100 .allmulticast_disable = ionic_dev_allmulticast_disable,
101 .flow_ctrl_get = ionic_flow_ctrl_get,
102 .flow_ctrl_set = ionic_flow_ctrl_set,
103 .rxq_info_get = ionic_rxq_info_get,
104 .txq_info_get = ionic_txq_info_get,
105 .rx_queue_setup = ionic_dev_rx_queue_setup,
106 .rx_queue_release = ionic_dev_rx_queue_release,
107 .rx_queue_start = ionic_dev_rx_queue_start,
108 .rx_queue_stop = ionic_dev_rx_queue_stop,
109 .tx_queue_setup = ionic_dev_tx_queue_setup,
110 .tx_queue_release = ionic_dev_tx_queue_release,
111 .tx_queue_start = ionic_dev_tx_queue_start,
112 .tx_queue_stop = ionic_dev_tx_queue_stop,
113 .vlan_offload_set = ionic_vlan_offload_set,
114 .reta_update = ionic_dev_rss_reta_update,
115 .reta_query = ionic_dev_rss_reta_query,
116 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get,
117 .rss_hash_update = ionic_dev_rss_hash_update,
118 .stats_get = ionic_dev_stats_get,
119 .stats_reset = ionic_dev_stats_reset,
120 .xstats_get = ionic_dev_xstats_get,
121 .xstats_get_by_id = ionic_dev_xstats_get_by_id,
122 .xstats_reset = ionic_dev_xstats_reset,
123 .xstats_get_names = ionic_dev_xstats_get_names,
124 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id,
125 .fw_version_get = ionic_dev_fw_version_get,
128 struct rte_ionic_xstats_name_off {
129 char name[RTE_ETH_XSTATS_NAME_SIZE];
133 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = {
135 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats,
137 {"rx_ucast_packets", offsetof(struct ionic_lif_stats,
139 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats,
141 {"rx_mcast_packets", offsetof(struct ionic_lif_stats,
143 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats,
145 {"rx_bcast_packets", offsetof(struct ionic_lif_stats,
148 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
149 rx_ucast_drop_bytes)},
150 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
151 rx_ucast_drop_packets)},
152 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
153 rx_mcast_drop_bytes)},
154 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
155 rx_mcast_drop_packets)},
156 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
157 rx_bcast_drop_bytes)},
158 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
159 rx_bcast_drop_packets)},
160 {"rx_dma_error", offsetof(struct ionic_lif_stats,
163 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats,
165 {"tx_ucast_packets", offsetof(struct ionic_lif_stats,
167 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats,
169 {"tx_mcast_packets", offsetof(struct ionic_lif_stats,
171 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats,
173 {"tx_bcast_packets", offsetof(struct ionic_lif_stats,
176 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
177 tx_ucast_drop_bytes)},
178 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
179 tx_ucast_drop_packets)},
180 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
181 tx_mcast_drop_bytes)},
182 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
183 tx_mcast_drop_packets)},
184 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
185 tx_bcast_drop_bytes)},
186 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
187 tx_bcast_drop_packets)},
188 {"tx_dma_error", offsetof(struct ionic_lif_stats,
190 /* Rx Queue/Ring drops */
191 {"rx_queue_disabled", offsetof(struct ionic_lif_stats,
193 {"rx_queue_empty", offsetof(struct ionic_lif_stats,
195 {"rx_queue_error", offsetof(struct ionic_lif_stats,
197 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats,
198 rx_desc_fetch_error)},
199 {"rx_desc_data_error", offsetof(struct ionic_lif_stats,
200 rx_desc_data_error)},
201 /* Tx Queue/Ring drops */
202 {"tx_queue_disabled", offsetof(struct ionic_lif_stats,
204 {"tx_queue_error", offsetof(struct ionic_lif_stats,
206 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats,
207 tx_desc_fetch_error)},
208 {"tx_desc_data_error", offsetof(struct ionic_lif_stats,
209 tx_desc_data_error)},
212 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \
213 sizeof(rte_ionic_xstats_strings[0]))
216 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev,
217 char *fw_version, size_t fw_size)
219 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
220 struct ionic_adapter *adapter = lif->adapter;
222 if (fw_version == NULL || fw_size <= 0)
225 snprintf(fw_version, fw_size, "%s",
226 adapter->fw_version);
227 fw_version[fw_size - 1] = '\0';
233 * Set device link up, enable tx.
236 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev)
238 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
239 struct ionic_adapter *adapter = lif->adapter;
240 struct ionic_dev *idev = &adapter->idev;
245 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP);
247 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
249 IONIC_PRINT(WARNING, "Failed to bring port UP");
257 * Set device link down, disable tx.
260 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev)
262 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
263 struct ionic_adapter *adapter = lif->adapter;
264 struct ionic_dev *idev = &adapter->idev;
269 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN);
271 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
273 IONIC_PRINT(WARNING, "Failed to bring port DOWN");
281 ionic_dev_link_update(struct rte_eth_dev *eth_dev,
282 int wait_to_complete __rte_unused)
284 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
285 struct ionic_adapter *adapter = lif->adapter;
286 struct rte_eth_link link;
291 memset(&link, 0, sizeof(link));
292 link.link_autoneg = ETH_LINK_AUTONEG;
294 if (!adapter->link_up) {
295 /* Interface is down */
296 link.link_status = ETH_LINK_DOWN;
297 link.link_duplex = ETH_LINK_HALF_DUPLEX;
298 link.link_speed = ETH_SPEED_NUM_NONE;
300 /* Interface is up */
301 link.link_status = ETH_LINK_UP;
302 link.link_duplex = ETH_LINK_FULL_DUPLEX;
303 switch (adapter->link_speed) {
305 link.link_speed = ETH_SPEED_NUM_10G;
308 link.link_speed = ETH_SPEED_NUM_25G;
311 link.link_speed = ETH_SPEED_NUM_40G;
314 link.link_speed = ETH_SPEED_NUM_50G;
317 link.link_speed = ETH_SPEED_NUM_100G;
320 link.link_speed = ETH_SPEED_NUM_NONE;
325 return rte_eth_linkstatus_set(eth_dev, &link);
329 * Interrupt handler triggered by NIC for handling
330 * specific interrupt.
333 * The address of parameter registered before.
339 ionic_dev_interrupt_handler(void *param)
341 struct ionic_adapter *adapter = (struct ionic_adapter *)param;
344 IONIC_PRINT(DEBUG, "->");
346 for (i = 0; i < adapter->nlifs; i++) {
347 if (adapter->lifs[i])
348 ionic_notifyq_handler(adapter->lifs[i], -1);
353 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
355 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
356 uint32_t max_frame_size;
362 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU
363 * is done by the the API.
367 * Max frame size is MTU + Ethernet header + VLAN + QinQ
368 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC)
370 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4;
372 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size)
375 err = ionic_lif_change_mtu(lif, mtu);
383 ionic_dev_info_get(struct rte_eth_dev *eth_dev,
384 struct rte_eth_dev_info *dev_info)
386 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
387 struct ionic_adapter *adapter = lif->adapter;
388 struct ionic_identity *ident = &adapter->ident;
392 dev_info->max_rx_queues = (uint16_t)
393 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
394 dev_info->max_tx_queues = (uint16_t)
395 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
396 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */
397 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN;
398 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN;
399 dev_info->max_mac_addrs = adapter->max_mac_addrs;
400 dev_info->min_mtu = IONIC_MIN_MTU;
401 dev_info->max_mtu = IONIC_MAX_MTU;
403 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;
404 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz;
405 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;
407 dev_info->speed_capa =
415 * Per-queue capabilities. Actually most of the offloads are enabled
416 * by default on the port and can be used on selected queues (by adding
417 * packet flags at runtime when required)
420 dev_info->rx_queue_offload_capa =
421 DEV_RX_OFFLOAD_IPV4_CKSUM |
422 DEV_RX_OFFLOAD_UDP_CKSUM |
423 DEV_RX_OFFLOAD_TCP_CKSUM |
426 dev_info->tx_queue_offload_capa =
427 DEV_TX_OFFLOAD_IPV4_CKSUM |
428 DEV_TX_OFFLOAD_UDP_CKSUM |
429 DEV_TX_OFFLOAD_TCP_CKSUM |
430 DEV_TX_OFFLOAD_VLAN_INSERT |
431 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
432 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM |
436 * Per-port capabilities
437 * See ionic_set_features to request and check supported features
440 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa |
441 DEV_RX_OFFLOAD_JUMBO_FRAME |
442 DEV_RX_OFFLOAD_VLAN_FILTER |
443 DEV_RX_OFFLOAD_VLAN_STRIP |
444 DEV_RX_OFFLOAD_SCATTER |
447 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa |
448 DEV_TX_OFFLOAD_MULTI_SEGS |
449 DEV_TX_OFFLOAD_TCP_TSO |
452 dev_info->rx_desc_lim = rx_desc_lim;
453 dev_info->tx_desc_lim = tx_desc_lim;
455 /* Driver-preferred Rx/Tx parameters */
456 dev_info->default_rxportconf.burst_size = 32;
457 dev_info->default_txportconf.burst_size = 32;
458 dev_info->default_rxportconf.nb_queues = 1;
459 dev_info->default_txportconf.nb_queues = 1;
460 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC;
461 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC;
467 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
468 struct rte_eth_fc_conf *fc_conf)
470 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
471 struct ionic_adapter *adapter = lif->adapter;
472 struct ionic_dev *idev = &adapter->idev;
474 if (idev->port_info) {
475 fc_conf->autoneg = idev->port_info->config.an_enable;
477 if (idev->port_info->config.pause_type)
478 fc_conf->mode = RTE_FC_FULL;
480 fc_conf->mode = RTE_FC_NONE;
487 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
488 struct rte_eth_fc_conf *fc_conf)
490 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
491 struct ionic_adapter *adapter = lif->adapter;
492 struct ionic_dev *idev = &adapter->idev;
493 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
496 switch (fc_conf->mode) {
498 pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
501 pause_type = IONIC_PORT_PAUSE_TYPE_LINK;
503 case RTE_FC_RX_PAUSE:
504 case RTE_FC_TX_PAUSE:
508 an_enable = fc_conf->autoneg;
510 ionic_dev_cmd_port_pause(idev, pause_type);
511 ionic_dev_cmd_port_autoneg(idev, an_enable);
517 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
519 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
520 struct rte_eth_rxmode *rxmode;
521 rxmode = ð_dev->data->dev_conf.rxmode;
524 if (mask & ETH_VLAN_STRIP_MASK) {
525 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
526 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
527 struct ionic_qcq *rxq =
528 eth_dev->data->rx_queues[i];
529 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
531 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
533 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
534 struct ionic_qcq *rxq =
535 eth_dev->data->rx_queues[i];
536 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
538 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
542 if (mask & ETH_VLAN_FILTER_MASK) {
543 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
544 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER;
546 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER;
549 ionic_lif_set_features(lif);
555 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
556 struct rte_eth_rss_reta_entry64 *reta_conf,
559 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
560 struct ionic_adapter *adapter = lif->adapter;
561 struct ionic_identity *ident = &adapter->ident;
562 uint32_t i, j, index, num;
566 if (!lif->rss_ind_tbl) {
567 IONIC_PRINT(ERR, "RSS RETA not initialized, "
568 "can't update the table");
572 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
573 IONIC_PRINT(ERR, "The size of hash lookup table configured "
574 "(%d) doesn't match the number hardware can supported "
576 reta_size, ident->lif.eth.rss_ind_tbl_sz);
580 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE;
582 for (i = 0; i < num; i++) {
583 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
584 if (reta_conf[i].mask & ((uint64_t)1 << j)) {
585 index = (i * RTE_RETA_GROUP_SIZE) + j;
586 lif->rss_ind_tbl[index] = reta_conf[i].reta[j];
591 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
595 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
596 struct rte_eth_rss_reta_entry64 *reta_conf,
599 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
600 struct ionic_adapter *adapter = lif->adapter;
601 struct ionic_identity *ident = &adapter->ident;
606 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
607 IONIC_PRINT(ERR, "The size of hash lookup table configured "
608 "(%d) doesn't match the number hardware can supported "
610 reta_size, ident->lif.eth.rss_ind_tbl_sz);
614 if (!lif->rss_ind_tbl) {
615 IONIC_PRINT(ERR, "RSS RETA has not been built yet");
619 num = reta_size / RTE_RETA_GROUP_SIZE;
621 for (i = 0; i < num; i++) {
622 memcpy(reta_conf->reta,
623 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE],
624 RTE_RETA_GROUP_SIZE);
632 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
633 struct rte_eth_rss_conf *rss_conf)
635 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
640 if (!lif->rss_ind_tbl) {
641 IONIC_PRINT(NOTICE, "RSS not enabled");
645 /* Get key value (if not null, rss_key is 40-byte) */
646 if (rss_conf->rss_key != NULL &&
647 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE)
648 memcpy(rss_conf->rss_key, lif->rss_hash_key,
649 IONIC_RSS_HASH_KEY_SIZE);
651 if (lif->rss_types & IONIC_RSS_TYPE_IPV4)
652 rss_hf |= ETH_RSS_IPV4;
653 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP)
654 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
655 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP)
656 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
657 if (lif->rss_types & IONIC_RSS_TYPE_IPV6)
658 rss_hf |= ETH_RSS_IPV6;
659 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP)
660 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
661 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP)
662 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
664 rss_conf->rss_hf = rss_hf;
670 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
671 struct rte_eth_rss_conf *rss_conf)
673 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
674 uint32_t rss_types = 0;
679 if (rss_conf->rss_key)
680 key = rss_conf->rss_key;
682 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) {
684 * Can't disable rss through hash flags,
685 * if it is enabled by default during init
687 if (lif->rss_ind_tbl)
690 /* Can't enable rss if disabled by default during init */
691 if (!lif->rss_ind_tbl)
694 if (rss_conf->rss_hf & ETH_RSS_IPV4)
695 rss_types |= IONIC_RSS_TYPE_IPV4;
696 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
697 rss_types |= IONIC_RSS_TYPE_IPV4_TCP;
698 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
699 rss_types |= IONIC_RSS_TYPE_IPV4_UDP;
700 if (rss_conf->rss_hf & ETH_RSS_IPV6)
701 rss_types |= IONIC_RSS_TYPE_IPV6;
702 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
703 rss_types |= IONIC_RSS_TYPE_IPV6_TCP;
704 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
705 rss_types |= IONIC_RSS_TYPE_IPV6_UDP;
707 ionic_lif_rss_config(lif, rss_types, key, NULL);
714 ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
715 struct rte_eth_stats *stats)
717 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
719 ionic_lif_get_stats(lif, stats);
725 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev)
727 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
731 ionic_lif_reset_stats(lif);
737 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev,
738 struct rte_eth_xstat_name *xstats_names,
739 __rte_unused unsigned int size)
743 if (xstats_names != NULL) {
744 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
745 snprintf(xstats_names[i].name,
746 sizeof(xstats_names[i].name),
747 "%s", rte_ionic_xstats_strings[i].name);
751 return IONIC_NB_HW_STATS;
755 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
756 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
759 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS];
763 if (xstats_names != NULL) {
764 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
765 snprintf(xstats_names[i].name,
766 sizeof(xstats_names[i].name),
767 "%s", rte_ionic_xstats_strings[i].name);
771 return IONIC_NB_HW_STATS;
774 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL,
777 for (i = 0; i < limit; i++) {
778 if (ids[i] >= IONIC_NB_HW_STATS) {
779 IONIC_PRINT(ERR, "id value isn't valid");
783 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
790 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats,
793 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
794 struct ionic_lif_stats hw_stats;
797 if (n < IONIC_NB_HW_STATS)
798 return IONIC_NB_HW_STATS;
800 ionic_lif_get_hw_stats(lif, &hw_stats);
802 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
803 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) +
804 rte_ionic_xstats_strings[i].offset);
808 return IONIC_NB_HW_STATS;
812 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
813 uint64_t *values, unsigned int n)
815 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
816 struct ionic_lif_stats hw_stats;
817 uint64_t values_copy[IONIC_NB_HW_STATS];
821 if (!ids && n < IONIC_NB_HW_STATS)
822 return IONIC_NB_HW_STATS;
824 ionic_lif_get_hw_stats(lif, &hw_stats);
826 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
827 values[i] = *(uint64_t *)(((char *)&hw_stats) +
828 rte_ionic_xstats_strings[i].offset);
831 return IONIC_NB_HW_STATS;
834 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy,
837 for (i = 0; i < n; i++) {
838 if (ids[i] >= IONIC_NB_HW_STATS) {
839 IONIC_PRINT(ERR, "id value isn't valid");
843 values[i] = values_copy[ids[i]];
850 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev)
852 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
854 ionic_lif_reset_hw_stats(lif);
860 ionic_dev_configure(struct rte_eth_dev *eth_dev)
862 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
867 err = ionic_lif_configure(lif);
869 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err);
876 static inline uint32_t
877 ionic_parse_link_speeds(uint16_t link_speeds)
879 if (link_speeds & ETH_LINK_SPEED_100G)
881 else if (link_speeds & ETH_LINK_SPEED_50G)
883 else if (link_speeds & ETH_LINK_SPEED_40G)
885 else if (link_speeds & ETH_LINK_SPEED_25G)
887 else if (link_speeds & ETH_LINK_SPEED_10G)
894 * Configure device link speed and setup link.
895 * It returns 0 on success.
898 ionic_dev_start(struct rte_eth_dev *eth_dev)
900 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf;
901 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
902 struct ionic_adapter *adapter = lif->adapter;
903 struct ionic_dev *idev = &adapter->idev;
904 uint32_t allowed_speeds;
910 ETH_LINK_SPEED_FIXED |
917 if (dev_conf->link_speeds & ~allowed_speeds) {
918 IONIC_PRINT(ERR, "Invalid link setting");
922 err = ionic_lif_start(lif);
924 IONIC_PRINT(ERR, "Cannot start LIF: %d", err);
928 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
929 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds);
932 ionic_dev_cmd_port_speed(idev, speed);
935 ionic_dev_link_update(eth_dev, 0);
941 * Stop device: disable rx and tx functions to allow for reconfiguring.
944 ionic_dev_stop(struct rte_eth_dev *eth_dev)
946 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
951 err = ionic_lif_stop(lif);
953 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err);
957 * Reset and stop device.
960 ionic_dev_close(struct rte_eth_dev *eth_dev)
962 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
966 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
969 err = ionic_lif_stop(lif);
971 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err);
975 err = eth_ionic_dev_uninit(eth_dev);
977 IONIC_PRINT(ERR, "Cannot destroy LIF: %d", err);
985 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params)
987 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
988 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
989 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params;
994 eth_dev->dev_ops = &ionic_eth_dev_ops;
995 eth_dev->rx_pkt_burst = &ionic_recv_pkts;
996 eth_dev->tx_pkt_burst = &ionic_xmit_pkts;
997 eth_dev->tx_pkt_prepare = &ionic_prep_pkts;
999 /* Multi-process not supported, primary does initialization anyway */
1000 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1003 rte_eth_copy_pci_info(eth_dev, pci_dev);
1005 lif->index = adapter->nlifs;
1006 lif->eth_dev = eth_dev;
1007 lif->adapter = adapter;
1008 adapter->lifs[adapter->nlifs] = lif;
1010 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported",
1011 adapter->max_mac_addrs);
1013 /* Allocate memory for storing MAC addresses */
1014 eth_dev->data->mac_addrs = rte_zmalloc("ionic",
1015 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0);
1017 if (eth_dev->data->mac_addrs == NULL) {
1018 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to "
1019 "store MAC addresses",
1020 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs);
1025 err = ionic_lif_alloc(lif);
1027 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting",
1032 err = ionic_lif_init(lif);
1034 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err);
1038 /* Copy the MAC address */
1039 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr,
1040 ð_dev->data->mac_addrs[0]);
1042 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id);
1047 ionic_lif_free(lif);
1053 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev)
1055 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
1056 struct ionic_adapter *adapter = lif->adapter;
1060 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1063 adapter->lifs[lif->index] = NULL;
1065 ionic_lif_deinit(lif);
1066 ionic_lif_free(lif);
1068 eth_dev->dev_ops = NULL;
1069 eth_dev->rx_pkt_burst = NULL;
1070 eth_dev->tx_pkt_burst = NULL;
1071 eth_dev->tx_pkt_prepare = NULL;
1077 ionic_configure_intr(struct ionic_adapter *adapter)
1079 struct rte_pci_device *pci_dev = adapter->pci_dev;
1080 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1083 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs);
1085 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) {
1086 IONIC_PRINT(ERR, "Fail to create eventfd");
1090 if (rte_intr_dp_is_en(intr_handle))
1092 "Packet I/O interrupt on datapath is enabled");
1094 if (!intr_handle->intr_vec) {
1095 intr_handle->intr_vec = rte_zmalloc("intr_vec",
1096 adapter->nintrs * sizeof(int), 0);
1098 if (!intr_handle->intr_vec) {
1099 IONIC_PRINT(ERR, "Failed to allocate %u vectors",
1105 err = rte_intr_callback_register(intr_handle,
1106 ionic_dev_interrupt_handler,
1111 "Failure registering interrupts handler (%d)",
1116 /* enable intr mapping */
1117 err = rte_intr_enable(intr_handle);
1120 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err);
1128 ionic_unconfigure_intr(struct ionic_adapter *adapter)
1130 struct rte_pci_device *pci_dev = adapter->pci_dev;
1131 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1133 rte_intr_disable(intr_handle);
1135 rte_intr_callback_unregister(intr_handle,
1136 ionic_dev_interrupt_handler,
1141 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1142 struct rte_pci_device *pci_dev)
1144 char name[RTE_ETH_NAME_MAX_LEN];
1145 struct rte_mem_resource *resource;
1146 struct ionic_adapter *adapter;
1147 struct ionic_hw *hw;
1151 /* Check structs (trigger error at compilation time) */
1152 ionic_struct_size_checks();
1154 /* Multi-process not supported */
1155 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1160 IONIC_PRINT(DEBUG, "Initializing device %s",
1161 pci_dev->device.name);
1163 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0);
1165 IONIC_PRINT(ERR, "OOM");
1170 adapter->pci_dev = pci_dev;
1173 hw->device_id = pci_dev->id.device_id;
1174 hw->vendor_id = pci_dev->id.vendor_id;
1176 err = ionic_init_mac(hw);
1178 IONIC_PRINT(ERR, "Mac init failed: %d", err);
1180 goto err_free_adapter;
1183 adapter->is_mgmt_nic = (pci_dev->id.device_id == IONIC_DEV_ID_ETH_MGMT);
1185 adapter->num_bars = 0;
1186 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) {
1187 resource = &pci_dev->mem_resource[i];
1188 if (resource->phys_addr == 0 || resource->len == 0)
1190 adapter->bars[adapter->num_bars].vaddr = resource->addr;
1191 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr;
1192 adapter->bars[adapter->num_bars].len = resource->len;
1193 adapter->num_bars++;
1196 /* Discover ionic dev resources */
1198 err = ionic_setup(adapter);
1200 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err);
1201 goto err_free_adapter;
1204 err = ionic_identify(adapter);
1206 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting",
1208 goto err_free_adapter;
1211 err = ionic_init(adapter);
1213 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err);
1214 goto err_free_adapter;
1217 /* Configure the ports */
1218 err = ionic_port_identify(adapter);
1220 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting",
1222 goto err_free_adapter;
1225 err = ionic_port_init(adapter);
1227 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err);
1228 goto err_free_adapter;
1231 /* Configure LIFs */
1232 err = ionic_lif_identify(adapter);
1234 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err);
1235 goto err_free_adapter;
1238 /* Allocate and init LIFs */
1239 err = ionic_lifs_size(adapter);
1241 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err);
1242 goto err_free_adapter;
1245 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters;
1248 for (i = 0; i < adapter->ident.dev.nlifs; i++) {
1249 snprintf(name, sizeof(name), "net_%s_lif_%lu",
1250 pci_dev->device.name, i);
1252 err = rte_eth_dev_create(&pci_dev->device, name,
1253 sizeof(struct ionic_lif),
1255 eth_ionic_dev_init, adapter);
1257 IONIC_PRINT(ERR, "Cannot create eth device for "
1258 "ionic lif %s", name);
1265 err = ionic_configure_intr(adapter);
1268 IONIC_PRINT(ERR, "Failed to configure interrupts");
1269 goto err_free_adapter;
1281 eth_ionic_pci_remove(struct rte_pci_device *pci_dev __rte_unused)
1283 char name[RTE_ETH_NAME_MAX_LEN];
1284 struct ionic_adapter *adapter = NULL;
1285 struct rte_eth_dev *eth_dev;
1286 struct ionic_lif *lif;
1289 /* Adapter lookup is using (the first) eth_dev name */
1290 snprintf(name, sizeof(name), "net_%s_lif_0",
1291 pci_dev->device.name);
1293 eth_dev = rte_eth_dev_allocated(name);
1295 lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
1296 adapter = lif->adapter;
1300 ionic_unconfigure_intr(adapter);
1302 for (i = 0; i < adapter->nlifs; i++) {
1303 lif = adapter->lifs[i];
1304 rte_eth_dev_destroy(lif->eth_dev, eth_ionic_dev_uninit);
1313 static struct rte_pci_driver rte_ionic_pmd = {
1314 .id_table = pci_id_ionic_map,
1315 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1316 .probe = eth_ionic_pci_probe,
1317 .remove = eth_ionic_pci_remove,
1320 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd);
1321 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map);
1322 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci");
1323 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE);