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35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82598.h"
40 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
41 * @hw: pointer to hardware structure
42 * @stats: pointer to statistics structure
43 * @tc_count: Number of elements in bwg_array.
45 * This function returns the status data for each of the Traffic Classes in use.
47 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
48 struct ixgbe_hw_stats *stats,
53 DEBUGFUNC("dcb_get_tc_stats");
55 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
56 return IXGBE_ERR_PARAM;
58 /* Statistics pertaining to each traffic class */
59 for (tc = 0; tc < tc_count; tc++) {
60 /* Transmitted Packets */
61 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
62 /* Transmitted Bytes */
63 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
64 /* Received Packets */
65 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
67 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
70 /* Can we get rid of these?? Consequently, getting rid
71 * of the tc_stats structure.
73 tc_stats_array[up]->in_overflow_discards = 0;
74 tc_stats_array[up]->out_overflow_discards = 0;
82 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
83 * @hw: pointer to hardware structure
84 * @stats: pointer to statistics structure
85 * @tc_count: Number of elements in bwg_array.
87 * This function returns the CBFC status data for each of the Traffic Classes.
89 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
90 struct ixgbe_hw_stats *stats,
95 DEBUGFUNC("dcb_get_pfc_stats");
97 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
98 return IXGBE_ERR_PARAM;
100 for (tc = 0; tc < tc_count; tc++) {
101 /* Priority XOFF Transmitted */
102 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
103 /* Priority XOFF Received */
104 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
107 return IXGBE_SUCCESS;
111 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
112 * @hw: pointer to hardware structure
113 * @refill: refill credits index by traffic class
114 * @max: max credits index by traffic class
115 * @tsa: transmission selection algorithm indexed by traffic class
117 * Configure Rx Data Arbiter and credits for each traffic class.
119 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
123 u32 credit_refill = 0;
127 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
128 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
130 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
132 reg &= ~IXGBE_RMCS_ARBDIS;
133 /* Enable Receive Recycle within the BWG */
134 reg |= IXGBE_RMCS_RRM;
135 /* Enable Deficit Fixed Priority arbitration*/
136 reg |= IXGBE_RMCS_DFP;
138 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
140 /* Configure traffic class credits and priority */
141 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
142 credit_refill = refill[i];
145 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
147 if (tsa[i] == ixgbe_dcb_tsa_strict)
148 reg |= IXGBE_RT2CR_LSP;
150 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
153 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
154 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
155 reg |= IXGBE_RDRXCTL_MPBEN;
156 reg |= IXGBE_RDRXCTL_MCEN;
157 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
159 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
160 /* Make sure there is enough descriptors before arbitration */
161 reg &= ~IXGBE_RXCTRL_DMBYPS;
162 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
164 return IXGBE_SUCCESS;
168 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
169 * @hw: pointer to hardware structure
170 * @refill: refill credits index by traffic class
171 * @max: max credits index by traffic class
172 * @bwg_id: bandwidth grouping indexed by traffic class
173 * @tsa: transmission selection algorithm indexed by traffic class
175 * Configure Tx Descriptor Arbiter and credits for each traffic class.
177 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
178 u16 *refill, u16 *max, u8 *bwg_id,
181 u32 reg, max_credits;
184 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
187 reg &= ~IXGBE_DPMCS_ARBDIS;
188 reg |= IXGBE_DPMCS_TSOEF;
190 /* Configure Max TSO packet size 34KB including payload and headers */
191 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
193 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
195 /* Configure traffic class credits and priority */
196 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
197 max_credits = max[i];
198 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
200 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
202 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
203 reg |= IXGBE_TDTQ2TCCR_GSP;
205 if (tsa[i] == ixgbe_dcb_tsa_strict)
206 reg |= IXGBE_TDTQ2TCCR_LSP;
208 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
211 return IXGBE_SUCCESS;
215 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
216 * @hw: pointer to hardware structure
217 * @refill: refill credits index by traffic class
218 * @max: max credits index by traffic class
219 * @bwg_id: bandwidth grouping indexed by traffic class
220 * @tsa: transmission selection algorithm indexed by traffic class
222 * Configure Tx Data Arbiter and credits for each traffic class.
224 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
225 u16 *refill, u16 *max, u8 *bwg_id,
231 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
232 /* Enable Data Plane Arbiter */
233 reg &= ~IXGBE_PDPMCS_ARBDIS;
234 /* Enable DFP and Transmit Recycle Mode */
235 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
237 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
239 /* Configure traffic class credits and priority */
240 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
242 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
243 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
245 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
246 reg |= IXGBE_TDPT2TCCR_GSP;
248 if (tsa[i] == ixgbe_dcb_tsa_strict)
249 reg |= IXGBE_TDPT2TCCR_LSP;
251 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
254 /* Enable Tx packet buffer division */
255 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
256 reg |= IXGBE_DTXCTL_ENDBUBD;
257 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
259 return IXGBE_SUCCESS;
263 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
264 * @hw: pointer to hardware structure
265 * @pfc_en: enabled pfc bitmask
267 * Configure Priority Flow Control for each traffic class.
269 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
274 /* Enable Transmit Priority Flow Control */
275 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
276 reg &= ~IXGBE_RMCS_TFCE_802_3X;
277 reg |= IXGBE_RMCS_TFCE_PRIORITY;
278 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
280 /* Enable Receive Priority Flow Control */
281 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
282 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
285 reg |= IXGBE_FCTRL_RPFCE;
287 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
289 /* Configure PFC Tx thresholds per TC */
290 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
291 if (!(pfc_en & (1 << i))) {
292 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
293 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
297 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
298 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
299 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
300 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
303 /* Configure pause time */
304 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
305 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
306 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
308 /* Configure flow control refresh threshold value */
309 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
311 return IXGBE_SUCCESS;
315 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
316 * @hw: pointer to hardware structure
318 * Configure queue statistics registers, all queues belonging to same traffic
319 * class uses a single set of queue statistics counters.
321 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
327 /* Receive Queues stats setting - 8 queues per statistics reg */
328 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
329 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
330 reg |= ((0x1010101) * j);
331 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
332 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
333 reg |= ((0x1010101) * j);
334 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
336 /* Transmit Queues stats setting - 4 queues per statistics reg*/
337 for (i = 0; i < 8; i++) {
338 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
339 reg |= ((0x1010101) * i);
340 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
343 return IXGBE_SUCCESS;
347 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
348 * @hw: pointer to hardware structure
349 * @link_speed: unused
350 * @refill: refill credits index by traffic class
351 * @max: max credits index by traffic class
352 * @bwg_id: bandwidth grouping indexed by traffic class
353 * @tsa: transmission selection algorithm indexed by traffic class
355 * Configure dcb settings and enable dcb mode.
357 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
358 u16 *refill, u16 *max, u8 *bwg_id,
361 UNREFERENCED_1PARAMETER(link_speed);
363 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
364 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
366 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
368 ixgbe_dcb_config_tc_stats_82598(hw);
371 return IXGBE_SUCCESS;