1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
131 /* Device Address and write indication */
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
134 /* Write bits 14:8 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
143 /* Re-start condition */
145 /* Device Address and read indication */
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
158 if (ixgbe_clock_out_i2c_bit(hw, false))
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
167 ixgbe_i2c_bus_clear(hw);
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
171 if (retry < max_retry)
172 DEBUGOUT("I2C byte read combined error - Retrying.\n");
174 DEBUGOUT("I2C byte read combined error.\n");
175 } while (retry < max_retry);
177 return IXGBE_ERR_I2C;
181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
182 * @hw: pointer to the hardware structure
183 * @addr: I2C bus address to write to
184 * @reg: I2C device register to write to
185 * @val: value to write
186 * @lock: true if to take and release semaphore
188 * Returns an error code on error.
190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
193 u32 swfw_mask = hw->phy.phy_semaphore_mask;
199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
206 return IXGBE_ERR_SWFW_SYNC;
208 /* Device Address and write indication */
209 if (ixgbe_out_i2c_byte_ack(hw, addr))
211 /* Write bits 14:8 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
217 /* Write data 15:8 */
218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
224 if (ixgbe_out_i2c_byte_ack(hw, csum))
228 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 ixgbe_i2c_bus_clear(hw);
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
236 if (retry < max_retry)
237 DEBUGOUT("I2C byte write combined error - Retrying.\n");
239 DEBUGOUT("I2C byte write combined error.\n");
240 } while (retry < max_retry);
242 return IXGBE_ERR_I2C;
246 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
247 * @hw: pointer to the hardware structure
249 * Initialize the function pointers.
251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
253 struct ixgbe_phy_info *phy = &hw->phy;
255 DEBUGFUNC("ixgbe_init_phy_ops_generic");
258 phy->ops.identify = ixgbe_identify_phy_generic;
259 phy->ops.reset = ixgbe_reset_phy_generic;
260 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
261 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
262 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
263 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
264 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
265 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
266 phy->ops.check_link = NULL;
267 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
268 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
269 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
270 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
271 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
272 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
273 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
274 phy->ops.identify_sfp = ixgbe_identify_module_generic;
275 phy->sfp_type = ixgbe_sfp_type_unknown;
276 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
277 phy->ops.write_i2c_byte_unlocked =
278 ixgbe_write_i2c_byte_generic_unlocked;
279 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
280 return IXGBE_SUCCESS;
284 * ixgbe_probe_phy - Probe a single address for a PHY
285 * @hw: pointer to hardware structure
286 * @phy_addr: PHY address to probe
288 * Returns true if PHY found
290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
294 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
295 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
300 if (ixgbe_get_phy_id(hw))
303 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
305 if (hw->phy.type == ixgbe_phy_unknown) {
306 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
309 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
310 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 hw->phy.type = ixgbe_phy_cu_unknown;
313 hw->phy.type = ixgbe_phy_generic;
320 * ixgbe_identify_phy_generic - Get physical layer module
321 * @hw: pointer to hardware structure
323 * Determines the physical layer module found on the current adapter.
325 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
327 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
330 DEBUGFUNC("ixgbe_identify_phy_generic");
332 if (!hw->phy.phy_semaphore_mask) {
334 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
339 if (hw->phy.type != ixgbe_phy_unknown)
340 return IXGBE_SUCCESS;
342 if (hw->phy.nw_mng_if_sel) {
343 phy_addr = (hw->phy.nw_mng_if_sel &
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
346 if (ixgbe_probe_phy(hw, phy_addr))
347 return IXGBE_SUCCESS;
349 return IXGBE_ERR_PHY_ADDR_INVALID;
352 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
353 if (ixgbe_probe_phy(hw, phy_addr)) {
354 status = IXGBE_SUCCESS;
359 /* Certain media types do not have a phy so an address will not
360 * be found and the code will take this path. Caller has to
361 * decide if it is an error or not.
363 if (status != IXGBE_SUCCESS)
370 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
371 * @hw: pointer to the hardware structure
373 * This function checks the MMNGC.MNG_VETO bit to see if there are
374 * any constraints on link from manageability. For MAC's that don't
375 * have this bit just return faluse since the link can not be blocked
378 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
382 DEBUGFUNC("ixgbe_check_reset_blocked");
384 /* If we don't have this bit, it can't be blocking */
385 if (hw->mac.type == ixgbe_mac_82598EB)
388 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
389 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
390 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
391 "MNG_VETO bit detected.\n");
399 * ixgbe_validate_phy_addr - Determines phy address is valid
400 * @hw: pointer to hardware structure
401 * @phy_addr: PHY address
404 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
409 DEBUGFUNC("ixgbe_validate_phy_addr");
411 hw->phy.addr = phy_addr;
412 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
413 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
415 if (phy_id != 0xFFFF && phy_id != 0x0)
418 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
424 * ixgbe_get_phy_id - Get the phy type
425 * @hw: pointer to hardware structure
428 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
434 DEBUGFUNC("ixgbe_get_phy_id");
436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
437 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
440 if (status == IXGBE_SUCCESS) {
441 hw->phy.id = (u32)(phy_id_high << 16);
442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
443 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
445 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
446 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
448 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
449 phy_id_high, phy_id_low);
455 * ixgbe_get_phy_type_from_id - Get the phy type
456 * @phy_id: PHY ID information
459 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
461 enum ixgbe_phy_type phy_type;
463 DEBUGFUNC("ixgbe_get_phy_type_from_id");
467 phy_type = ixgbe_phy_tn;
472 phy_type = ixgbe_phy_aq;
475 phy_type = ixgbe_phy_qt;
478 phy_type = ixgbe_phy_nl;
482 phy_type = ixgbe_phy_x550em_ext_t;
484 case IXGBE_M88E1500_E_PHY_ID:
485 case IXGBE_M88E1543_E_PHY_ID:
486 phy_type = ixgbe_phy_ext_1g_t;
489 phy_type = ixgbe_phy_unknown;
496 * ixgbe_reset_phy_generic - Performs a PHY reset
497 * @hw: pointer to hardware structure
499 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
503 s32 status = IXGBE_SUCCESS;
505 DEBUGFUNC("ixgbe_reset_phy_generic");
507 if (hw->phy.type == ixgbe_phy_unknown)
508 status = ixgbe_identify_phy_generic(hw);
510 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
513 /* Don't reset PHY if it's shut down due to overtemp. */
514 if (!hw->phy.reset_if_overtemp &&
515 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
518 /* Blocked by MNG FW so bail */
519 if (ixgbe_check_reset_blocked(hw))
523 * Perform soft PHY reset to the PHY_XS.
524 * This will cause a soft reset to the PHY
526 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
527 IXGBE_MDIO_PHY_XS_DEV_TYPE,
528 IXGBE_MDIO_PHY_XS_RESET);
531 * Poll for reset bit to self-clear indicating reset is complete.
532 * Some PHYs could take up to 3 seconds to complete and need about
533 * 1.7 usec delay after the reset is complete.
535 for (i = 0; i < 30; i++) {
537 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
538 status = hw->phy.ops.read_reg(hw,
539 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
540 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
542 if (status != IXGBE_SUCCESS)
545 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
550 status = hw->phy.ops.read_reg(hw,
551 IXGBE_MDIO_PHY_XS_CONTROL,
552 IXGBE_MDIO_PHY_XS_DEV_TYPE,
554 if (status != IXGBE_SUCCESS)
557 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
564 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
565 status = IXGBE_ERR_RESET_FAILED;
566 ERROR_REPORT1(IXGBE_ERROR_POLLING,
567 "PHY reset polling failed to complete.\n");
575 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
577 * @hw: pointer to hardware structure
578 * @reg_addr: 32 bit address of PHY register to read
579 * @device_type: 5 bit device type
580 * @phy_data: Pointer to read data from PHY register
582 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
585 u32 i, data, command;
587 /* Setup and write the address cycle command */
588 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
589 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
590 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
591 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
593 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
596 * Check every 10 usec to see if the address cycle completed.
597 * The MDI Command bit will clear when the operation is
600 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
603 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
604 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
609 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
610 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
611 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
612 return IXGBE_ERR_PHY;
616 * Address cycle complete, setup and write the read
619 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
620 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
621 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
622 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
624 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
627 * Check every 10 usec to see if the address cycle
628 * completed. The MDI Command bit will clear when the
629 * operation is complete
631 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
634 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
635 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
639 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
640 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
641 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
642 return IXGBE_ERR_PHY;
646 * Read operation is complete. Get the data
649 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
650 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
651 *phy_data = (u16)(data);
653 return IXGBE_SUCCESS;
657 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
658 * using the SWFW lock - this function is needed in most cases
659 * @hw: pointer to hardware structure
660 * @reg_addr: 32 bit address of PHY register to read
661 * @device_type: 5 bit device type
662 * @phy_data: Pointer to read data from PHY register
664 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
665 u32 device_type, u16 *phy_data)
668 u32 gssr = hw->phy.phy_semaphore_mask;
670 DEBUGFUNC("ixgbe_read_phy_reg_generic");
672 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
673 return IXGBE_ERR_SWFW_SYNC;
675 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
677 hw->mac.ops.release_swfw_sync(hw, gssr);
683 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
685 * @hw: pointer to hardware structure
686 * @reg_addr: 32 bit PHY register to write
687 * @device_type: 5 bit device type
688 * @phy_data: Data to write to the PHY register
690 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
691 u32 device_type, u16 phy_data)
695 /* Put the data in the MDI single read and write data register*/
696 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
698 /* Setup and write the address cycle command */
699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
707 * Check every 10 usec to see if the address cycle completed.
708 * The MDI Command bit will clear when the operation is
711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
714 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
721 return IXGBE_ERR_PHY;
725 * Address cycle complete, setup and write the write
728 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
729 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
730 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
731 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
733 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
736 * Check every 10 usec to see if the address cycle
737 * completed. The MDI Command bit will clear when the
738 * operation is complete
740 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
743 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
744 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
748 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
749 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
750 return IXGBE_ERR_PHY;
753 return IXGBE_SUCCESS;
757 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
758 * using SWFW lock- this function is needed in most cases
759 * @hw: pointer to hardware structure
760 * @reg_addr: 32 bit PHY register to write
761 * @device_type: 5 bit device type
762 * @phy_data: Data to write to the PHY register
764 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
765 u32 device_type, u16 phy_data)
768 u32 gssr = hw->phy.phy_semaphore_mask;
770 DEBUGFUNC("ixgbe_write_phy_reg_generic");
772 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
773 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
775 hw->mac.ops.release_swfw_sync(hw, gssr);
777 status = IXGBE_ERR_SWFW_SYNC;
784 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
785 * @hw: pointer to hardware structure
787 * Restart auto-negotiation and PHY and waits for completion.
789 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
791 s32 status = IXGBE_SUCCESS;
792 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
793 bool autoneg = false;
794 ixgbe_link_speed speed;
796 DEBUGFUNC("ixgbe_setup_phy_link_generic");
798 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
800 /* Set or unset auto-negotiation 10G advertisement */
801 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
806 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
807 (speed & IXGBE_LINK_SPEED_10GB_FULL))
808 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
810 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
814 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
818 if (hw->mac.type == ixgbe_mac_X550) {
819 /* Set or unset auto-negotiation 5G advertisement */
820 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
822 (speed & IXGBE_LINK_SPEED_5GB_FULL))
823 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
825 /* Set or unset auto-negotiation 2.5G advertisement */
826 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
827 if ((hw->phy.autoneg_advertised &
828 IXGBE_LINK_SPEED_2_5GB_FULL) &&
829 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
830 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
833 /* Set or unset auto-negotiation 1G advertisement */
834 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
835 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
836 (speed & IXGBE_LINK_SPEED_1GB_FULL))
837 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
839 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
840 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
843 /* Set or unset auto-negotiation 100M advertisement */
844 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
845 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
848 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
849 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
851 (speed & IXGBE_LINK_SPEED_100_FULL))
852 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
858 /* Blocked by MNG FW so don't reset PHY */
859 if (ixgbe_check_reset_blocked(hw))
862 /* Restart PHY auto-negotiation. */
863 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
866 autoneg_reg |= IXGBE_MII_RESTART;
868 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
869 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
875 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
876 * @hw: pointer to hardware structure
877 * @speed: new link speed
878 * @autoneg_wait_to_complete: unused
880 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
881 ixgbe_link_speed speed,
882 bool autoneg_wait_to_complete)
884 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
886 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
889 * Clear autoneg_advertised and set new values based on input link
892 hw->phy.autoneg_advertised = 0;
894 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
895 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
897 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
900 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
903 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
906 if (speed & IXGBE_LINK_SPEED_100_FULL)
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
909 if (speed & IXGBE_LINK_SPEED_10_FULL)
910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
912 /* Setup link based on the new speed settings */
913 ixgbe_setup_phy_link(hw);
915 return IXGBE_SUCCESS;
919 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
920 * @hw: pointer to hardware structure
922 * Determines the supported link capabilities by reading the PHY auto
923 * negotiation register.
925 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
930 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
931 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
940 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
943 switch (hw->mac.type) {
945 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
948 case ixgbe_mac_X550EM_x:
949 case ixgbe_mac_X550EM_a:
950 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
960 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
961 * @hw: pointer to hardware structure
962 * @speed: pointer to link speed
963 * @autoneg: boolean auto-negotiation value
965 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
966 ixgbe_link_speed *speed,
969 s32 status = IXGBE_SUCCESS;
971 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
974 if (!hw->phy.speeds_supported)
975 status = ixgbe_get_copper_speeds_supported(hw);
977 *speed = hw->phy.speeds_supported;
982 * ixgbe_check_phy_link_tnx - Determine link and speed status
983 * @hw: pointer to hardware structure
984 * @speed: current link speed
985 * @link_up: true is link is up, false otherwise
987 * Reads the VS1 register to determine if link is up and the current speed for
990 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
993 s32 status = IXGBE_SUCCESS;
995 u32 max_time_out = 10;
1000 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1002 /* Initialize speed and link to default case */
1004 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1007 * Check current speed and link status of the PHY register.
1008 * This is a vendor specific register and may have to
1009 * be changed for other copper PHYs.
1011 for (time_out = 0; time_out < max_time_out; time_out++) {
1013 status = hw->phy.ops.read_reg(hw,
1014 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1015 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1017 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1018 phy_speed = phy_data &
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1020 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1023 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1024 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1033 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1034 * @hw: pointer to hardware structure
1036 * Restart auto-negotiation and PHY and waits for completion.
1038 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1040 s32 status = IXGBE_SUCCESS;
1041 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1042 bool autoneg = false;
1043 ixgbe_link_speed speed;
1045 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1047 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1049 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1050 /* Set or unset auto-negotiation 10G advertisement */
1051 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1052 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1056 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1057 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1059 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1060 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1065 /* Set or unset auto-negotiation 1G advertisement */
1066 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1067 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1070 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1071 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1072 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1074 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1075 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1080 /* Set or unset auto-negotiation 100M advertisement */
1081 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1085 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1087 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1089 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1090 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1094 /* Blocked by MNG FW so don't reset PHY */
1095 if (ixgbe_check_reset_blocked(hw))
1098 /* Restart PHY auto-negotiation. */
1099 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1102 autoneg_reg |= IXGBE_MII_RESTART;
1104 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1111 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1112 * @hw: pointer to hardware structure
1113 * @firmware_version: pointer to the PHY Firmware Version
1115 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1116 u16 *firmware_version)
1120 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1122 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1123 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1130 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1131 * @hw: pointer to hardware structure
1132 * @firmware_version: pointer to the PHY Firmware Version
1134 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1135 u16 *firmware_version)
1139 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1141 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1142 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1149 * ixgbe_reset_phy_nl - Performs a PHY reset
1150 * @hw: pointer to hardware structure
1152 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1154 u16 phy_offset, control, eword, edata, block_crc;
1155 bool end_data = false;
1156 u16 list_offset, data_offset;
1158 s32 ret_val = IXGBE_SUCCESS;
1161 DEBUGFUNC("ixgbe_reset_phy_nl");
1163 /* Blocked by MNG FW so bail */
1164 if (ixgbe_check_reset_blocked(hw))
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1170 /* reset the PHY and poll for completion */
1171 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1172 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1173 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1175 for (i = 0; i < 100; i++) {
1176 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1177 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1178 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1183 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1184 DEBUGOUT("PHY reset did not complete.\n");
1185 ret_val = IXGBE_ERR_PHY;
1189 /* Get init offsets */
1190 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1192 if (ret_val != IXGBE_SUCCESS)
1195 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1199 * Read control word from PHY init contents offset
1201 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1204 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1205 IXGBE_CONTROL_SHIFT_NL;
1206 edata = eword & IXGBE_DATA_MASK_NL;
1208 case IXGBE_DELAY_NL:
1210 DEBUGOUT1("DELAY: %d MS\n", edata);
1214 DEBUGOUT("DATA:\n");
1216 ret_val = hw->eeprom.ops.read(hw, data_offset,
1221 for (i = 0; i < edata; i++) {
1222 ret_val = hw->eeprom.ops.read(hw, data_offset,
1226 hw->phy.ops.write_reg(hw, phy_offset,
1227 IXGBE_TWINAX_DEV, eword);
1228 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1234 case IXGBE_CONTROL_NL:
1236 DEBUGOUT("CONTROL:\n");
1237 if (edata == IXGBE_CONTROL_EOL_NL) {
1240 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1243 DEBUGOUT("Bad control value\n");
1244 ret_val = IXGBE_ERR_PHY;
1249 DEBUGOUT("Bad control type\n");
1250 ret_val = IXGBE_ERR_PHY;
1259 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1260 "eeprom read at offset %d failed", data_offset);
1261 return IXGBE_ERR_PHY;
1265 * ixgbe_identify_module_generic - Identifies module type
1266 * @hw: pointer to hardware structure
1268 * Determines HW type and calls appropriate function.
1270 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1272 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1274 DEBUGFUNC("ixgbe_identify_module_generic");
1276 switch (hw->mac.ops.get_media_type(hw)) {
1277 case ixgbe_media_type_fiber:
1278 status = ixgbe_identify_sfp_module_generic(hw);
1281 case ixgbe_media_type_fiber_qsfp:
1282 status = ixgbe_identify_qsfp_module_generic(hw);
1286 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1287 status = IXGBE_ERR_SFP_NOT_PRESENT;
1295 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1296 * @hw: pointer to hardware structure
1298 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1300 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1302 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1304 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1306 u8 comp_codes_1g = 0;
1307 u8 comp_codes_10g = 0;
1308 u8 oui_bytes[3] = {0, 0, 0};
1311 u16 enforce_sfp = 0;
1313 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1315 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1316 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1317 status = IXGBE_ERR_SFP_NOT_PRESENT;
1321 /* LAN ID is needed for I2C access */
1322 hw->mac.ops.set_lan_id(hw);
1324 status = hw->phy.ops.read_i2c_eeprom(hw,
1325 IXGBE_SFF_IDENTIFIER,
1328 if (status != IXGBE_SUCCESS)
1329 goto err_read_i2c_eeprom;
1331 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1332 hw->phy.type = ixgbe_phy_sfp_unsupported;
1333 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_1GBE_COMP_CODES,
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1342 status = hw->phy.ops.read_i2c_eeprom(hw,
1343 IXGBE_SFF_10GBE_COMP_CODES,
1346 if (status != IXGBE_SUCCESS)
1347 goto err_read_i2c_eeprom;
1348 status = hw->phy.ops.read_i2c_eeprom(hw,
1349 IXGBE_SFF_CABLE_TECHNOLOGY,
1352 if (status != IXGBE_SUCCESS)
1353 goto err_read_i2c_eeprom;
1360 * 3 SFP_DA_CORE0 - 82599-specific
1361 * 4 SFP_DA_CORE1 - 82599-specific
1362 * 5 SFP_SR/LR_CORE0 - 82599-specific
1363 * 6 SFP_SR/LR_CORE1 - 82599-specific
1364 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1365 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1366 * 9 SFP_1g_cu_CORE0 - 82599-specific
1367 * 10 SFP_1g_cu_CORE1 - 82599-specific
1368 * 11 SFP_1g_sx_CORE0 - 82599-specific
1369 * 12 SFP_1g_sx_CORE1 - 82599-specific
1371 if (hw->mac.type == ixgbe_mac_82598EB) {
1372 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1373 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1374 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1375 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1376 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1377 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1379 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1381 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1382 if (hw->bus.lan_id == 0)
1384 ixgbe_sfp_type_da_cu_core0;
1387 ixgbe_sfp_type_da_cu_core1;
1388 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1389 hw->phy.ops.read_i2c_eeprom(
1390 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1393 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1394 if (hw->bus.lan_id == 0)
1396 ixgbe_sfp_type_da_act_lmt_core0;
1399 ixgbe_sfp_type_da_act_lmt_core1;
1402 ixgbe_sfp_type_unknown;
1404 } else if (comp_codes_10g &
1405 (IXGBE_SFF_10GBASESR_CAPABLE |
1406 IXGBE_SFF_10GBASELR_CAPABLE)) {
1407 if (hw->bus.lan_id == 0)
1409 ixgbe_sfp_type_srlr_core0;
1412 ixgbe_sfp_type_srlr_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1416 ixgbe_sfp_type_1g_cu_core0;
1419 ixgbe_sfp_type_1g_cu_core1;
1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1421 if (hw->bus.lan_id == 0)
1423 ixgbe_sfp_type_1g_sx_core0;
1426 ixgbe_sfp_type_1g_sx_core1;
1427 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1428 if (hw->bus.lan_id == 0)
1430 ixgbe_sfp_type_1g_lx_core0;
1433 ixgbe_sfp_type_1g_lx_core1;
1435 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1439 if (hw->phy.sfp_type != stored_sfp_type)
1440 hw->phy.sfp_setup_needed = true;
1442 /* Determine if the SFP+ PHY is dual speed or not. */
1443 hw->phy.multispeed_fiber = false;
1444 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1445 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1446 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1447 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1448 hw->phy.multispeed_fiber = true;
1450 /* Determine PHY vendor */
1451 if (hw->phy.type != ixgbe_phy_nl) {
1452 hw->phy.id = identifier;
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE0,
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1460 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 IXGBE_SFF_VENDOR_OUI_BYTE1,
1464 if (status != IXGBE_SUCCESS)
1465 goto err_read_i2c_eeprom;
1467 status = hw->phy.ops.read_i2c_eeprom(hw,
1468 IXGBE_SFF_VENDOR_OUI_BYTE2,
1471 if (status != IXGBE_SUCCESS)
1472 goto err_read_i2c_eeprom;
1475 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1476 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1477 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1479 switch (vendor_oui) {
1480 case IXGBE_SFF_VENDOR_OUI_TYCO:
1481 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1483 ixgbe_phy_sfp_passive_tyco;
1485 case IXGBE_SFF_VENDOR_OUI_FTL:
1486 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1487 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1489 hw->phy.type = ixgbe_phy_sfp_ftl;
1491 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1492 hw->phy.type = ixgbe_phy_sfp_avago;
1494 case IXGBE_SFF_VENDOR_OUI_INTEL:
1495 hw->phy.type = ixgbe_phy_sfp_intel;
1498 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500 ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1503 ixgbe_phy_sfp_active_unknown;
1505 hw->phy.type = ixgbe_phy_sfp_unknown;
1510 /* Allow any DA cable vendor */
1511 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1512 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1513 status = IXGBE_SUCCESS;
1517 /* Verify supported 1G SFP modules */
1518 if (comp_codes_10g == 0 &&
1519 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1524 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1525 hw->phy.type = ixgbe_phy_sfp_unsupported;
1526 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1530 /* Anything else 82598-based is supported */
1531 if (hw->mac.type == ixgbe_mac_82598EB) {
1532 status = IXGBE_SUCCESS;
1536 ixgbe_get_device_caps(hw, &enforce_sfp);
1537 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1538 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1544 /* Make sure we're a supported PHY type */
1545 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1546 status = IXGBE_SUCCESS;
1548 if (hw->allow_unsupported_sfp == true) {
1550 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1551 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1552 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1553 status = IXGBE_SUCCESS;
1555 DEBUGOUT("SFP+ module not supported\n");
1557 ixgbe_phy_sfp_unsupported;
1558 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1562 status = IXGBE_SUCCESS;
1569 err_read_i2c_eeprom:
1570 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1571 if (hw->phy.type != ixgbe_phy_nl) {
1573 hw->phy.type = ixgbe_phy_unknown;
1575 return IXGBE_ERR_SFP_NOT_PRESENT;
1579 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1580 * @hw: pointer to hardware structure
1582 * Determines physical layer capabilities of the current SFP.
1584 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1586 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1587 u8 comp_codes_10g = 0;
1588 u8 comp_codes_1g = 0;
1590 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1592 hw->phy.ops.identify_sfp(hw);
1593 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1594 return physical_layer;
1596 switch (hw->phy.type) {
1597 case ixgbe_phy_sfp_passive_tyco:
1598 case ixgbe_phy_sfp_passive_unknown:
1599 case ixgbe_phy_qsfp_passive_unknown:
1600 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1602 case ixgbe_phy_sfp_ftl_active:
1603 case ixgbe_phy_sfp_active_unknown:
1604 case ixgbe_phy_qsfp_active_unknown:
1605 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1607 case ixgbe_phy_sfp_avago:
1608 case ixgbe_phy_sfp_ftl:
1609 case ixgbe_phy_sfp_intel:
1610 case ixgbe_phy_sfp_unknown:
1611 hw->phy.ops.read_i2c_eeprom(hw,
1612 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1613 hw->phy.ops.read_i2c_eeprom(hw,
1614 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1615 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1620 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1621 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1624 case ixgbe_phy_qsfp_intel:
1625 case ixgbe_phy_qsfp_unknown:
1626 hw->phy.ops.read_i2c_eeprom(hw,
1627 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1628 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1629 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1630 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1631 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1637 return physical_layer;
1641 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1642 * @hw: pointer to hardware structure
1644 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1646 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1648 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1650 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1652 u8 comp_codes_1g = 0;
1653 u8 comp_codes_10g = 0;
1654 u8 oui_bytes[3] = {0, 0, 0};
1655 u16 enforce_sfp = 0;
1657 u8 cable_length = 0;
1659 bool active_cable = false;
1661 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1663 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1664 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1665 status = IXGBE_ERR_SFP_NOT_PRESENT;
1669 /* LAN ID is needed for I2C access */
1670 hw->mac.ops.set_lan_id(hw);
1672 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1675 if (status != IXGBE_SUCCESS)
1676 goto err_read_i2c_eeprom;
1678 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1679 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1684 hw->phy.id = identifier;
1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1689 if (status != IXGBE_SUCCESS)
1690 goto err_read_i2c_eeprom;
1692 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1695 if (status != IXGBE_SUCCESS)
1696 goto err_read_i2c_eeprom;
1698 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1699 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1700 if (hw->bus.lan_id == 0)
1701 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1703 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1704 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1705 IXGBE_SFF_10GBASELR_CAPABLE)) {
1706 if (hw->bus.lan_id == 0)
1707 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1709 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1711 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1712 active_cable = true;
1714 if (!active_cable) {
1715 /* check for active DA cables that pre-date
1717 hw->phy.ops.read_i2c_eeprom(hw,
1718 IXGBE_SFF_QSFP_CONNECTOR,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1722 IXGBE_SFF_QSFP_CABLE_LENGTH,
1725 hw->phy.ops.read_i2c_eeprom(hw,
1726 IXGBE_SFF_QSFP_DEVICE_TECH,
1730 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1731 (cable_length > 0) &&
1732 ((device_tech >> 4) ==
1733 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1734 active_cable = true;
1738 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1739 if (hw->bus.lan_id == 0)
1741 ixgbe_sfp_type_da_act_lmt_core0;
1744 ixgbe_sfp_type_da_act_lmt_core1;
1746 /* unsupported module type */
1747 hw->phy.type = ixgbe_phy_sfp_unsupported;
1748 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1753 if (hw->phy.sfp_type != stored_sfp_type)
1754 hw->phy.sfp_setup_needed = true;
1756 /* Determine if the QSFP+ PHY is dual speed or not. */
1757 hw->phy.multispeed_fiber = false;
1758 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1759 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1760 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1761 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1762 hw->phy.multispeed_fiber = true;
1764 /* Determine PHY vendor for optical modules */
1765 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1766 IXGBE_SFF_10GBASELR_CAPABLE)) {
1767 status = hw->phy.ops.read_i2c_eeprom(hw,
1768 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1771 if (status != IXGBE_SUCCESS)
1772 goto err_read_i2c_eeprom;
1774 status = hw->phy.ops.read_i2c_eeprom(hw,
1775 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1778 if (status != IXGBE_SUCCESS)
1779 goto err_read_i2c_eeprom;
1781 status = hw->phy.ops.read_i2c_eeprom(hw,
1782 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1785 if (status != IXGBE_SUCCESS)
1786 goto err_read_i2c_eeprom;
1789 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1790 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1791 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1793 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1794 hw->phy.type = ixgbe_phy_qsfp_intel;
1796 hw->phy.type = ixgbe_phy_qsfp_unknown;
1798 ixgbe_get_device_caps(hw, &enforce_sfp);
1799 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1800 /* Make sure we're a supported PHY type */
1801 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1802 status = IXGBE_SUCCESS;
1804 if (hw->allow_unsupported_sfp == true) {
1806 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1807 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1808 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1809 status = IXGBE_SUCCESS;
1811 DEBUGOUT("QSFP module not supported\n");
1813 ixgbe_phy_sfp_unsupported;
1814 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1818 status = IXGBE_SUCCESS;
1825 err_read_i2c_eeprom:
1826 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1828 hw->phy.type = ixgbe_phy_unknown;
1830 return IXGBE_ERR_SFP_NOT_PRESENT;
1834 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1835 * @hw: pointer to hardware structure
1836 * @list_offset: offset to the SFP ID list
1837 * @data_offset: offset to the SFP data block
1839 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1840 * so it returns the offsets to the phy init sequence block.
1842 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1847 u16 sfp_type = hw->phy.sfp_type;
1849 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1851 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1854 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855 return IXGBE_ERR_SFP_NOT_PRESENT;
1857 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1858 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1859 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1862 * Limiting active cables and 1G Phys must be initialized as
1865 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1866 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1867 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1868 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1869 sfp_type = ixgbe_sfp_type_srlr_core0;
1870 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1871 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1872 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1873 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1874 sfp_type = ixgbe_sfp_type_srlr_core1;
1876 /* Read offset to PHY init contents */
1877 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1878 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1879 "eeprom read at offset %d failed",
1880 IXGBE_PHY_INIT_OFFSET_NL);
1881 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1884 if ((!*list_offset) || (*list_offset == 0xFFFF))
1885 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1887 /* Shift offset to first ID word */
1891 * Find the matching SFP ID in the EEPROM
1892 * and program the init sequence
1894 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1897 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1898 if (sfp_id == sfp_type) {
1900 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1902 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1903 DEBUGOUT("SFP+ module not supported\n");
1904 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1909 (*list_offset) += 2;
1910 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1915 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1916 DEBUGOUT("No matching SFP+ module found\n");
1917 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1920 return IXGBE_SUCCESS;
1923 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1924 "eeprom read at offset %d failed", *list_offset);
1925 return IXGBE_ERR_PHY;
1929 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1930 * @hw: pointer to hardware structure
1931 * @byte_offset: EEPROM byte offset to read
1932 * @eeprom_data: value read
1934 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1936 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1939 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1941 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942 IXGBE_I2C_EEPROM_DEV_ADDR,
1947 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: byte offset at address 0xA2
1950 * @sff8472_data: value read
1952 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1954 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1957 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1958 IXGBE_I2C_EEPROM_DEV_ADDR2,
1963 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1964 * @hw: pointer to hardware structure
1965 * @byte_offset: EEPROM byte offset to write
1966 * @eeprom_data: value to write
1968 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1970 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1973 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1975 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1976 IXGBE_I2C_EEPROM_DEV_ADDR,
1981 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1982 * @hw: pointer to hardware structure
1983 * @offset: eeprom offset to be read
1984 * @addr: I2C address to be read
1986 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1988 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1989 offset == IXGBE_SFF_IDENTIFIER &&
1990 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1996 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1997 * @hw: pointer to hardware structure
1998 * @byte_offset: byte offset to read
1999 * @dev_addr: address to read from
2001 * @lock: true if to take and release semaphore
2003 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2004 * a specified device address.
2006 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2007 u8 dev_addr, u8 *data, bool lock)
2012 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2016 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2018 if (hw->mac.type >= ixgbe_mac_X550)
2020 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2021 max_retry = IXGBE_SFP_DETECT_RETRIES;
2024 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2025 return IXGBE_ERR_SWFW_SYNC;
2027 ixgbe_i2c_start(hw);
2029 /* Device Address and write indication */
2030 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2031 if (status != IXGBE_SUCCESS)
2034 status = ixgbe_get_i2c_ack(hw);
2035 if (status != IXGBE_SUCCESS)
2038 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2039 if (status != IXGBE_SUCCESS)
2042 status = ixgbe_get_i2c_ack(hw);
2043 if (status != IXGBE_SUCCESS)
2046 ixgbe_i2c_start(hw);
2048 /* Device Address and read indication */
2049 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2050 if (status != IXGBE_SUCCESS)
2053 status = ixgbe_get_i2c_ack(hw);
2054 if (status != IXGBE_SUCCESS)
2057 status = ixgbe_clock_in_i2c_byte(hw, data);
2058 if (status != IXGBE_SUCCESS)
2061 status = ixgbe_clock_out_i2c_bit(hw, nack);
2062 if (status != IXGBE_SUCCESS)
2067 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2068 return IXGBE_SUCCESS;
2071 ixgbe_i2c_bus_clear(hw);
2073 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077 if (retry < max_retry)
2078 DEBUGOUT("I2C byte read error - Retrying.\n");
2080 DEBUGOUT("I2C byte read error.\n");
2082 } while (retry < max_retry);
2088 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2089 * @hw: pointer to hardware structure
2090 * @byte_offset: byte offset to read
2091 * @dev_addr: address to read from
2094 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2095 * a specified device address.
2097 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2098 u8 dev_addr, u8 *data)
2100 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2105 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2106 * @hw: pointer to hardware structure
2107 * @byte_offset: byte offset to read
2108 * @dev_addr: address to read from
2111 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2112 * a specified device address.
2114 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2115 u8 dev_addr, u8 *data)
2117 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2122 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2123 * @hw: pointer to hardware structure
2124 * @byte_offset: byte offset to write
2125 * @dev_addr: address to write to
2126 * @data: value to write
2127 * @lock: true if to take and release semaphore
2129 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2130 * a specified device address.
2132 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2133 u8 dev_addr, u8 data, bool lock)
2138 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2140 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2142 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2144 return IXGBE_ERR_SWFW_SYNC;
2147 ixgbe_i2c_start(hw);
2149 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2150 if (status != IXGBE_SUCCESS)
2153 status = ixgbe_get_i2c_ack(hw);
2154 if (status != IXGBE_SUCCESS)
2157 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2158 if (status != IXGBE_SUCCESS)
2161 status = ixgbe_get_i2c_ack(hw);
2162 if (status != IXGBE_SUCCESS)
2165 status = ixgbe_clock_out_i2c_byte(hw, data);
2166 if (status != IXGBE_SUCCESS)
2169 status = ixgbe_get_i2c_ack(hw);
2170 if (status != IXGBE_SUCCESS)
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176 return IXGBE_SUCCESS;
2179 ixgbe_i2c_bus_clear(hw);
2181 if (retry < max_retry)
2182 DEBUGOUT("I2C byte write error - Retrying.\n");
2184 DEBUGOUT("I2C byte write error.\n");
2185 } while (retry < max_retry);
2188 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2194 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2195 * @hw: pointer to hardware structure
2196 * @byte_offset: byte offset to write
2197 * @dev_addr: address to write to
2198 * @data: value to write
2200 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2201 * a specified device address.
2203 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2204 u8 dev_addr, u8 data)
2206 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2211 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2212 * @hw: pointer to hardware structure
2213 * @byte_offset: byte offset to write
2214 * @dev_addr: address to write to
2215 * @data: value to write
2217 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2218 * a specified device address.
2220 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2221 u8 dev_addr, u8 data)
2223 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2228 * ixgbe_i2c_start - Sets I2C start condition
2229 * @hw: pointer to hardware structure
2231 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2232 * Set bit-bang mode on X550 hardware.
2234 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2236 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2238 DEBUGFUNC("ixgbe_i2c_start");
2240 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2242 /* Start condition must begin with data and clock high */
2243 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2244 ixgbe_raise_i2c_clk(hw, &i2cctl);
2246 /* Setup time for start condition (4.7us) */
2247 usec_delay(IXGBE_I2C_T_SU_STA);
2249 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2251 /* Hold time for start condition (4us) */
2252 usec_delay(IXGBE_I2C_T_HD_STA);
2254 ixgbe_lower_i2c_clk(hw, &i2cctl);
2256 /* Minimum low period of clock is 4.7 us */
2257 usec_delay(IXGBE_I2C_T_LOW);
2262 * ixgbe_i2c_stop - Sets I2C stop condition
2263 * @hw: pointer to hardware structure
2265 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2266 * Disables bit-bang mode and negates data output enable on X550
2269 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2271 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2272 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2273 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2274 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2276 DEBUGFUNC("ixgbe_i2c_stop");
2278 /* Stop condition must begin with data low and clock high */
2279 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2280 ixgbe_raise_i2c_clk(hw, &i2cctl);
2282 /* Setup time for stop condition (4us) */
2283 usec_delay(IXGBE_I2C_T_SU_STO);
2285 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2287 /* bus free time between stop and start (4.7us)*/
2288 usec_delay(IXGBE_I2C_T_BUF);
2290 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2291 i2cctl &= ~bb_en_bit;
2292 i2cctl |= data_oe_bit | clk_oe_bit;
2293 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2294 IXGBE_WRITE_FLUSH(hw);
2299 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2300 * @hw: pointer to hardware structure
2301 * @data: data byte to clock in
2303 * Clocks in one byte data via I2C data/clock
2305 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2310 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2313 for (i = 7; i >= 0; i--) {
2314 ixgbe_clock_in_i2c_bit(hw, &bit);
2318 return IXGBE_SUCCESS;
2322 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2323 * @hw: pointer to hardware structure
2324 * @data: data byte clocked out
2326 * Clocks out one byte data via I2C data/clock
2328 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2330 s32 status = IXGBE_SUCCESS;
2335 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2337 for (i = 7; i >= 0; i--) {
2338 bit = (data >> i) & 0x1;
2339 status = ixgbe_clock_out_i2c_bit(hw, bit);
2341 if (status != IXGBE_SUCCESS)
2345 /* Release SDA line (set high) */
2346 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2347 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2348 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2349 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2350 IXGBE_WRITE_FLUSH(hw);
2356 * ixgbe_get_i2c_ack - Polls for I2C ACK
2357 * @hw: pointer to hardware structure
2359 * Clocks in/out one bit via I2C data/clock
2361 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2363 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2364 s32 status = IXGBE_SUCCESS;
2366 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2370 DEBUGFUNC("ixgbe_get_i2c_ack");
2373 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2374 i2cctl |= data_oe_bit;
2375 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2376 IXGBE_WRITE_FLUSH(hw);
2378 ixgbe_raise_i2c_clk(hw, &i2cctl);
2380 /* Minimum high period of clock is 4us */
2381 usec_delay(IXGBE_I2C_T_HIGH);
2383 /* Poll for ACK. Note that ACK in I2C spec is
2384 * transition from 1 to 0 */
2385 for (i = 0; i < timeout; i++) {
2386 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2387 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2395 DEBUGOUT("I2C ack was not received.\n");
2396 status = IXGBE_ERR_I2C;
2399 ixgbe_lower_i2c_clk(hw, &i2cctl);
2401 /* Minimum low period of clock is 4.7 us */
2402 usec_delay(IXGBE_I2C_T_LOW);
2408 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2409 * @hw: pointer to hardware structure
2410 * @data: read data value
2412 * Clocks in one bit via I2C data/clock
2414 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2416 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2417 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2419 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2422 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2423 i2cctl |= data_oe_bit;
2424 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2425 IXGBE_WRITE_FLUSH(hw);
2427 ixgbe_raise_i2c_clk(hw, &i2cctl);
2429 /* Minimum high period of clock is 4us */
2430 usec_delay(IXGBE_I2C_T_HIGH);
2432 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2433 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2435 ixgbe_lower_i2c_clk(hw, &i2cctl);
2437 /* Minimum low period of clock is 4.7 us */
2438 usec_delay(IXGBE_I2C_T_LOW);
2440 return IXGBE_SUCCESS;
2444 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2445 * @hw: pointer to hardware structure
2446 * @data: data value to write
2448 * Clocks out one bit via I2C data/clock
2450 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2453 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2455 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2457 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2458 if (status == IXGBE_SUCCESS) {
2459 ixgbe_raise_i2c_clk(hw, &i2cctl);
2461 /* Minimum high period of clock is 4us */
2462 usec_delay(IXGBE_I2C_T_HIGH);
2464 ixgbe_lower_i2c_clk(hw, &i2cctl);
2466 /* Minimum low period of clock is 4.7 us.
2467 * This also takes care of the data hold time.
2469 usec_delay(IXGBE_I2C_T_LOW);
2471 status = IXGBE_ERR_I2C;
2472 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2473 "I2C data was not set to %X\n", data);
2480 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2481 * @hw: pointer to hardware structure
2482 * @i2cctl: Current value of I2CCTL register
2484 * Raises the I2C clock line '0'->'1'
2485 * Negates the I2C clock output enable on X550 hardware.
2487 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2489 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2491 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2494 DEBUGFUNC("ixgbe_raise_i2c_clk");
2497 *i2cctl |= clk_oe_bit;
2498 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2501 for (i = 0; i < timeout; i++) {
2502 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2504 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2505 IXGBE_WRITE_FLUSH(hw);
2506 /* SCL rise time (1000ns) */
2507 usec_delay(IXGBE_I2C_T_RISE);
2509 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2510 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2516 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2517 * @hw: pointer to hardware structure
2518 * @i2cctl: Current value of I2CCTL register
2520 * Lowers the I2C clock line '1'->'0'
2521 * Asserts the I2C clock output enable on X550 hardware.
2523 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2525 DEBUGFUNC("ixgbe_lower_i2c_clk");
2527 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2528 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2530 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2531 IXGBE_WRITE_FLUSH(hw);
2533 /* SCL fall time (300ns) */
2534 usec_delay(IXGBE_I2C_T_FALL);
2538 * ixgbe_set_i2c_data - Sets the I2C data bit
2539 * @hw: pointer to hardware structure
2540 * @i2cctl: Current value of I2CCTL register
2541 * @data: I2C data value (0 or 1) to set
2543 * Sets the I2C data bit
2544 * Asserts the I2C data output enable on X550 hardware.
2546 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2548 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2549 s32 status = IXGBE_SUCCESS;
2551 DEBUGFUNC("ixgbe_set_i2c_data");
2554 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2556 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2557 *i2cctl &= ~data_oe_bit;
2559 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2560 IXGBE_WRITE_FLUSH(hw);
2562 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2563 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2565 if (!data) /* Can't verify data in this case */
2566 return IXGBE_SUCCESS;
2568 *i2cctl |= data_oe_bit;
2569 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2570 IXGBE_WRITE_FLUSH(hw);
2573 /* Verify data was set correctly */
2574 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2575 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2576 status = IXGBE_ERR_I2C;
2577 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2578 "Error - I2C data was not set to %X.\n",
2586 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2587 * @hw: pointer to hardware structure
2588 * @i2cctl: Current value of I2CCTL register
2590 * Returns the I2C data bit value
2591 * Negates the I2C data output enable on X550 hardware.
2593 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2595 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2597 UNREFERENCED_1PARAMETER(hw);
2599 DEBUGFUNC("ixgbe_get_i2c_data");
2602 *i2cctl |= data_oe_bit;
2603 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2604 IXGBE_WRITE_FLUSH(hw);
2605 usec_delay(IXGBE_I2C_T_FALL);
2608 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2617 * ixgbe_i2c_bus_clear - Clears the I2C bus
2618 * @hw: pointer to hardware structure
2620 * Clears the I2C bus by sending nine clock pulses.
2621 * Used when data line is stuck low.
2623 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2628 DEBUGFUNC("ixgbe_i2c_bus_clear");
2630 ixgbe_i2c_start(hw);
2631 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2633 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2635 for (i = 0; i < 9; i++) {
2636 ixgbe_raise_i2c_clk(hw, &i2cctl);
2638 /* Min high period of clock is 4us */
2639 usec_delay(IXGBE_I2C_T_HIGH);
2641 ixgbe_lower_i2c_clk(hw, &i2cctl);
2643 /* Min low period of clock is 4.7us*/
2644 usec_delay(IXGBE_I2C_T_LOW);
2647 ixgbe_i2c_start(hw);
2649 /* Put the i2c bus back to default state */
2654 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2655 * @hw: pointer to hardware structure
2657 * Checks if the LASI temp alarm status was triggered due to overtemp
2659 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2661 s32 status = IXGBE_SUCCESS;
2664 DEBUGFUNC("ixgbe_tn_check_overtemp");
2666 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2669 /* Check that the LASI temp alarm status was triggered */
2670 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2671 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2673 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2676 status = IXGBE_ERR_OVERTEMP;
2677 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2683 * ixgbe_set_copper_phy_power - Control power for copper phy
2684 * @hw: pointer to hardware structure
2685 * @on: true for on, false for off
2687 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2692 if (!on && ixgbe_mng_present(hw))
2695 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2696 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2702 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2704 if (ixgbe_check_reset_blocked(hw))
2706 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2709 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,