1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
110 * Returns an error code on error.
112 STATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
113 u16 reg, u16 *val, bool lock)
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
124 if (hw->mac.type >= ixgbe_mac_X550)
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, false))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to read from
186 * @reg: I2C device register to read from
187 * @val: pointer to location to receive read value
189 * Returns an error code on error.
191 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
194 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
198 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
199 * @hw: pointer to the hardware structure
200 * @addr: I2C bus address to read from
201 * @reg: I2C device register to read from
202 * @val: pointer to location to receive read value
204 * Returns an error code on error.
207 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
210 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
214 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
215 * @hw: pointer to the hardware structure
216 * @addr: I2C bus address to write to
217 * @reg: I2C device register to write to
218 * @val: value to write
219 * @lock: true if to take and release semaphore
221 * Returns an error code on error.
223 STATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
224 u16 reg, u16 val, bool lock)
226 u32 swfw_mask = hw->phy.phy_semaphore_mask;
232 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
233 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
234 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
235 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
238 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
239 return IXGBE_ERR_SWFW_SYNC;
241 /* Device Address and write indication */
242 if (ixgbe_out_i2c_byte_ack(hw, addr))
244 /* Write bits 14:8 */
245 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
248 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
250 /* Write data 15:8 */
251 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
254 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
257 if (ixgbe_out_i2c_byte_ack(hw, csum))
261 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
265 ixgbe_i2c_bus_clear(hw);
267 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
269 if (retry < max_retry)
270 DEBUGOUT("I2C byte write combined error - Retrying.\n");
272 DEBUGOUT("I2C byte write combined error.\n");
273 } while (retry < max_retry);
275 return IXGBE_ERR_I2C;
279 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
280 * @hw: pointer to the hardware structure
281 * @addr: I2C bus address to write to
282 * @reg: I2C device register to write to
283 * @val: value to write
285 * Returns an error code on error.
287 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
288 u8 addr, u16 reg, u16 val)
290 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
294 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
295 * @hw: pointer to the hardware structure
296 * @addr: I2C bus address to write to
297 * @reg: I2C device register to write to
298 * @val: value to write
300 * Returns an error code on error.
303 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
304 u8 addr, u16 reg, u16 val)
306 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
310 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
311 * @hw: pointer to the hardware structure
313 * Initialize the function pointers.
315 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
317 struct ixgbe_phy_info *phy = &hw->phy;
319 DEBUGFUNC("ixgbe_init_phy_ops_generic");
322 phy->ops.identify = ixgbe_identify_phy_generic;
323 phy->ops.reset = ixgbe_reset_phy_generic;
324 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
325 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
326 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
327 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
328 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
329 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
330 phy->ops.check_link = NULL;
331 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
332 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
333 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
334 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
335 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
336 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
337 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
338 phy->ops.identify_sfp = ixgbe_identify_module_generic;
339 phy->sfp_type = ixgbe_sfp_type_unknown;
340 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
341 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
342 phy->ops.read_i2c_combined_unlocked =
343 ixgbe_read_i2c_combined_generic_unlocked;
344 phy->ops.write_i2c_combined_unlocked =
345 ixgbe_write_i2c_combined_generic_unlocked;
346 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
347 phy->ops.write_i2c_byte_unlocked =
348 ixgbe_write_i2c_byte_generic_unlocked;
349 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
350 return IXGBE_SUCCESS;
354 * ixgbe_identify_phy_generic - Get physical layer module
355 * @hw: pointer to hardware structure
357 * Determines the physical layer module found on the current adapter.
359 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
361 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
365 DEBUGFUNC("ixgbe_identify_phy_generic");
367 if (!hw->phy.phy_semaphore_mask) {
369 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
371 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
374 if (hw->phy.type == ixgbe_phy_unknown) {
375 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
376 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
377 hw->phy.addr = phy_addr;
378 ixgbe_get_phy_id(hw);
380 ixgbe_get_phy_type_from_id(hw->phy.id);
382 if (hw->phy.type == ixgbe_phy_unknown) {
383 hw->phy.ops.read_reg(hw,
384 IXGBE_MDIO_PHY_EXT_ABILITY,
385 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
388 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
389 IXGBE_MDIO_PHY_1000BASET_ABILITY))
391 ixgbe_phy_cu_unknown;
397 status = IXGBE_SUCCESS;
402 /* Certain media types do not have a phy so an address will not
403 * be found and the code will take this path. Caller has to
404 * decide if it is an error or not.
406 if (status != IXGBE_SUCCESS) {
410 status = IXGBE_SUCCESS;
417 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
418 * @hw: pointer to the hardware structure
420 * This function checks the MMNGC.MNG_VETO bit to see if there are
421 * any constraints on link from manageability. For MAC's that don't
422 * have this bit just return faluse since the link can not be blocked
425 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
429 DEBUGFUNC("ixgbe_check_reset_blocked");
431 /* If we don't have this bit, it can't be blocking */
432 if (hw->mac.type == ixgbe_mac_82598EB)
435 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
436 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
437 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
438 "MNG_VETO bit detected.\n");
446 * ixgbe_validate_phy_addr - Determines phy address is valid
447 * @hw: pointer to hardware structure
450 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
455 DEBUGFUNC("ixgbe_validate_phy_addr");
457 hw->phy.addr = phy_addr;
458 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
459 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
461 if (phy_id != 0xFFFF && phy_id != 0x0)
468 * ixgbe_get_phy_id - Get the phy type
469 * @hw: pointer to hardware structure
472 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
478 DEBUGFUNC("ixgbe_get_phy_id");
480 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
481 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
484 if (status == IXGBE_SUCCESS) {
485 hw->phy.id = (u32)(phy_id_high << 16);
486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
487 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
489 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
490 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
496 * ixgbe_get_phy_type_from_id - Get the phy type
497 * @hw: pointer to hardware structure
500 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
502 enum ixgbe_phy_type phy_type;
504 DEBUGFUNC("ixgbe_get_phy_type_from_id");
508 phy_type = ixgbe_phy_tn;
514 phy_type = ixgbe_phy_aq;
517 phy_type = ixgbe_phy_qt;
520 phy_type = ixgbe_phy_nl;
523 phy_type = ixgbe_phy_x550em_ext_t;
526 phy_type = ixgbe_phy_unknown;
530 DEBUGOUT1("phy type found is %d\n", phy_type);
535 * ixgbe_reset_phy_generic - Performs a PHY reset
536 * @hw: pointer to hardware structure
538 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
542 s32 status = IXGBE_SUCCESS;
544 DEBUGFUNC("ixgbe_reset_phy_generic");
546 if (hw->phy.type == ixgbe_phy_unknown)
547 status = ixgbe_identify_phy_generic(hw);
549 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
552 /* Don't reset PHY if it's shut down due to overtemp. */
553 if (!hw->phy.reset_if_overtemp &&
554 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
557 /* Blocked by MNG FW so bail */
558 if (ixgbe_check_reset_blocked(hw))
562 * Perform soft PHY reset to the PHY_XS.
563 * This will cause a soft reset to the PHY
565 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
566 IXGBE_MDIO_PHY_XS_DEV_TYPE,
567 IXGBE_MDIO_PHY_XS_RESET);
570 * Poll for reset bit to self-clear indicating reset is complete.
571 * Some PHYs could take up to 3 seconds to complete and need about
572 * 1.7 usec delay after the reset is complete.
574 for (i = 0; i < 30; i++) {
576 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
577 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
578 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
584 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
585 status = IXGBE_ERR_RESET_FAILED;
586 ERROR_REPORT1(IXGBE_ERROR_POLLING,
587 "PHY reset polling failed to complete.\n");
595 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
597 * @hw: pointer to hardware structure
598 * @reg_addr: 32 bit address of PHY register to read
599 * @phy_data: Pointer to read data from PHY register
601 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
604 u32 i, data, command;
606 /* Setup and write the address cycle command */
607 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
608 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
609 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
610 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
612 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
615 * Check every 10 usec to see if the address cycle completed.
616 * The MDI Command bit will clear when the operation is
619 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
622 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
623 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
628 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
629 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
630 return IXGBE_ERR_PHY;
634 * Address cycle complete, setup and write the read
637 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
638 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
639 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
640 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
642 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
645 * Check every 10 usec to see if the address cycle
646 * completed. The MDI Command bit will clear when the
647 * operation is complete
649 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
652 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
653 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
657 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
658 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
659 return IXGBE_ERR_PHY;
663 * Read operation is complete. Get the data
666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
668 *phy_data = (u16)(data);
670 return IXGBE_SUCCESS;
674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
675 * using the SWFW lock - this function is needed in most cases
676 * @hw: pointer to hardware structure
677 * @reg_addr: 32 bit address of PHY register to read
678 * @phy_data: Pointer to read data from PHY register
680 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
681 u32 device_type, u16 *phy_data)
684 u32 gssr = hw->phy.phy_semaphore_mask;
686 DEBUGFUNC("ixgbe_read_phy_reg_generic");
688 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
689 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
691 hw->mac.ops.release_swfw_sync(hw, gssr);
693 status = IXGBE_ERR_SWFW_SYNC;
700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
702 * @hw: pointer to hardware structure
703 * @reg_addr: 32 bit PHY register to write
704 * @device_type: 5 bit device type
705 * @phy_data: Data to write to the PHY register
707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
708 u32 device_type, u16 phy_data)
712 /* Put the data in the MDI single read and write data register*/
713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
715 /* Setup and write the address cycle command */
716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
724 * Check every 10 usec to see if the address cycle completed.
725 * The MDI Command bit will clear when the operation is
728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
731 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
738 return IXGBE_ERR_PHY;
742 * Address cycle complete, setup and write the write
745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
753 * Check every 10 usec to see if the address cycle
754 * completed. The MDI Command bit will clear when the
755 * operation is complete
757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
760 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
767 return IXGBE_ERR_PHY;
770 return IXGBE_SUCCESS;
774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
775 * using SWFW lock- this function is needed in most cases
776 * @hw: pointer to hardware structure
777 * @reg_addr: 32 bit PHY register to write
778 * @device_type: 5 bit device type
779 * @phy_data: Data to write to the PHY register
781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
782 u32 device_type, u16 phy_data)
785 u32 gssr = hw->phy.phy_semaphore_mask;
787 DEBUGFUNC("ixgbe_write_phy_reg_generic");
789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
790 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
792 hw->mac.ops.release_swfw_sync(hw, gssr);
794 status = IXGBE_ERR_SWFW_SYNC;
801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
802 * @hw: pointer to hardware structure
804 * Restart auto-negotiation and PHY and waits for completion.
806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
808 s32 status = IXGBE_SUCCESS;
809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
810 bool autoneg = false;
811 ixgbe_link_speed speed;
813 DEBUGFUNC("ixgbe_setup_phy_link_generic");
815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
817 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
818 /* Set or unset auto-negotiation 10G advertisement */
819 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
823 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
824 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
832 if (hw->mac.type == ixgbe_mac_X550) {
833 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
834 /* Set or unset auto-negotiation 5G advertisement */
835 hw->phy.ops.read_reg(hw,
836 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
837 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
840 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
841 if (hw->phy.autoneg_advertised &
842 IXGBE_LINK_SPEED_5GB_FULL)
843 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
845 hw->phy.ops.write_reg(hw,
846 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
851 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
852 /* Set or unset auto-negotiation 2.5G advertisement */
853 hw->phy.ops.read_reg(hw,
854 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
858 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
859 if (hw->phy.autoneg_advertised &
860 IXGBE_LINK_SPEED_2_5GB_FULL)
861 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
863 hw->phy.ops.write_reg(hw,
864 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
865 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
870 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
871 /* Set or unset auto-negotiation 1G advertisement */
872 hw->phy.ops.read_reg(hw,
873 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
874 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
877 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
878 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
879 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
881 hw->phy.ops.write_reg(hw,
882 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
883 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
887 if (speed & IXGBE_LINK_SPEED_100_FULL) {
888 /* Set or unset auto-negotiation 100M advertisement */
889 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
890 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
893 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
894 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
895 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
896 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
898 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
903 /* Blocked by MNG FW so don't reset PHY */
904 if (ixgbe_check_reset_blocked(hw))
907 /* Restart PHY auto-negotiation. */
908 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
909 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
911 autoneg_reg |= IXGBE_MII_RESTART;
913 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
914 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
920 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
921 * @hw: pointer to hardware structure
922 * @speed: new link speed
924 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
925 ixgbe_link_speed speed,
926 bool autoneg_wait_to_complete)
928 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
930 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
933 * Clear autoneg_advertised and set new values based on input link
936 hw->phy.autoneg_advertised = 0;
938 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
939 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
941 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
942 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
944 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
945 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
947 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
948 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
950 if (speed & IXGBE_LINK_SPEED_100_FULL)
951 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
953 /* Setup link based on the new speed settings */
954 hw->phy.ops.setup_link(hw);
956 return IXGBE_SUCCESS;
960 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
961 * @hw: pointer to hardware structure
962 * @speed: pointer to link speed
963 * @autoneg: boolean auto-negotiation value
965 * Determines the supported link capabilities by reading the PHY auto
966 * negotiation register.
968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
969 ixgbe_link_speed *speed,
975 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
980 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
981 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
984 if (status == IXGBE_SUCCESS) {
985 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
986 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
987 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
988 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
989 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
990 *speed |= IXGBE_LINK_SPEED_100_FULL;
993 /* Internal PHY does not support 100 Mbps */
994 if (hw->mac.type == ixgbe_mac_X550EM_x)
995 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
997 if (hw->mac.type == ixgbe_mac_X550) {
998 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
999 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
1006 * ixgbe_check_phy_link_tnx - Determine link and speed status
1007 * @hw: pointer to hardware structure
1009 * Reads the VS1 register to determine if link is up and the current speed for
1012 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1015 s32 status = IXGBE_SUCCESS;
1017 u32 max_time_out = 10;
1022 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1024 /* Initialize speed and link to default case */
1026 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1029 * Check current speed and link status of the PHY register.
1030 * This is a vendor specific register and may have to
1031 * be changed for other copper PHYs.
1033 for (time_out = 0; time_out < max_time_out; time_out++) {
1035 status = hw->phy.ops.read_reg(hw,
1036 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1037 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1039 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1040 phy_speed = phy_data &
1041 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1042 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1045 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1046 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1055 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1056 * @hw: pointer to hardware structure
1058 * Restart auto-negotiation and PHY and waits for completion.
1060 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1062 s32 status = IXGBE_SUCCESS;
1063 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1064 bool autoneg = false;
1065 ixgbe_link_speed speed;
1067 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1069 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1071 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1072 /* Set or unset auto-negotiation 10G advertisement */
1073 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1074 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1077 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1078 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1079 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1081 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1086 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1087 /* Set or unset auto-negotiation 1G advertisement */
1088 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1089 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1092 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1093 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1094 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1096 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1097 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1101 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1102 /* Set or unset auto-negotiation 100M advertisement */
1103 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1104 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1107 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1108 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1109 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1111 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1112 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1116 /* Blocked by MNG FW so don't reset PHY */
1117 if (ixgbe_check_reset_blocked(hw))
1120 /* Restart PHY auto-negotiation. */
1121 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1122 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1124 autoneg_reg |= IXGBE_MII_RESTART;
1126 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1127 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1133 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1134 * @hw: pointer to hardware structure
1135 * @firmware_version: pointer to the PHY Firmware Version
1137 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1138 u16 *firmware_version)
1142 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1144 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1145 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1152 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1153 * @hw: pointer to hardware structure
1154 * @firmware_version: pointer to the PHY Firmware Version
1156 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1157 u16 *firmware_version)
1161 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1163 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1164 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1171 * ixgbe_reset_phy_nl - Performs a PHY reset
1172 * @hw: pointer to hardware structure
1174 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1176 u16 phy_offset, control, eword, edata, block_crc;
1177 bool end_data = false;
1178 u16 list_offset, data_offset;
1180 s32 ret_val = IXGBE_SUCCESS;
1183 DEBUGFUNC("ixgbe_reset_phy_nl");
1185 /* Blocked by MNG FW so bail */
1186 if (ixgbe_check_reset_blocked(hw))
1189 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1190 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1192 /* reset the PHY and poll for completion */
1193 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1194 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1195 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1197 for (i = 0; i < 100; i++) {
1198 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1199 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1200 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1205 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1206 DEBUGOUT("PHY reset did not complete.\n");
1207 ret_val = IXGBE_ERR_PHY;
1211 /* Get init offsets */
1212 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1214 if (ret_val != IXGBE_SUCCESS)
1217 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1221 * Read control word from PHY init contents offset
1223 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1226 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1227 IXGBE_CONTROL_SHIFT_NL;
1228 edata = eword & IXGBE_DATA_MASK_NL;
1230 case IXGBE_DELAY_NL:
1232 DEBUGOUT1("DELAY: %d MS\n", edata);
1236 DEBUGOUT("DATA:\n");
1238 ret_val = hw->eeprom.ops.read(hw, data_offset,
1243 for (i = 0; i < edata; i++) {
1244 ret_val = hw->eeprom.ops.read(hw, data_offset,
1248 hw->phy.ops.write_reg(hw, phy_offset,
1249 IXGBE_TWINAX_DEV, eword);
1250 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1256 case IXGBE_CONTROL_NL:
1258 DEBUGOUT("CONTROL:\n");
1259 if (edata == IXGBE_CONTROL_EOL_NL) {
1262 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1265 DEBUGOUT("Bad control value\n");
1266 ret_val = IXGBE_ERR_PHY;
1271 DEBUGOUT("Bad control type\n");
1272 ret_val = IXGBE_ERR_PHY;
1281 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1282 "eeprom read at offset %d failed", data_offset);
1283 return IXGBE_ERR_PHY;
1287 * ixgbe_identify_module_generic - Identifies module type
1288 * @hw: pointer to hardware structure
1290 * Determines HW type and calls appropriate function.
1292 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1294 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1296 DEBUGFUNC("ixgbe_identify_module_generic");
1298 switch (hw->mac.ops.get_media_type(hw)) {
1299 case ixgbe_media_type_fiber:
1300 status = ixgbe_identify_sfp_module_generic(hw);
1303 case ixgbe_media_type_fiber_qsfp:
1304 status = ixgbe_identify_qsfp_module_generic(hw);
1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1309 status = IXGBE_ERR_SFP_NOT_PRESENT;
1317 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1318 * @hw: pointer to hardware structure
1320 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1322 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1326 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1328 u8 comp_codes_1g = 0;
1329 u8 comp_codes_10g = 0;
1330 u8 oui_bytes[3] = {0, 0, 0};
1333 u16 enforce_sfp = 0;
1335 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1337 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1338 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1339 status = IXGBE_ERR_SFP_NOT_PRESENT;
1343 /* LAN ID is needed for I2C access */
1344 hw->mac.ops.set_lan_id(hw);
1346 status = hw->phy.ops.read_i2c_eeprom(hw,
1347 IXGBE_SFF_IDENTIFIER,
1350 if (status != IXGBE_SUCCESS)
1351 goto err_read_i2c_eeprom;
1353 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1354 hw->phy.type = ixgbe_phy_sfp_unsupported;
1355 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1357 status = hw->phy.ops.read_i2c_eeprom(hw,
1358 IXGBE_SFF_1GBE_COMP_CODES,
1361 if (status != IXGBE_SUCCESS)
1362 goto err_read_i2c_eeprom;
1364 status = hw->phy.ops.read_i2c_eeprom(hw,
1365 IXGBE_SFF_10GBE_COMP_CODES,
1368 if (status != IXGBE_SUCCESS)
1369 goto err_read_i2c_eeprom;
1370 status = hw->phy.ops.read_i2c_eeprom(hw,
1371 IXGBE_SFF_CABLE_TECHNOLOGY,
1374 if (status != IXGBE_SUCCESS)
1375 goto err_read_i2c_eeprom;
1382 * 3 SFP_DA_CORE0 - 82599-specific
1383 * 4 SFP_DA_CORE1 - 82599-specific
1384 * 5 SFP_SR/LR_CORE0 - 82599-specific
1385 * 6 SFP_SR/LR_CORE1 - 82599-specific
1386 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1387 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1388 * 9 SFP_1g_cu_CORE0 - 82599-specific
1389 * 10 SFP_1g_cu_CORE1 - 82599-specific
1390 * 11 SFP_1g_sx_CORE0 - 82599-specific
1391 * 12 SFP_1g_sx_CORE1 - 82599-specific
1393 if (hw->mac.type == ixgbe_mac_82598EB) {
1394 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1395 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1396 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1397 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1398 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1399 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1401 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1403 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1404 if (hw->bus.lan_id == 0)
1406 ixgbe_sfp_type_da_cu_core0;
1409 ixgbe_sfp_type_da_cu_core1;
1410 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1411 hw->phy.ops.read_i2c_eeprom(
1412 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1415 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1416 if (hw->bus.lan_id == 0)
1418 ixgbe_sfp_type_da_act_lmt_core0;
1421 ixgbe_sfp_type_da_act_lmt_core1;
1424 ixgbe_sfp_type_unknown;
1426 } else if (comp_codes_10g &
1427 (IXGBE_SFF_10GBASESR_CAPABLE |
1428 IXGBE_SFF_10GBASELR_CAPABLE)) {
1429 if (hw->bus.lan_id == 0)
1431 ixgbe_sfp_type_srlr_core0;
1434 ixgbe_sfp_type_srlr_core1;
1435 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1436 if (hw->bus.lan_id == 0)
1438 ixgbe_sfp_type_1g_cu_core0;
1441 ixgbe_sfp_type_1g_cu_core1;
1442 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1443 if (hw->bus.lan_id == 0)
1445 ixgbe_sfp_type_1g_sx_core0;
1448 ixgbe_sfp_type_1g_sx_core1;
1449 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1450 if (hw->bus.lan_id == 0)
1452 ixgbe_sfp_type_1g_lx_core0;
1455 ixgbe_sfp_type_1g_lx_core1;
1457 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1461 if (hw->phy.sfp_type != stored_sfp_type)
1462 hw->phy.sfp_setup_needed = true;
1464 /* Determine if the SFP+ PHY is dual speed or not. */
1465 hw->phy.multispeed_fiber = false;
1466 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1467 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1468 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1469 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1470 hw->phy.multispeed_fiber = true;
1472 /* Determine PHY vendor */
1473 if (hw->phy.type != ixgbe_phy_nl) {
1474 hw->phy.id = identifier;
1475 status = hw->phy.ops.read_i2c_eeprom(hw,
1476 IXGBE_SFF_VENDOR_OUI_BYTE0,
1479 if (status != IXGBE_SUCCESS)
1480 goto err_read_i2c_eeprom;
1482 status = hw->phy.ops.read_i2c_eeprom(hw,
1483 IXGBE_SFF_VENDOR_OUI_BYTE1,
1486 if (status != IXGBE_SUCCESS)
1487 goto err_read_i2c_eeprom;
1489 status = hw->phy.ops.read_i2c_eeprom(hw,
1490 IXGBE_SFF_VENDOR_OUI_BYTE2,
1493 if (status != IXGBE_SUCCESS)
1494 goto err_read_i2c_eeprom;
1497 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1498 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1499 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1501 switch (vendor_oui) {
1502 case IXGBE_SFF_VENDOR_OUI_TYCO:
1503 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1505 ixgbe_phy_sfp_passive_tyco;
1507 case IXGBE_SFF_VENDOR_OUI_FTL:
1508 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1509 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1511 hw->phy.type = ixgbe_phy_sfp_ftl;
1513 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1514 hw->phy.type = ixgbe_phy_sfp_avago;
1516 case IXGBE_SFF_VENDOR_OUI_INTEL:
1517 hw->phy.type = ixgbe_phy_sfp_intel;
1520 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1522 ixgbe_phy_sfp_passive_unknown;
1523 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1525 ixgbe_phy_sfp_active_unknown;
1527 hw->phy.type = ixgbe_phy_sfp_unknown;
1532 /* Allow any DA cable vendor */
1533 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1534 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1535 status = IXGBE_SUCCESS;
1539 /* Verify supported 1G SFP modules */
1540 if (comp_codes_10g == 0 &&
1541 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1545 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1546 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1547 hw->phy.type = ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552 /* Anything else 82598-based is supported */
1553 if (hw->mac.type == ixgbe_mac_82598EB) {
1554 status = IXGBE_SUCCESS;
1558 ixgbe_get_device_caps(hw, &enforce_sfp);
1559 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1560 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1564 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1565 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1566 /* Make sure we're a supported PHY type */
1567 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1568 status = IXGBE_SUCCESS;
1570 if (hw->allow_unsupported_sfp == true) {
1571 EWARN(hw, "WARNING: Intel (R) Network "
1572 "Connections are quality tested "
1573 "using Intel (R) Ethernet Optics."
1574 " Using untested modules is not "
1575 "supported and may cause unstable"
1576 " operation or damage to the "
1577 "module or the adapter. Intel "
1578 "Corporation is not responsible "
1579 "for any harm caused by using "
1580 "untested modules.\n", status);
1581 status = IXGBE_SUCCESS;
1583 DEBUGOUT("SFP+ module not supported\n");
1585 ixgbe_phy_sfp_unsupported;
1586 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1590 status = IXGBE_SUCCESS;
1597 err_read_i2c_eeprom:
1598 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1599 if (hw->phy.type != ixgbe_phy_nl) {
1601 hw->phy.type = ixgbe_phy_unknown;
1603 return IXGBE_ERR_SFP_NOT_PRESENT;
1607 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1608 * @hw: pointer to hardware structure
1610 * Determines physical layer capabilities of the current SFP.
1612 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1614 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1615 u8 comp_codes_10g = 0;
1616 u8 comp_codes_1g = 0;
1618 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1620 hw->phy.ops.identify_sfp(hw);
1621 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1622 return physical_layer;
1624 switch (hw->phy.type) {
1625 case ixgbe_phy_sfp_passive_tyco:
1626 case ixgbe_phy_sfp_passive_unknown:
1627 case ixgbe_phy_qsfp_passive_unknown:
1628 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1630 case ixgbe_phy_sfp_ftl_active:
1631 case ixgbe_phy_sfp_active_unknown:
1632 case ixgbe_phy_qsfp_active_unknown:
1633 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1635 case ixgbe_phy_sfp_avago:
1636 case ixgbe_phy_sfp_ftl:
1637 case ixgbe_phy_sfp_intel:
1638 case ixgbe_phy_sfp_unknown:
1639 hw->phy.ops.read_i2c_eeprom(hw,
1640 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1641 hw->phy.ops.read_i2c_eeprom(hw,
1642 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1643 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1644 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1645 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1646 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1647 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1648 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1649 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1650 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1652 case ixgbe_phy_qsfp_intel:
1653 case ixgbe_phy_qsfp_unknown:
1654 hw->phy.ops.read_i2c_eeprom(hw,
1655 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1656 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1657 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1658 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1659 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1665 return physical_layer;
1669 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1670 * @hw: pointer to hardware structure
1672 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1674 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1676 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1678 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1680 u8 comp_codes_1g = 0;
1681 u8 comp_codes_10g = 0;
1682 u8 oui_bytes[3] = {0, 0, 0};
1683 u16 enforce_sfp = 0;
1685 u8 cable_length = 0;
1687 bool active_cable = false;
1689 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1691 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1692 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1693 status = IXGBE_ERR_SFP_NOT_PRESENT;
1697 /* LAN ID is needed for I2C access */
1698 hw->mac.ops.set_lan_id(hw);
1700 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1703 if (status != IXGBE_SUCCESS)
1704 goto err_read_i2c_eeprom;
1706 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1707 hw->phy.type = ixgbe_phy_sfp_unsupported;
1708 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1712 hw->phy.id = identifier;
1714 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1717 if (status != IXGBE_SUCCESS)
1718 goto err_read_i2c_eeprom;
1720 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1723 if (status != IXGBE_SUCCESS)
1724 goto err_read_i2c_eeprom;
1726 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1727 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1728 if (hw->bus.lan_id == 0)
1729 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1731 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1732 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1733 IXGBE_SFF_10GBASELR_CAPABLE)) {
1734 if (hw->bus.lan_id == 0)
1735 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1737 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1739 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1740 active_cable = true;
1742 if (!active_cable) {
1743 /* check for active DA cables that pre-date
1745 hw->phy.ops.read_i2c_eeprom(hw,
1746 IXGBE_SFF_QSFP_CONNECTOR,
1749 hw->phy.ops.read_i2c_eeprom(hw,
1750 IXGBE_SFF_QSFP_CABLE_LENGTH,
1753 hw->phy.ops.read_i2c_eeprom(hw,
1754 IXGBE_SFF_QSFP_DEVICE_TECH,
1758 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1759 (cable_length > 0) &&
1760 ((device_tech >> 4) ==
1761 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1762 active_cable = true;
1766 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1767 if (hw->bus.lan_id == 0)
1769 ixgbe_sfp_type_da_act_lmt_core0;
1772 ixgbe_sfp_type_da_act_lmt_core1;
1774 /* unsupported module type */
1775 hw->phy.type = ixgbe_phy_sfp_unsupported;
1776 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1781 if (hw->phy.sfp_type != stored_sfp_type)
1782 hw->phy.sfp_setup_needed = true;
1784 /* Determine if the QSFP+ PHY is dual speed or not. */
1785 hw->phy.multispeed_fiber = false;
1786 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1787 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1788 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1789 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1790 hw->phy.multispeed_fiber = true;
1792 /* Determine PHY vendor for optical modules */
1793 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1794 IXGBE_SFF_10GBASELR_CAPABLE)) {
1795 status = hw->phy.ops.read_i2c_eeprom(hw,
1796 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1799 if (status != IXGBE_SUCCESS)
1800 goto err_read_i2c_eeprom;
1802 status = hw->phy.ops.read_i2c_eeprom(hw,
1803 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1806 if (status != IXGBE_SUCCESS)
1807 goto err_read_i2c_eeprom;
1809 status = hw->phy.ops.read_i2c_eeprom(hw,
1810 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1813 if (status != IXGBE_SUCCESS)
1814 goto err_read_i2c_eeprom;
1817 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1818 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1819 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1821 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1822 hw->phy.type = ixgbe_phy_qsfp_intel;
1824 hw->phy.type = ixgbe_phy_qsfp_unknown;
1826 ixgbe_get_device_caps(hw, &enforce_sfp);
1827 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1828 /* Make sure we're a supported PHY type */
1829 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1830 status = IXGBE_SUCCESS;
1832 if (hw->allow_unsupported_sfp == true) {
1833 EWARN(hw, "WARNING: Intel (R) Network "
1834 "Connections are quality tested "
1835 "using Intel (R) Ethernet Optics."
1836 " Using untested modules is not "
1837 "supported and may cause unstable"
1838 " operation or damage to the "
1839 "module or the adapter. Intel "
1840 "Corporation is not responsible "
1841 "for any harm caused by using "
1842 "untested modules.\n", status);
1843 status = IXGBE_SUCCESS;
1845 DEBUGOUT("QSFP module not supported\n");
1847 ixgbe_phy_sfp_unsupported;
1848 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1852 status = IXGBE_SUCCESS;
1859 err_read_i2c_eeprom:
1860 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1862 hw->phy.type = ixgbe_phy_unknown;
1864 return IXGBE_ERR_SFP_NOT_PRESENT;
1869 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1870 * @hw: pointer to hardware structure
1871 * @list_offset: offset to the SFP ID list
1872 * @data_offset: offset to the SFP data block
1874 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1875 * so it returns the offsets to the phy init sequence block.
1877 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1882 u16 sfp_type = hw->phy.sfp_type;
1884 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1886 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1887 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1889 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1890 return IXGBE_ERR_SFP_NOT_PRESENT;
1892 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1893 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1894 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1897 * Limiting active cables and 1G Phys must be initialized as
1900 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1901 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1902 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1903 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1904 sfp_type = ixgbe_sfp_type_srlr_core0;
1905 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1906 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1907 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1908 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1909 sfp_type = ixgbe_sfp_type_srlr_core1;
1911 /* Read offset to PHY init contents */
1912 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1914 "eeprom read at offset %d failed",
1915 IXGBE_PHY_INIT_OFFSET_NL);
1916 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1919 if ((!*list_offset) || (*list_offset == 0xFFFF))
1920 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1922 /* Shift offset to first ID word */
1926 * Find the matching SFP ID in the EEPROM
1927 * and program the init sequence
1929 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1932 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1933 if (sfp_id == sfp_type) {
1935 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1937 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1938 DEBUGOUT("SFP+ module not supported\n");
1939 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1944 (*list_offset) += 2;
1945 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1950 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1951 DEBUGOUT("No matching SFP+ module found\n");
1952 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1955 return IXGBE_SUCCESS;
1958 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1959 "eeprom read at offset %d failed", *list_offset);
1960 return IXGBE_ERR_PHY;
1964 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1965 * @hw: pointer to hardware structure
1966 * @byte_offset: EEPROM byte offset to read
1967 * @eeprom_data: value read
1969 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1971 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1974 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1976 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1977 IXGBE_I2C_EEPROM_DEV_ADDR,
1982 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1983 * @hw: pointer to hardware structure
1984 * @byte_offset: byte offset at address 0xA2
1985 * @eeprom_data: value read
1987 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1989 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1992 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1993 IXGBE_I2C_EEPROM_DEV_ADDR2,
1998 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1999 * @hw: pointer to hardware structure
2000 * @byte_offset: EEPROM byte offset to write
2001 * @eeprom_data: value to write
2003 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2005 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2008 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2010 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2011 IXGBE_I2C_EEPROM_DEV_ADDR,
2016 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2017 * @hw: pointer to hardware structure
2018 * @offset: eeprom offset to be read
2019 * @addr: I2C address to be read
2021 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2023 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2024 offset == IXGBE_SFF_IDENTIFIER &&
2025 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2031 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2032 * @hw: pointer to hardware structure
2033 * @byte_offset: byte offset to read
2035 * @lock: true if to take and release semaphore
2037 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2038 * a specified device address.
2040 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2041 u8 dev_addr, u8 *data, bool lock)
2046 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2050 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2052 if (hw->mac.type >= ixgbe_mac_X550)
2054 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2055 max_retry = IXGBE_SFP_DETECT_RETRIES;
2058 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2059 return IXGBE_ERR_SWFW_SYNC;
2061 ixgbe_i2c_start(hw);
2063 /* Device Address and write indication */
2064 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2065 if (status != IXGBE_SUCCESS)
2068 status = ixgbe_get_i2c_ack(hw);
2069 if (status != IXGBE_SUCCESS)
2072 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2073 if (status != IXGBE_SUCCESS)
2076 status = ixgbe_get_i2c_ack(hw);
2077 if (status != IXGBE_SUCCESS)
2080 ixgbe_i2c_start(hw);
2082 /* Device Address and read indication */
2083 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2084 if (status != IXGBE_SUCCESS)
2087 status = ixgbe_get_i2c_ack(hw);
2088 if (status != IXGBE_SUCCESS)
2091 status = ixgbe_clock_in_i2c_byte(hw, data);
2092 if (status != IXGBE_SUCCESS)
2095 status = ixgbe_clock_out_i2c_bit(hw, nack);
2096 if (status != IXGBE_SUCCESS)
2101 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2102 return IXGBE_SUCCESS;
2105 ixgbe_i2c_bus_clear(hw);
2107 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2111 if (retry < max_retry)
2112 DEBUGOUT("I2C byte read error - Retrying.\n");
2114 DEBUGOUT("I2C byte read error.\n");
2116 } while (retry < max_retry);
2122 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2123 * @hw: pointer to hardware structure
2124 * @byte_offset: byte offset to read
2127 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2128 * a specified device address.
2130 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2131 u8 dev_addr, u8 *data)
2133 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2138 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2139 * @hw: pointer to hardware structure
2140 * @byte_offset: byte offset to read
2143 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2144 * a specified device address.
2146 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2147 u8 dev_addr, u8 *data)
2149 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2154 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2155 * @hw: pointer to hardware structure
2156 * @byte_offset: byte offset to write
2157 * @data: value to write
2158 * @lock: true if to take and release semaphore
2160 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2161 * a specified device address.
2163 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2164 u8 dev_addr, u8 data, bool lock)
2169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2171 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2173 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2175 return IXGBE_ERR_SWFW_SYNC;
2178 ixgbe_i2c_start(hw);
2180 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2181 if (status != IXGBE_SUCCESS)
2184 status = ixgbe_get_i2c_ack(hw);
2185 if (status != IXGBE_SUCCESS)
2188 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2189 if (status != IXGBE_SUCCESS)
2192 status = ixgbe_get_i2c_ack(hw);
2193 if (status != IXGBE_SUCCESS)
2196 status = ixgbe_clock_out_i2c_byte(hw, data);
2197 if (status != IXGBE_SUCCESS)
2200 status = ixgbe_get_i2c_ack(hw);
2201 if (status != IXGBE_SUCCESS)
2206 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2207 return IXGBE_SUCCESS;
2210 ixgbe_i2c_bus_clear(hw);
2212 if (retry < max_retry)
2213 DEBUGOUT("I2C byte write error - Retrying.\n");
2215 DEBUGOUT("I2C byte write error.\n");
2216 } while (retry < max_retry);
2219 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2225 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2226 * @hw: pointer to hardware structure
2227 * @byte_offset: byte offset to write
2228 * @data: value to write
2230 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2231 * a specified device address.
2233 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2234 u8 dev_addr, u8 data)
2236 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2241 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2242 * @hw: pointer to hardware structure
2243 * @byte_offset: byte offset to write
2244 * @data: value to write
2246 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2247 * a specified device address.
2249 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2250 u8 dev_addr, u8 data)
2252 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2257 * ixgbe_i2c_start - Sets I2C start condition
2258 * @hw: pointer to hardware structure
2260 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2261 * Set bit-bang mode on X550 hardware.
2263 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2265 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2267 DEBUGFUNC("ixgbe_i2c_start");
2269 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2271 /* Start condition must begin with data and clock high */
2272 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2273 ixgbe_raise_i2c_clk(hw, &i2cctl);
2275 /* Setup time for start condition (4.7us) */
2276 usec_delay(IXGBE_I2C_T_SU_STA);
2278 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2280 /* Hold time for start condition (4us) */
2281 usec_delay(IXGBE_I2C_T_HD_STA);
2283 ixgbe_lower_i2c_clk(hw, &i2cctl);
2285 /* Minimum low period of clock is 4.7 us */
2286 usec_delay(IXGBE_I2C_T_LOW);
2291 * ixgbe_i2c_stop - Sets I2C stop condition
2292 * @hw: pointer to hardware structure
2294 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2295 * Disables bit-bang mode and negates data output enable on X550
2298 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2300 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2301 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2302 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2303 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2305 DEBUGFUNC("ixgbe_i2c_stop");
2307 /* Stop condition must begin with data low and clock high */
2308 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2309 ixgbe_raise_i2c_clk(hw, &i2cctl);
2311 /* Setup time for stop condition (4us) */
2312 usec_delay(IXGBE_I2C_T_SU_STO);
2314 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2316 /* bus free time between stop and start (4.7us)*/
2317 usec_delay(IXGBE_I2C_T_BUF);
2319 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2320 i2cctl &= ~bb_en_bit;
2321 i2cctl |= data_oe_bit | clk_oe_bit;
2322 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2323 IXGBE_WRITE_FLUSH(hw);
2328 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2329 * @hw: pointer to hardware structure
2330 * @data: data byte to clock in
2332 * Clocks in one byte data via I2C data/clock
2334 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2339 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2342 for (i = 7; i >= 0; i--) {
2343 ixgbe_clock_in_i2c_bit(hw, &bit);
2347 return IXGBE_SUCCESS;
2351 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2352 * @hw: pointer to hardware structure
2353 * @data: data byte clocked out
2355 * Clocks out one byte data via I2C data/clock
2357 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2359 s32 status = IXGBE_SUCCESS;
2364 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2366 for (i = 7; i >= 0; i--) {
2367 bit = (data >> i) & 0x1;
2368 status = ixgbe_clock_out_i2c_bit(hw, bit);
2370 if (status != IXGBE_SUCCESS)
2374 /* Release SDA line (set high) */
2375 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2376 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2377 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2378 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2379 IXGBE_WRITE_FLUSH(hw);
2385 * ixgbe_get_i2c_ack - Polls for I2C ACK
2386 * @hw: pointer to hardware structure
2388 * Clocks in/out one bit via I2C data/clock
2390 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2392 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2393 s32 status = IXGBE_SUCCESS;
2395 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2399 DEBUGFUNC("ixgbe_get_i2c_ack");
2402 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2403 i2cctl |= data_oe_bit;
2404 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2405 IXGBE_WRITE_FLUSH(hw);
2407 ixgbe_raise_i2c_clk(hw, &i2cctl);
2409 /* Minimum high period of clock is 4us */
2410 usec_delay(IXGBE_I2C_T_HIGH);
2412 /* Poll for ACK. Note that ACK in I2C spec is
2413 * transition from 1 to 0 */
2414 for (i = 0; i < timeout; i++) {
2415 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2416 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2424 DEBUGOUT("I2C ack was not received.\n");
2425 status = IXGBE_ERR_I2C;
2428 ixgbe_lower_i2c_clk(hw, &i2cctl);
2430 /* Minimum low period of clock is 4.7 us */
2431 usec_delay(IXGBE_I2C_T_LOW);
2437 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2438 * @hw: pointer to hardware structure
2439 * @data: read data value
2441 * Clocks in one bit via I2C data/clock
2443 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2445 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2446 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2448 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2451 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2452 i2cctl |= data_oe_bit;
2453 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2454 IXGBE_WRITE_FLUSH(hw);
2456 ixgbe_raise_i2c_clk(hw, &i2cctl);
2458 /* Minimum high period of clock is 4us */
2459 usec_delay(IXGBE_I2C_T_HIGH);
2461 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2462 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2464 ixgbe_lower_i2c_clk(hw, &i2cctl);
2466 /* Minimum low period of clock is 4.7 us */
2467 usec_delay(IXGBE_I2C_T_LOW);
2469 return IXGBE_SUCCESS;
2473 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2474 * @hw: pointer to hardware structure
2475 * @data: data value to write
2477 * Clocks out one bit via I2C data/clock
2479 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2482 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2484 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2486 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2487 if (status == IXGBE_SUCCESS) {
2488 ixgbe_raise_i2c_clk(hw, &i2cctl);
2490 /* Minimum high period of clock is 4us */
2491 usec_delay(IXGBE_I2C_T_HIGH);
2493 ixgbe_lower_i2c_clk(hw, &i2cctl);
2495 /* Minimum low period of clock is 4.7 us.
2496 * This also takes care of the data hold time.
2498 usec_delay(IXGBE_I2C_T_LOW);
2500 status = IXGBE_ERR_I2C;
2501 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2502 "I2C data was not set to %X\n", data);
2509 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2510 * @hw: pointer to hardware structure
2511 * @i2cctl: Current value of I2CCTL register
2513 * Raises the I2C clock line '0'->'1'
2514 * Negates the I2C clock output enable on X550 hardware.
2516 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2518 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2520 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2523 DEBUGFUNC("ixgbe_raise_i2c_clk");
2526 *i2cctl |= clk_oe_bit;
2527 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2530 for (i = 0; i < timeout; i++) {
2531 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2533 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2534 IXGBE_WRITE_FLUSH(hw);
2535 /* SCL rise time (1000ns) */
2536 usec_delay(IXGBE_I2C_T_RISE);
2538 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2539 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2545 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2546 * @hw: pointer to hardware structure
2547 * @i2cctl: Current value of I2CCTL register
2549 * Lowers the I2C clock line '1'->'0'
2550 * Asserts the I2C clock output enable on X550 hardware.
2552 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2554 DEBUGFUNC("ixgbe_lower_i2c_clk");
2556 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2557 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2559 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2560 IXGBE_WRITE_FLUSH(hw);
2562 /* SCL fall time (300ns) */
2563 usec_delay(IXGBE_I2C_T_FALL);
2567 * ixgbe_set_i2c_data - Sets the I2C data bit
2568 * @hw: pointer to hardware structure
2569 * @i2cctl: Current value of I2CCTL register
2570 * @data: I2C data value (0 or 1) to set
2572 * Sets the I2C data bit
2573 * Asserts the I2C data output enable on X550 hardware.
2575 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2577 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2578 s32 status = IXGBE_SUCCESS;
2580 DEBUGFUNC("ixgbe_set_i2c_data");
2583 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2585 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2586 *i2cctl &= ~data_oe_bit;
2588 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2589 IXGBE_WRITE_FLUSH(hw);
2591 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2592 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2594 if (!data) /* Can't verify data in this case */
2595 return IXGBE_SUCCESS;
2597 *i2cctl |= data_oe_bit;
2598 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2599 IXGBE_WRITE_FLUSH(hw);
2602 /* Verify data was set correctly */
2603 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2604 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2605 status = IXGBE_ERR_I2C;
2606 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2607 "Error - I2C data was not set to %X.\n",
2615 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2616 * @hw: pointer to hardware structure
2617 * @i2cctl: Current value of I2CCTL register
2619 * Returns the I2C data bit value
2620 * Negates the I2C data output enable on X550 hardware.
2622 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2624 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2627 DEBUGFUNC("ixgbe_get_i2c_data");
2630 *i2cctl |= data_oe_bit;
2631 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2632 IXGBE_WRITE_FLUSH(hw);
2633 usec_delay(IXGBE_I2C_T_FALL);
2636 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2645 * ixgbe_i2c_bus_clear - Clears the I2C bus
2646 * @hw: pointer to hardware structure
2648 * Clears the I2C bus by sending nine clock pulses.
2649 * Used when data line is stuck low.
2651 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2656 DEBUGFUNC("ixgbe_i2c_bus_clear");
2658 ixgbe_i2c_start(hw);
2659 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2661 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2663 for (i = 0; i < 9; i++) {
2664 ixgbe_raise_i2c_clk(hw, &i2cctl);
2666 /* Min high period of clock is 4us */
2667 usec_delay(IXGBE_I2C_T_HIGH);
2669 ixgbe_lower_i2c_clk(hw, &i2cctl);
2671 /* Min low period of clock is 4.7us*/
2672 usec_delay(IXGBE_I2C_T_LOW);
2675 ixgbe_i2c_start(hw);
2677 /* Put the i2c bus back to default state */
2682 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2683 * @hw: pointer to hardware structure
2685 * Checks if the LASI temp alarm status was triggered due to overtemp
2687 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2689 s32 status = IXGBE_SUCCESS;
2692 DEBUGFUNC("ixgbe_tn_check_overtemp");
2694 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2697 /* Check that the LASI temp alarm status was triggered */
2698 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2699 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2701 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2704 status = IXGBE_ERR_OVERTEMP;
2705 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2711 * ixgbe_set_copper_phy_power - Control power for copper phy
2712 * @hw: pointer to hardware structure
2713 * @on: true for on, false for off
2715 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2720 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2721 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2727 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2729 if (ixgbe_check_reset_blocked(hw))
2731 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2734 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2735 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,