1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
53 * @hw: pointer to hardware structure
55 * Initialize the function pointers and assign the MAC type for X540.
56 * Does not touch the hardware.
58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
61 struct ixgbe_phy_info *phy = &hw->phy;
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 DEBUGFUNC("ixgbe_init_ops_X540");
67 ret_val = ixgbe_init_phy_ops_generic(hw);
68 ret_val = ixgbe_init_ops_generic(hw);
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
73 eeprom->ops.read = ixgbe_read_eerd_X540;
74 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
75 eeprom->ops.write = ixgbe_write_eewr_X540;
76 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
79 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
82 phy->ops.init = ixgbe_init_phy_ops_generic;
83 phy->ops.reset = NULL;
84 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
87 mac->ops.reset_hw = ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
102 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
103 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
104 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
106 /* RAR, Multicast, VLAN */
107 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
108 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
109 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
110 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
111 mac->rar_highwater = 1;
112 mac->ops.set_vfta = ixgbe_set_vfta_generic;
113 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
114 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
115 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
116 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
117 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
120 mac->ops.get_link_capabilities =
121 ixgbe_get_copper_link_capabilities_generic;
122 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
123 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
124 mac->ops.check_link = ixgbe_check_mac_link_generic;
127 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
128 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
129 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
130 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
131 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
132 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
137 * ARC supported; valid only if manageability features are
140 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
141 & IXGBE_FWSM_MODE_MASK);
143 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
146 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
147 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
149 /* Manageability interface */
150 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
152 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
158 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
159 * @hw: pointer to hardware structure
160 * @speed: pointer to link speed
161 * @autoneg: true when autoneg or autotry is enabled
163 * Determines the link capabilities by reading the AUTOC register.
165 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
166 ixgbe_link_speed *speed,
169 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
171 return IXGBE_SUCCESS;
175 * ixgbe_get_media_type_X540 - Get media type
176 * @hw: pointer to hardware structure
178 * Returns the media type (fiber, copper, backplane)
180 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
182 UNREFERENCED_1PARAMETER(hw);
183 return ixgbe_media_type_copper;
187 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
188 * @hw: pointer to hardware structure
189 * @speed: new link speed
190 * @autoneg_wait_to_complete: true when waiting for completion is needed
192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
193 ixgbe_link_speed speed,
194 bool autoneg_wait_to_complete)
196 DEBUGFUNC("ixgbe_setup_mac_link_X540");
197 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
201 * ixgbe_reset_hw_X540 - Perform hardware reset
202 * @hw: pointer to hardware structure
204 * Resets the hardware by resetting the transmit and receive units, masks
205 * and clears all interrupts, and perform a reset.
207 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
211 u32 swfw_mask = hw->phy.phy_semaphore_mask;
213 DEBUGFUNC("ixgbe_reset_hw_X540");
215 /* Call adapter stop to disable tx/rx and clear interrupts */
216 status = hw->mac.ops.stop_adapter(hw);
217 if (status != IXGBE_SUCCESS)
220 /* flush pending Tx transactions */
221 ixgbe_clear_tx_pending(hw);
224 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
225 if (status != IXGBE_SUCCESS) {
226 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
227 "semaphore failed with %d", status);
228 return IXGBE_ERR_SWFW_SYNC;
230 ctrl = IXGBE_CTRL_RST;
231 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
232 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
233 IXGBE_WRITE_FLUSH(hw);
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
236 /* Poll for reset bit to self-clear indicating reset is complete */
237 for (i = 0; i < 10; i++) {
239 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
240 if (!(ctrl & IXGBE_CTRL_RST_MASK))
244 if (ctrl & IXGBE_CTRL_RST_MASK) {
245 status = IXGBE_ERR_RESET_FAILED;
246 ERROR_REPORT1(IXGBE_ERROR_POLLING,
247 "Reset polling failed to complete.\n");
252 * Double resets are required for recovery from certain error
253 * conditions. Between resets, it is necessary to stall to allow time
254 * for any pending HW events to complete.
256 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
257 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
261 /* Set the Rx packet buffer size. */
262 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
264 /* Store the permanent mac address */
265 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
268 * Store MAC address from RAR0, clear receive address registers, and
269 * clear the multicast table. Also reset num_rar_entries to 128,
270 * since we modify this value when programming the SAN MAC address.
272 hw->mac.num_rar_entries = 128;
273 hw->mac.ops.init_rx_addrs(hw);
275 /* Store the permanent SAN mac address */
276 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
278 /* Add the SAN MAC address to the RAR only if it's a valid address */
279 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
280 /* Save the SAN MAC RAR index */
281 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
283 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
284 hw->mac.san_addr, 0, IXGBE_RAH_AV);
286 /* clear VMDq pool/queue selection for this RAR */
287 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
288 IXGBE_CLEAR_VMDQ_ALL);
290 /* Reserve the last RAR for the SAN MAC address */
291 hw->mac.num_rar_entries--;
294 /* Store the alternative WWNN/WWPN prefix */
295 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
296 &hw->mac.wwpn_prefix);
303 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
304 * @hw: pointer to hardware structure
306 * Starts the hardware using the generic start_hw function
307 * and the generation start_hw function.
308 * Then performs revision-specific operations, if any.
310 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
312 s32 ret_val = IXGBE_SUCCESS;
314 DEBUGFUNC("ixgbe_start_hw_X540");
316 ret_val = ixgbe_start_hw_generic(hw);
317 if (ret_val != IXGBE_SUCCESS)
320 ret_val = ixgbe_start_hw_gen2(hw);
327 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
328 * @hw: pointer to hardware structure
330 * Determines physical layer capabilities of the current configuration.
332 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
334 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
337 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
339 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
340 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
341 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
342 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
343 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
344 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
345 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
346 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
348 return physical_layer;
352 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
353 * @hw: pointer to hardware structure
355 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
356 * ixgbe_hw struct in order to set up EEPROM access.
358 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
360 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
364 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
366 if (eeprom->type == ixgbe_eeprom_uninitialized) {
367 eeprom->semaphore_delay = 10;
368 eeprom->type = ixgbe_flash;
370 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
371 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
372 IXGBE_EEC_SIZE_SHIFT);
373 eeprom->word_size = 1 << (eeprom_size +
374 IXGBE_EEPROM_WORD_SIZE_SHIFT);
376 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
377 eeprom->type, eeprom->word_size);
380 return IXGBE_SUCCESS;
384 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
385 * @hw: pointer to hardware structure
386 * @offset: offset of word in the EEPROM to read
387 * @data: word read from the EEPROM
389 * Reads a 16 bit word from the EEPROM using the EERD register.
391 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
393 s32 status = IXGBE_SUCCESS;
395 DEBUGFUNC("ixgbe_read_eerd_X540");
396 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
398 status = ixgbe_read_eerd_generic(hw, offset, data);
399 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
401 status = IXGBE_ERR_SWFW_SYNC;
408 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
409 * @hw: pointer to hardware structure
410 * @offset: offset of word in the EEPROM to read
411 * @words: number of words
412 * @data: word(s) read from the EEPROM
414 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
416 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
417 u16 offset, u16 words, u16 *data)
419 s32 status = IXGBE_SUCCESS;
421 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
422 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
424 status = ixgbe_read_eerd_buffer_generic(hw, offset,
426 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
428 status = IXGBE_ERR_SWFW_SYNC;
435 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
436 * @hw: pointer to hardware structure
437 * @offset: offset of word in the EEPROM to write
438 * @data: word write to the EEPROM
440 * Write a 16 bit word to the EEPROM using the EEWR register.
442 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
444 s32 status = IXGBE_SUCCESS;
446 DEBUGFUNC("ixgbe_write_eewr_X540");
447 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
449 status = ixgbe_write_eewr_generic(hw, offset, data);
450 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
452 status = IXGBE_ERR_SWFW_SYNC;
459 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
460 * @hw: pointer to hardware structure
461 * @offset: offset of word in the EEPROM to write
462 * @words: number of words
463 * @data: word(s) write to the EEPROM
465 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
467 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
468 u16 offset, u16 words, u16 *data)
470 s32 status = IXGBE_SUCCESS;
472 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
473 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
475 status = ixgbe_write_eewr_buffer_generic(hw, offset,
477 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
479 status = IXGBE_ERR_SWFW_SYNC;
486 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
488 * This function does not use synchronization for EERD and EEWR. It can
489 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
491 * @hw: pointer to hardware structure
493 * Returns a negative error code on error, or the 16-bit checksum
495 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
502 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
504 /* Do not use hw->eeprom.ops.read because we do not want to take
505 * the synchronization semaphores here. Instead use
506 * ixgbe_read_eerd_generic
509 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
511 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
514 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
515 if (ixgbe_read_eerd_generic(hw, i, &word)) {
516 DEBUGOUT("EEPROM read failed\n");
517 return IXGBE_ERR_EEPROM;
522 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
523 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
525 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
526 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
529 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
530 DEBUGOUT("EEPROM read failed\n");
531 return IXGBE_ERR_EEPROM;
534 /* Skip pointer section if the pointer is invalid. */
535 if (pointer == 0xFFFF || pointer == 0 ||
536 pointer >= hw->eeprom.word_size)
539 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
540 DEBUGOUT("EEPROM read failed\n");
541 return IXGBE_ERR_EEPROM;
544 /* Skip pointer section if length is invalid. */
545 if (length == 0xFFFF || length == 0 ||
546 (pointer + length) >= hw->eeprom.word_size)
549 for (j = pointer + 1; j <= pointer + length; j++) {
550 if (ixgbe_read_eerd_generic(hw, j, &word)) {
551 DEBUGOUT("EEPROM read failed\n");
552 return IXGBE_ERR_EEPROM;
558 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
560 return (s32)checksum;
564 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
565 * @hw: pointer to hardware structure
566 * @checksum_val: calculated checksum
568 * Performs checksum calculation and validates the EEPROM checksum. If the
569 * caller does not need checksum_val, the value can be NULL.
571 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
576 u16 read_checksum = 0;
578 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
580 /* Read the first word from the EEPROM. If this times out or fails, do
581 * not continue or we could be in for a very long wait while every
584 status = hw->eeprom.ops.read(hw, 0, &checksum);
586 DEBUGOUT("EEPROM read failed\n");
590 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
591 return IXGBE_ERR_SWFW_SYNC;
593 status = hw->eeprom.ops.calc_checksum(hw);
597 checksum = (u16)(status & 0xffff);
599 /* Do not use hw->eeprom.ops.read because we do not want to take
600 * the synchronization semaphores twice here.
602 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
607 /* Verify read checksum from EEPROM is the same as
608 * calculated checksum
610 if (read_checksum != checksum) {
611 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
612 "Invalid EEPROM checksum");
613 status = IXGBE_ERR_EEPROM_CHECKSUM;
616 /* If the user cares, return the calculated checksum */
618 *checksum_val = checksum;
621 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
627 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
628 * @hw: pointer to hardware structure
630 * After writing EEPROM to shadow RAM using EEWR register, software calculates
631 * checksum and updates the EEPROM and instructs the hardware to update
634 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
639 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
641 /* Read the first word from the EEPROM. If this times out or fails, do
642 * not continue or we could be in for a very long wait while every
645 status = hw->eeprom.ops.read(hw, 0, &checksum);
647 DEBUGOUT("EEPROM read failed\n");
651 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
652 return IXGBE_ERR_SWFW_SYNC;
654 status = hw->eeprom.ops.calc_checksum(hw);
658 checksum = (u16)(status & 0xffff);
660 /* Do not use hw->eeprom.ops.write because we do not want to
661 * take the synchronization semaphores twice here.
663 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
667 status = ixgbe_update_flash_X540(hw);
670 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
676 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
677 * @hw: pointer to hardware structure
679 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
680 * EEPROM from shadow RAM to the flash device.
682 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
687 DEBUGFUNC("ixgbe_update_flash_X540");
689 status = ixgbe_poll_flash_update_done_X540(hw);
690 if (status == IXGBE_ERR_EEPROM) {
691 DEBUGOUT("Flash update time out\n");
695 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
696 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
698 status = ixgbe_poll_flash_update_done_X540(hw);
699 if (status == IXGBE_SUCCESS)
700 DEBUGOUT("Flash update complete\n");
702 DEBUGOUT("Flash update time out\n");
704 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
705 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
707 if (flup & IXGBE_EEC_SEC1VAL) {
708 flup |= IXGBE_EEC_FLUP;
709 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
712 status = ixgbe_poll_flash_update_done_X540(hw);
713 if (status == IXGBE_SUCCESS)
714 DEBUGOUT("Flash update complete\n");
716 DEBUGOUT("Flash update time out\n");
723 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
724 * @hw: pointer to hardware structure
726 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
727 * flash update is done.
729 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
733 s32 status = IXGBE_ERR_EEPROM;
735 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
737 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
738 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
739 if (reg & IXGBE_EEC_FLUDONE) {
740 status = IXGBE_SUCCESS;
746 if (i == IXGBE_FLUDONE_ATTEMPTS)
747 ERROR_REPORT1(IXGBE_ERROR_POLLING,
748 "Flash update status polling timed out");
754 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
755 * @hw: pointer to hardware structure
756 * @mask: Mask to specify which semaphore to acquire
758 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
759 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
761 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
763 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
764 u32 fwmask = swmask << 5;
765 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
771 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
773 if (swmask & IXGBE_GSSR_EEP_SM)
774 hwmask |= IXGBE_GSSR_FLASH_SM;
776 /* SW only mask doesn't have FW bit pair */
777 if (mask & IXGBE_GSSR_SW_MNG_SM)
778 swmask |= IXGBE_GSSR_SW_MNG_SM;
780 swmask |= swi2c_mask;
781 fwmask |= swi2c_mask << 2;
782 if (hw->mac.type >= ixgbe_mac_X550)
785 for (i = 0; i < timeout; i++) {
786 /* SW NVM semaphore bit is used for access to all
787 * SW_FW_SYNC bits (not just NVM)
789 if (ixgbe_get_swfw_sync_semaphore(hw)) {
790 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
791 return IXGBE_ERR_SWFW_SYNC;
794 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
795 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
797 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
799 ixgbe_release_swfw_sync_semaphore(hw);
800 return IXGBE_SUCCESS;
802 /* Firmware currently using resource (fwmask), hardware
803 * currently using resource (hwmask), or other software
804 * thread currently using resource (swmask)
806 ixgbe_release_swfw_sync_semaphore(hw);
810 /* If the resource is not released by the FW/HW the SW can assume that
811 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
812 * of the requested resource(s) while ignoring the corresponding FW/HW
813 * bits in the SW_FW_SYNC register.
815 if (ixgbe_get_swfw_sync_semaphore(hw)) {
816 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
817 return IXGBE_ERR_SWFW_SYNC;
819 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
820 if (swfw_sync & (fwmask | hwmask)) {
822 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
823 ixgbe_release_swfw_sync_semaphore(hw);
825 return IXGBE_SUCCESS;
827 /* If the resource is not released by other SW the SW can assume that
828 * the other SW malfunctions. In that case the SW should clear all SW
829 * flags that it does not own and then repeat the whole process once
832 if (swfw_sync & swmask) {
833 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
834 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
835 IXGBE_GSSR_SW_MNG_SM;
838 rmask |= IXGBE_GSSR_I2C_MASK;
839 ixgbe_release_swfw_sync_X540(hw, rmask);
840 ixgbe_release_swfw_sync_semaphore(hw);
841 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
842 return IXGBE_ERR_SWFW_SYNC;
844 ixgbe_release_swfw_sync_semaphore(hw);
845 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
847 return IXGBE_ERR_SWFW_SYNC;
851 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
852 * @hw: pointer to hardware structure
853 * @mask: Mask to specify which semaphore to release
855 * Releases the SWFW semaphore through the SW_FW_SYNC register
856 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
858 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
860 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
863 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
865 if (mask & IXGBE_GSSR_I2C_MASK)
866 swmask |= mask & IXGBE_GSSR_I2C_MASK;
867 ixgbe_get_swfw_sync_semaphore(hw);
869 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
870 swfw_sync &= ~swmask;
871 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
873 ixgbe_release_swfw_sync_semaphore(hw);
878 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
879 * @hw: pointer to hardware structure
881 * Sets the hardware semaphores so SW/FW can gain control of shared resources
883 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
885 s32 status = IXGBE_ERR_EEPROM;
890 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
892 /* Get SMBI software semaphore between device drivers first */
893 for (i = 0; i < timeout; i++) {
895 * If the SMBI bit is 0 when we read it, then the bit will be
896 * set and we have the semaphore
898 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
899 if (!(swsm & IXGBE_SWSM_SMBI)) {
900 status = IXGBE_SUCCESS;
906 /* Now get the semaphore between SW/FW through the REGSMP bit */
907 if (status == IXGBE_SUCCESS) {
908 for (i = 0; i < timeout; i++) {
909 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
910 if (!(swsm & IXGBE_SWFW_REGSMP))
917 * Release semaphores and return error if SW NVM semaphore
918 * was not granted because we don't have access to the EEPROM
921 ERROR_REPORT1(IXGBE_ERROR_POLLING,
922 "REGSMP Software NVM semaphore not granted.\n");
923 ixgbe_release_swfw_sync_semaphore(hw);
924 status = IXGBE_ERR_EEPROM;
927 ERROR_REPORT1(IXGBE_ERROR_POLLING,
928 "Software semaphore SMBI between device drivers "
936 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
937 * @hw: pointer to hardware structure
939 * This function clears hardware semaphore bits.
941 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
945 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
947 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
949 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
950 swsm &= ~IXGBE_SWFW_REGSMP;
951 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
953 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
954 swsm &= ~IXGBE_SWSM_SMBI;
955 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
957 IXGBE_WRITE_FLUSH(hw);
961 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
962 * @hw: pointer to hardware structure
964 * This function reset hardware semaphore bits for a semaphore that may
965 * have be left locked due to a catastrophic failure.
967 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
971 /* First try to grab the semaphore but we don't need to bother
972 * looking to see whether we got the lock or not since we do
973 * the same thing regardless of whether we got the lock or not.
974 * We got the lock - we release it.
975 * We timeout trying to get the lock - we force its release.
977 ixgbe_get_swfw_sync_semaphore(hw);
978 ixgbe_release_swfw_sync_semaphore(hw);
980 /* Acquire and release all software resources. */
981 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
982 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
983 IXGBE_GSSR_SW_MNG_SM;
985 rmask |= IXGBE_GSSR_I2C_MASK;
986 ixgbe_acquire_swfw_sync_X540(hw, rmask);
987 ixgbe_release_swfw_sync_X540(hw, rmask);
991 * ixgbe_blink_led_start_X540 - Blink LED based on index.
992 * @hw: pointer to hardware structure
993 * @index: led number to blink
995 * Devices that implement the version 2 interface:
998 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1002 ixgbe_link_speed speed;
1005 DEBUGFUNC("ixgbe_blink_led_start_X540");
1008 return IXGBE_ERR_PARAM;
1011 * Link should be up in order for the blink bit in the LED control
1012 * register to work. Force link and speed in the MAC if link is down.
1013 * This will be reversed when we stop the blinking.
1015 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1016 if (link_up == false) {
1017 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1018 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
1019 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1021 /* Set the LED to LINK_UP + BLINK. */
1022 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1023 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1024 ledctl_reg |= IXGBE_LED_BLINK(index);
1025 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1026 IXGBE_WRITE_FLUSH(hw);
1028 return IXGBE_SUCCESS;
1032 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1033 * @hw: pointer to hardware structure
1034 * @index: led number to stop blinking
1036 * Devices that implement the version 2 interface:
1039 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1045 return IXGBE_ERR_PARAM;
1047 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1049 /* Restore the LED to its default value. */
1050 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1051 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1052 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1053 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1054 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1056 /* Unforce link and speed in the MAC. */
1057 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1058 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1059 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1060 IXGBE_WRITE_FLUSH(hw);
1062 return IXGBE_SUCCESS;