1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
44 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
45 * @hw: pointer to hardware structure
47 * Initialize the function pointers and assign the MAC type for X550.
48 * Does not touch the hardware.
50 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
52 struct ixgbe_mac_info *mac = &hw->mac;
53 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
56 DEBUGFUNC("ixgbe_init_ops_X550");
58 ret_val = ixgbe_init_ops_X540(hw);
59 mac->ops.dmac_config = ixgbe_dmac_config_X550;
60 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
61 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
62 mac->ops.setup_eee = ixgbe_setup_eee_X550;
63 mac->ops.set_source_address_pruning =
64 ixgbe_set_source_address_pruning_X550;
65 mac->ops.set_ethertype_anti_spoofing =
66 ixgbe_set_ethertype_anti_spoofing_X550;
68 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
69 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
70 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
71 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
72 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
73 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
74 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
75 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
76 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
79 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
80 mac->ops.mdd_event = ixgbe_mdd_event_X550;
81 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
82 mac->ops.disable_rx = ixgbe_disable_rx_x550;
83 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
84 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
85 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
91 * ixgbe_read_cs4227 - Read CS4227 register
92 * @hw: pointer to hardware structure
93 * @reg: register number to write
94 * @value: pointer to receive value read
98 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
104 * ixgbe_write_cs4227 - Write CS4227 register
105 * @hw: pointer to hardware structure
106 * @reg: register number to write
107 * @value: value to write to register
109 * Returns status code
111 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
117 * ixgbe_get_cs4227_status - Return CS4227 status
118 * @hw: pointer to hardware structure
120 * Performs a diagnostic on the CS4227 chip. Returns an error if it is
121 * not operating correctly.
122 * This function assumes that the caller has acquired the proper semaphore.
124 STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)
128 u16 reg_slice, reg_val;
131 /* Check register reads. */
132 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {
133 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,
135 if (status != IXGBE_SUCCESS)
137 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE)
139 msec_delay(IXGBE_CS4227_CHECK_DELAY);
141 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE)
142 return IXGBE_ERR_PHY;
144 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
145 if (status != IXGBE_SUCCESS)
148 /* If this is the first time after power-on, check the ucode.
149 * Otherwise, this will disrupt link on all ports. Because we
150 * can only do this the first time, we must check all ports,
152 * While we are at it, set the LINE side to 10G SR, which is
153 * what it needs to be regardless of the actual link.
155 if (value != IXGBE_CS4227_SCRATCH_VALUE) {
156 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB;
157 reg_val = IXGBE_CS4227_SPEED_10G;
158 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
159 if (status != IXGBE_SUCCESS)
162 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
163 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
164 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
165 if (status != IXGBE_SUCCESS)
168 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
169 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
170 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
171 if (status != IXGBE_SUCCESS)
174 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (1 << 12);
175 reg_val = IXGBE_CS4227_SPEED_10G;
176 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
177 if (status != IXGBE_SUCCESS)
180 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
181 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
182 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
183 if (status != IXGBE_SUCCESS)
186 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
187 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
188 status = ixgbe_write_cs4227(hw, reg_slice, reg_val);
189 if (status != IXGBE_SUCCESS)
195 /* Verify that the ucode is operational on all ports. */
196 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;
198 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
199 if (status != IXGBE_SUCCESS)
202 return IXGBE_ERR_PHY;
204 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;
206 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
207 if (status != IXGBE_SUCCESS)
210 return IXGBE_ERR_PHY;
212 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);
214 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
215 if (status != IXGBE_SUCCESS)
218 return IXGBE_ERR_PHY;
220 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);
222 status = ixgbe_read_cs4227(hw, reg_slice, ®_val);
223 if (status != IXGBE_SUCCESS)
226 return IXGBE_ERR_PHY;
228 /* Set scratch indicating that the diagnostic was successful. */
229 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
230 IXGBE_CS4227_SCRATCH_VALUE);
231 if (status != IXGBE_SUCCESS)
233 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
234 if (status != IXGBE_SUCCESS)
236 if (value != IXGBE_CS4227_SCRATCH_VALUE)
237 return IXGBE_ERR_PHY;
239 return IXGBE_SUCCESS;
243 * ixgbe_read_pe - Read register from port expander
244 * @hw: pointer to hardware structure
245 * @reg: register number to read
246 * @value: pointer to receive read value
248 * Returns status code
250 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
254 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
255 if (status != IXGBE_SUCCESS)
256 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
257 "port expander access failed with %d\n", status);
262 * ixgbe_write_pe - Write register to port expander
263 * @hw: pointer to hardware structure
264 * @reg: register number to write
265 * @value: value to write
267 * Returns status code
269 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
273 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
274 if (status != IXGBE_SUCCESS)
275 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
276 "port expander access failed with %d\n", status);
281 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
282 * @hw: pointer to hardware structure
286 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
291 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
292 if (status != IXGBE_SUCCESS)
294 reg |= IXGBE_PE_BIT1;
295 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
296 if (status != IXGBE_SUCCESS)
299 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
300 if (status != IXGBE_SUCCESS)
302 reg &= ~IXGBE_PE_BIT1;
303 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
304 if (status != IXGBE_SUCCESS)
307 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
308 if (status != IXGBE_SUCCESS)
310 reg &= ~IXGBE_PE_BIT1;
311 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
312 if (status != IXGBE_SUCCESS)
315 usec_delay(IXGBE_CS4227_RESET_HOLD);
317 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
318 if (status != IXGBE_SUCCESS)
320 reg |= IXGBE_PE_BIT1;
321 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
322 if (status != IXGBE_SUCCESS)
325 msec_delay(IXGBE_CS4227_RESET_DELAY);
327 return IXGBE_SUCCESS;
331 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
332 * @hw: pointer to hardware structure
334 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
336 u32 swfw_mask = hw->phy.phy_semaphore_mask;
340 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
341 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
342 if (status != IXGBE_SUCCESS) {
343 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
344 "semaphore failed with %d\n", status);
347 status = ixgbe_get_cs4227_status(hw);
348 if (status == IXGBE_SUCCESS) {
349 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
350 msec_delay(hw->eeprom.semaphore_delay);
353 ixgbe_reset_cs4227(hw);
354 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
355 msec_delay(hw->eeprom.semaphore_delay);
357 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
358 "Unable to initialize CS4227, err=%d\n", status);
362 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
363 * @hw: pointer to hardware structure
365 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
367 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
369 if (hw->bus.lan_id) {
370 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
371 esdp |= IXGBE_ESDP_SDP1_DIR;
373 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
374 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
375 IXGBE_WRITE_FLUSH(hw);
379 * ixgbe_identify_phy_x550em - Get PHY type based on device id
380 * @hw: pointer to hardware structure
384 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
386 switch (hw->device_id) {
387 case IXGBE_DEV_ID_X550EM_X_SFP:
388 /* set up for CS4227 usage */
389 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
390 ixgbe_setup_mux_ctl(hw);
391 ixgbe_check_cs4227(hw);
393 return ixgbe_identify_module_generic(hw);
395 case IXGBE_DEV_ID_X550EM_X_KX4:
396 hw->phy.type = ixgbe_phy_x550em_kx4;
398 case IXGBE_DEV_ID_X550EM_X_KR:
399 hw->phy.type = ixgbe_phy_x550em_kr;
401 case IXGBE_DEV_ID_X550EM_X_1G_T:
402 case IXGBE_DEV_ID_X550EM_X_10G_T:
403 return ixgbe_identify_phy_generic(hw);
407 return IXGBE_SUCCESS;
410 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
411 u32 device_type, u16 *phy_data)
413 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
414 return IXGBE_NOT_IMPLEMENTED;
417 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
418 u32 device_type, u16 phy_data)
420 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
421 return IXGBE_NOT_IMPLEMENTED;
425 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
426 * @hw: pointer to hardware structure
428 * Initialize the function pointers and for MAC type X550EM.
429 * Does not touch the hardware.
431 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
433 struct ixgbe_mac_info *mac = &hw->mac;
434 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
435 struct ixgbe_phy_info *phy = &hw->phy;
438 DEBUGFUNC("ixgbe_init_ops_X550EM");
440 /* Similar to X550 so start there. */
441 ret_val = ixgbe_init_ops_X550(hw);
443 /* Since this function eventually calls
444 * ixgbe_init_ops_540 by design, we are setting
445 * the pointers to NULL explicitly here to overwrite
446 * the values being set in the x540 function.
448 /* Thermal sensor not supported in x550EM */
449 mac->ops.get_thermal_sensor_data = NULL;
450 mac->ops.init_thermal_sensor_thresh = NULL;
451 mac->thermal_sensor_enabled = false;
453 /* FCOE not supported in x550EM */
454 mac->ops.get_san_mac_addr = NULL;
455 mac->ops.set_san_mac_addr = NULL;
456 mac->ops.get_wwn_prefix = NULL;
457 mac->ops.get_fcoe_boot_status = NULL;
459 /* IPsec not supported in x550EM */
460 mac->ops.disable_sec_rx_path = NULL;
461 mac->ops.enable_sec_rx_path = NULL;
463 /* AUTOC register is not present in x550EM. */
464 mac->ops.prot_autoc_read = NULL;
465 mac->ops.prot_autoc_write = NULL;
467 /* X550EM bus type is internal*/
468 hw->bus.type = ixgbe_bus_type_internal;
469 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
471 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
472 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
473 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
474 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
475 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
476 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
477 mac->ops.get_supported_physical_layer =
478 ixgbe_get_supported_physical_layer_X550em;
480 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
481 mac->ops.setup_fc = ixgbe_setup_fc_generic;
483 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
485 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
486 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
488 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
489 mac->ops.setup_eee = NULL;
492 phy->ops.init = ixgbe_init_phy_ops_X550em;
493 phy->ops.identify = ixgbe_identify_phy_x550em;
494 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
495 phy->ops.set_phy_power = NULL;
499 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
500 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
501 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
502 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
503 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
504 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
505 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
506 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
512 * ixgbe_dmac_config_X550
513 * @hw: pointer to hardware structure
515 * Configure DMA coalescing. If enabling dmac, dmac is activated.
516 * When disabling dmac, dmac enable dmac bit is cleared.
518 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
520 u32 reg, high_pri_tc;
522 DEBUGFUNC("ixgbe_dmac_config_X550");
524 /* Disable DMA coalescing before configuring */
525 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
526 reg &= ~IXGBE_DMACR_DMAC_EN;
527 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
529 /* Disable DMA Coalescing if the watchdog timer is 0 */
530 if (!hw->mac.dmac_config.watchdog_timer)
533 ixgbe_dmac_config_tcs_X550(hw);
535 /* Configure DMA Coalescing Control Register */
536 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
538 /* Set the watchdog timer in units of 40.96 usec */
539 reg &= ~IXGBE_DMACR_DMACWT_MASK;
540 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
542 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
543 /* If fcoe is enabled, set high priority traffic class */
544 if (hw->mac.dmac_config.fcoe_en) {
545 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
546 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
547 IXGBE_DMACR_HIGH_PRI_TC_MASK);
549 reg |= IXGBE_DMACR_EN_MNG_IND;
551 /* Enable DMA coalescing after configuration */
552 reg |= IXGBE_DMACR_DMAC_EN;
553 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
556 return IXGBE_SUCCESS;
560 * ixgbe_dmac_config_tcs_X550
561 * @hw: pointer to hardware structure
563 * Configure DMA coalescing threshold per TC. The dmac enable bit must
564 * be cleared before configuring.
566 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
568 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
570 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
572 /* Configure DMA coalescing enabled */
573 switch (hw->mac.dmac_config.link_speed) {
574 case IXGBE_LINK_SPEED_100_FULL:
575 pb_headroom = IXGBE_DMACRXT_100M;
577 case IXGBE_LINK_SPEED_1GB_FULL:
578 pb_headroom = IXGBE_DMACRXT_1G;
581 pb_headroom = IXGBE_DMACRXT_10G;
585 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
586 IXGBE_MHADD_MFS_SHIFT) / 1024);
588 /* Set the per Rx packet buffer receive threshold */
589 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
590 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
591 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
593 if (tc < hw->mac.dmac_config.num_tcs) {
595 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
596 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
597 IXGBE_RXPBSIZE_SHIFT;
599 /* Calculate receive buffer threshold in kilobytes */
600 if (rx_pb_size > pb_headroom)
601 rx_pb_size = rx_pb_size - pb_headroom;
605 /* Minimum of MFS shall be set for DMCTH */
606 reg |= (rx_pb_size > maxframe_size_kb) ?
607 rx_pb_size : maxframe_size_kb;
609 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
611 return IXGBE_SUCCESS;
615 * ixgbe_dmac_update_tcs_X550
616 * @hw: pointer to hardware structure
618 * Disables dmac, updates per TC settings, and then enables dmac.
620 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
624 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
626 /* Disable DMA coalescing before configuring */
627 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
628 reg &= ~IXGBE_DMACR_DMAC_EN;
629 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
631 ixgbe_dmac_config_tcs_X550(hw);
633 /* Enable DMA coalescing after configuration */
634 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
635 reg |= IXGBE_DMACR_DMAC_EN;
636 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
638 return IXGBE_SUCCESS;
642 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
643 * @hw: pointer to hardware structure
645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
646 * ixgbe_hw struct in order to set up EEPROM access.
648 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
654 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
656 if (eeprom->type == ixgbe_eeprom_uninitialized) {
657 eeprom->semaphore_delay = 10;
658 eeprom->type = ixgbe_flash;
660 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
661 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
662 IXGBE_EEC_SIZE_SHIFT);
663 eeprom->word_size = 1 << (eeprom_size +
664 IXGBE_EEPROM_WORD_SIZE_SHIFT);
666 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
667 eeprom->type, eeprom->word_size);
670 return IXGBE_SUCCESS;
674 * ixgbe_setup_eee_X550 - Enable/disable EEE support
675 * @hw: pointer to the HW structure
676 * @enable_eee: boolean flag to enable EEE
678 * Enable/disable EEE based on enable_eee flag.
679 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
683 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
691 DEBUGFUNC("ixgbe_setup_eee_X550");
693 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
694 /* Enable or disable EEE per flag */
696 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
698 if (hw->device_id == IXGBE_DEV_ID_X550T) {
699 /* Advertise EEE capability */
700 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
701 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
703 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
704 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
705 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
707 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
708 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
709 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
710 /* Not supported on first revision. */
711 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
712 if (!(fuse & IXGBE_FUSES0_REV1))
713 return IXGBE_SUCCESS;
715 status = ixgbe_read_iosf_sb_reg_x550(hw,
716 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
717 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
718 if (status != IXGBE_SUCCESS)
721 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
722 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
724 /* Don't advertise FEC capability when EEE enabled. */
725 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
727 status = ixgbe_write_iosf_sb_reg_x550(hw,
728 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
729 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
730 if (status != IXGBE_SUCCESS)
734 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
736 if (hw->device_id == IXGBE_DEV_ID_X550T) {
737 /* Disable advertised EEE capability */
738 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
739 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
741 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
742 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
743 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
745 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
747 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
748 status = ixgbe_read_iosf_sb_reg_x550(hw,
749 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
750 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
751 if (status != IXGBE_SUCCESS)
754 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
755 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
757 /* Advertise FEC capability when EEE is disabled. */
758 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
760 status = ixgbe_write_iosf_sb_reg_x550(hw,
761 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
762 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
763 if (status != IXGBE_SUCCESS)
767 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
769 return IXGBE_SUCCESS;
773 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
774 * @hw: pointer to hardware structure
775 * @enable: enable or disable source address pruning
776 * @pool: Rx pool to set source address pruning for
778 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
783 /* max rx pool is 63 */
787 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
788 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
791 pfflp |= (1ULL << pool);
793 pfflp &= ~(1ULL << pool);
795 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
796 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
800 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
801 * @hw: pointer to hardware structure
802 * @enable: enable or disable switch for Ethertype anti-spoofing
803 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
806 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
809 int vf_target_reg = vf >> 3;
810 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
813 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
815 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
817 pfvfspoof |= (1 << vf_target_shift);
819 pfvfspoof &= ~(1 << vf_target_shift);
821 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
825 * ixgbe_iosf_wait - Wait for IOSF command completion
826 * @hw: pointer to hardware structure
827 * @ctrl: pointer to location to receive final IOSF control value
829 * Returns failing status on timeout
831 * Note: ctrl can be NULL if the IOSF control register value is not needed
833 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
837 /* Check every 10 usec to see if the address cycle completed.
838 * The SB IOSF BUSY bit will clear when the operation is
841 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
842 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
843 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
849 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
850 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
851 return IXGBE_ERR_PHY;
854 return IXGBE_SUCCESS;
858 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
860 * @hw: pointer to hardware structure
861 * @reg_addr: 32 bit PHY register to write
862 * @device_type: 3 bit device type
863 * @data: Data to write to the register
865 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
866 u32 device_type, u32 data)
868 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
872 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
873 if (ret != IXGBE_SUCCESS)
876 ret = ixgbe_iosf_wait(hw, NULL);
877 if (ret != IXGBE_SUCCESS)
880 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
881 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
883 /* Write IOSF control register */
884 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
886 /* Write IOSF data register */
887 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
889 ret = ixgbe_iosf_wait(hw, &command);
891 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
892 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
893 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
894 ERROR_REPORT2(IXGBE_ERROR_POLLING,
895 "Failed to write, error %x\n", error);
900 ixgbe_release_swfw_semaphore(hw, gssr);
905 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
907 * @hw: pointer to hardware structure
908 * @reg_addr: 32 bit PHY register to write
909 * @device_type: 3 bit device type
910 * @phy_data: Pointer to read data from the register
912 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
913 u32 device_type, u32 *data)
915 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
919 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
920 if (ret != IXGBE_SUCCESS)
923 ret = ixgbe_iosf_wait(hw, NULL);
924 if (ret != IXGBE_SUCCESS)
927 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
928 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
930 /* Write IOSF control register */
931 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
933 ret = ixgbe_iosf_wait(hw, &command);
935 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
936 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
937 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
938 ERROR_REPORT2(IXGBE_ERROR_POLLING,
939 "Failed to read, error %x\n", error);
943 if (ret == IXGBE_SUCCESS)
944 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
947 ixgbe_release_swfw_semaphore(hw, gssr);
952 * ixgbe_disable_mdd_X550
953 * @hw: pointer to hardware structure
955 * Disable malicious driver detection
957 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
961 DEBUGFUNC("ixgbe_disable_mdd_X550");
963 /* Disable MDD for TX DMA and interrupt */
964 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
965 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
966 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
968 /* Disable MDD for RX and interrupt */
969 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
970 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
971 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
975 * ixgbe_enable_mdd_X550
976 * @hw: pointer to hardware structure
978 * Enable malicious driver detection
980 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
984 DEBUGFUNC("ixgbe_enable_mdd_X550");
986 /* Enable MDD for TX DMA and interrupt */
987 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
988 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
989 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
991 /* Enable MDD for RX and interrupt */
992 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
993 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
994 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
998 * ixgbe_restore_mdd_vf_X550
999 * @hw: pointer to hardware structure
1002 * Restore VF that was disabled during malicious driver detection event
1004 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1006 u32 idx, reg, num_qs, start_q, bitmask;
1008 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1010 /* Map VF to queues */
1011 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1012 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1013 case IXGBE_MRQC_VMDQRT8TCEN:
1014 num_qs = 8; /* 16 VFs / pools */
1015 bitmask = 0x000000FF;
1017 case IXGBE_MRQC_VMDQRSS32EN:
1018 case IXGBE_MRQC_VMDQRT4TCEN:
1019 num_qs = 4; /* 32 VFs / pools */
1020 bitmask = 0x0000000F;
1022 default: /* 64 VFs / pools */
1024 bitmask = 0x00000003;
1027 start_q = vf * num_qs;
1029 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1032 reg |= (bitmask << (start_q % 32));
1033 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1034 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1038 * ixgbe_mdd_event_X550
1039 * @hw: pointer to hardware structure
1040 * @vf_bitmap: vf bitmap of malicious vfs
1042 * Handle malicious driver detection event.
1044 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1047 u32 i, j, reg, q, shift, vf, idx;
1049 DEBUGFUNC("ixgbe_mdd_event_X550");
1051 /* figure out pool size for mapping to vf's */
1052 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1053 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1054 case IXGBE_MRQC_VMDQRT8TCEN:
1055 shift = 3; /* 16 VFs / pools */
1057 case IXGBE_MRQC_VMDQRSS32EN:
1058 case IXGBE_MRQC_VMDQRT4TCEN:
1059 shift = 2; /* 32 VFs / pools */
1062 shift = 1; /* 64 VFs / pools */
1066 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1067 for (i = 0; i < 4; i++) {
1068 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1069 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1074 /* Get malicious queue */
1075 for (j = 0; j < 32 && wqbr; j++) {
1077 if (!(wqbr & (1 << j)))
1080 /* Get queue from bitmask */
1083 /* Map queue to vf */
1086 /* Set vf bit in vf_bitmap */
1088 vf_bitmap[idx] |= (1 << (vf % 32));
1095 * ixgbe_get_media_type_X550em - Get media type
1096 * @hw: pointer to hardware structure
1098 * Returns the media type (fiber, copper, backplane)
1100 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1102 enum ixgbe_media_type media_type;
1104 DEBUGFUNC("ixgbe_get_media_type_X550em");
1106 /* Detect if there is a copper PHY attached. */
1107 switch (hw->device_id) {
1108 case IXGBE_DEV_ID_X550EM_X_KR:
1109 case IXGBE_DEV_ID_X550EM_X_KX4:
1110 media_type = ixgbe_media_type_backplane;
1112 case IXGBE_DEV_ID_X550EM_X_SFP:
1113 media_type = ixgbe_media_type_fiber;
1115 case IXGBE_DEV_ID_X550EM_X_1G_T:
1116 case IXGBE_DEV_ID_X550EM_X_10G_T:
1117 media_type = ixgbe_media_type_copper;
1120 media_type = ixgbe_media_type_unknown;
1127 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1128 * @hw: pointer to hardware structure
1129 * @linear: true if SFP module is linear
1131 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1133 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1135 switch (hw->phy.sfp_type) {
1136 case ixgbe_sfp_type_not_present:
1137 return IXGBE_ERR_SFP_NOT_PRESENT;
1138 case ixgbe_sfp_type_da_cu_core0:
1139 case ixgbe_sfp_type_da_cu_core1:
1142 case ixgbe_sfp_type_srlr_core0:
1143 case ixgbe_sfp_type_srlr_core1:
1144 case ixgbe_sfp_type_da_act_lmt_core0:
1145 case ixgbe_sfp_type_da_act_lmt_core1:
1146 case ixgbe_sfp_type_1g_sx_core0:
1147 case ixgbe_sfp_type_1g_sx_core1:
1148 case ixgbe_sfp_type_1g_lx_core0:
1149 case ixgbe_sfp_type_1g_lx_core1:
1152 case ixgbe_sfp_type_unknown:
1153 case ixgbe_sfp_type_1g_cu_core0:
1154 case ixgbe_sfp_type_1g_cu_core1:
1156 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1159 return IXGBE_SUCCESS;
1163 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1164 * @hw: pointer to hardware structure
1166 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1168 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1173 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1175 status = ixgbe_identify_module_generic(hw);
1177 if (status != IXGBE_SUCCESS)
1180 /* Check if SFP module is supported */
1181 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1187 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1188 * @hw: pointer to hardware structure
1190 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1195 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1197 /* Check if SFP module is supported */
1198 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1200 if (status != IXGBE_SUCCESS)
1203 ixgbe_init_mac_link_ops_X550em(hw);
1204 hw->phy.ops.reset = NULL;
1206 return IXGBE_SUCCESS;
1210 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1211 * @hw: pointer to hardware structure
1213 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1215 struct ixgbe_mac_info *mac = &hw->mac;
1217 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1219 switch (hw->mac.ops.get_media_type(hw)) {
1220 case ixgbe_media_type_fiber:
1221 /* CS4227 does not support autoneg, so disable the laser control
1222 * functions for SFP+ fiber
1224 mac->ops.disable_tx_laser = NULL;
1225 mac->ops.enable_tx_laser = NULL;
1226 mac->ops.flap_tx_laser = NULL;
1227 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1228 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1229 mac->ops.set_rate_select_speed =
1230 ixgbe_set_soft_rate_select_speed;
1232 case ixgbe_media_type_copper:
1233 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1234 mac->ops.check_link = ixgbe_check_link_t_X550em;
1242 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1243 * @hw: pointer to hardware structure
1244 * @speed: pointer to link speed
1245 * @autoneg: true when autoneg or autotry is enabled
1247 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1248 ixgbe_link_speed *speed,
1251 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1254 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1256 /* CS4227 SFP must not enable auto-negotiation */
1259 /* Check if 1G SFP module. */
1260 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1261 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1262 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1263 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1264 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1265 return IXGBE_SUCCESS;
1268 /* Link capabilities are based on SFP */
1269 if (hw->phy.multispeed_fiber)
1270 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1271 IXGBE_LINK_SPEED_1GB_FULL;
1273 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1275 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1276 IXGBE_LINK_SPEED_1GB_FULL;
1280 return IXGBE_SUCCESS;
1284 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1285 * @hw: pointer to hardware structure
1286 * @lsc: pointer to boolean flag which indicates whether external Base T
1287 * PHY interrupt is lsc
1289 * Determime if external Base T PHY interrupt cause is high temperature
1290 * failure alarm or link status change.
1292 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1293 * failure alarm, else return PHY access status.
1295 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1302 /* Vendor alarm triggered */
1303 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1304 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1307 if (status != IXGBE_SUCCESS ||
1308 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1311 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1312 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1313 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1316 if (status != IXGBE_SUCCESS ||
1317 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1318 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1321 /* High temperature failure alarm triggered */
1322 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1323 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1326 if (status != IXGBE_SUCCESS)
1329 /* If high temperature failure, then return over temp error and exit */
1330 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1331 /* power down the PHY in case the PHY FW didn't already */
1332 ixgbe_set_copper_phy_power(hw, false);
1333 return IXGBE_ERR_OVERTEMP;
1336 /* Vendor alarm 2 triggered */
1337 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1338 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1340 if (status != IXGBE_SUCCESS ||
1341 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1344 /* link connect/disconnect event occurred */
1345 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1346 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1348 if (status != IXGBE_SUCCESS)
1352 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1355 return IXGBE_SUCCESS;
1359 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1360 * @hw: pointer to hardware structure
1362 * Enable link status change and temperature failure alarm for the external
1365 * Returns PHY access status
1367 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1373 /* Clear interrupt flags */
1374 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1376 /* Enable link status change alarm */
1377 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1378 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1380 if (status != IXGBE_SUCCESS)
1383 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1385 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1386 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1388 if (status != IXGBE_SUCCESS)
1391 /* Enables high temperature failure alarm */
1392 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1393 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1396 if (status != IXGBE_SUCCESS)
1399 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1401 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1402 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1405 if (status != IXGBE_SUCCESS)
1408 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1409 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1410 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1413 if (status != IXGBE_SUCCESS)
1416 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1417 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1419 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1420 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1423 if (status != IXGBE_SUCCESS)
1426 /* Enable chip-wide vendor alarm */
1427 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1428 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1431 if (status != IXGBE_SUCCESS)
1434 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1436 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1437 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1444 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1445 * @hw: pointer to hardware structure
1446 * @speed: link speed
1448 * Configures the integrated KR PHY.
1450 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1451 ixgbe_link_speed speed)
1456 status = ixgbe_read_iosf_sb_reg_x550(hw,
1457 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1458 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1462 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1463 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1464 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1466 /* Advertise 10G support. */
1467 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1468 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1470 /* Advertise 1G support. */
1471 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1472 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1474 /* Restart auto-negotiation. */
1475 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1476 status = ixgbe_write_iosf_sb_reg_x550(hw,
1477 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1478 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1484 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1485 * @hw: pointer to hardware structure
1487 * Initialize any function pointers that were not able to be
1488 * set during init_shared_code because the PHY/SFP type was
1489 * not known. Perform the SFP init if necessary.
1491 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1493 struct ixgbe_phy_info *phy = &hw->phy;
1494 ixgbe_link_speed speed;
1497 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1499 hw->mac.ops.set_lan_id(hw);
1501 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1502 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1503 ixgbe_setup_mux_ctl(hw);
1505 /* Save NW management interface connected on board. This is used
1506 * to determine internal PHY mode.
1508 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1510 /* If internal PHY mode is KR, then initialize KR link */
1511 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1512 speed = IXGBE_LINK_SPEED_10GB_FULL |
1513 IXGBE_LINK_SPEED_1GB_FULL;
1514 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1517 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1520 /* Identify the PHY or SFP module */
1521 ret_val = phy->ops.identify(hw);
1522 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1525 /* Setup function pointers based on detected hardware */
1526 ixgbe_init_mac_link_ops_X550em(hw);
1527 if (phy->sfp_type != ixgbe_sfp_type_unknown)
1528 phy->ops.reset = NULL;
1530 /* Set functions pointers based on phy type */
1531 switch (hw->phy.type) {
1532 case ixgbe_phy_x550em_kx4:
1533 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
1534 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1535 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1537 case ixgbe_phy_x550em_kr:
1538 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1539 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1540 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1542 case ixgbe_phy_x550em_ext_t:
1543 /* Save NW management interface connected on board. This is used
1544 * to determine internal PHY mode
1546 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1548 /* If internal link mode is XFI, then setup iXFI internal link,
1549 * else setup KR now.
1551 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1552 phy->ops.setup_internal_link =
1553 ixgbe_setup_internal_phy_t_x550em;
1555 speed = IXGBE_LINK_SPEED_10GB_FULL |
1556 IXGBE_LINK_SPEED_1GB_FULL;
1557 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1560 /* setup SW LPLU only for first revision */
1561 if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1562 IXGBE_FUSES0_GROUP(0))))
1563 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1565 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1566 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1575 * ixgbe_reset_hw_X550em - Perform hardware reset
1576 * @hw: pointer to hardware structure
1578 * Resets the hardware by resetting the transmit and receive units, masks
1579 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1582 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1584 ixgbe_link_speed link_speed;
1589 bool link_up = false;
1591 DEBUGFUNC("ixgbe_reset_hw_X550em");
1593 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1594 status = hw->mac.ops.stop_adapter(hw);
1595 if (status != IXGBE_SUCCESS)
1598 /* flush pending Tx transactions */
1599 ixgbe_clear_tx_pending(hw);
1601 /* PHY ops must be identified and initialized prior to reset */
1603 /* Identify PHY and related function pointers */
1604 status = hw->phy.ops.init(hw);
1606 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1609 /* start the external PHY */
1610 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1611 status = ixgbe_init_ext_t_x550em(hw);
1616 /* Setup SFP module if there is one present. */
1617 if (hw->phy.sfp_setup_needed) {
1618 status = hw->mac.ops.setup_sfp(hw);
1619 hw->phy.sfp_setup_needed = false;
1622 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1626 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1627 hw->phy.ops.reset(hw);
1630 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1631 * If link reset is used when link is up, it might reset the PHY when
1632 * mng is using it. If link is down or the flag to force full link
1633 * reset is set, then perform link reset.
1635 ctrl = IXGBE_CTRL_LNK_RST;
1636 if (!hw->force_full_reset) {
1637 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1639 ctrl = IXGBE_CTRL_RST;
1642 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1643 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1644 IXGBE_WRITE_FLUSH(hw);
1646 /* Poll for reset bit to self-clear meaning reset is complete */
1647 for (i = 0; i < 10; i++) {
1649 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1650 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1654 if (ctrl & IXGBE_CTRL_RST_MASK) {
1655 status = IXGBE_ERR_RESET_FAILED;
1656 DEBUGOUT("Reset polling failed to complete.\n");
1661 /* Double resets are required for recovery from certain error
1662 * conditions. Between resets, it is necessary to stall to
1663 * allow time for any pending HW events to complete.
1665 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1666 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1670 /* Store the permanent mac address */
1671 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1673 /* Store MAC address from RAR0, clear receive address registers, and
1674 * clear the multicast table. Also reset num_rar_entries to 128,
1675 * since we modify this value when programming the SAN MAC address.
1677 hw->mac.num_rar_entries = 128;
1678 hw->mac.ops.init_rx_addrs(hw);
1680 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1681 /* Config MDIO clock speed. */
1682 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1683 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1684 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1687 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1688 ixgbe_setup_mux_ctl(hw);
1694 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1695 * @hw: pointer to hardware structure
1697 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1702 status = hw->phy.ops.read_reg(hw,
1703 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1704 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1707 if (status != IXGBE_SUCCESS)
1710 /* If PHY FW reset completed bit is set then this is the first
1711 * SW instance after a power on so the PHY FW must be un-stalled.
1713 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1714 status = hw->phy.ops.read_reg(hw,
1715 IXGBE_MDIO_GLOBAL_RES_PR_10,
1716 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1719 if (status != IXGBE_SUCCESS)
1722 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1724 status = hw->phy.ops.write_reg(hw,
1725 IXGBE_MDIO_GLOBAL_RES_PR_10,
1726 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1729 if (status != IXGBE_SUCCESS)
1737 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1738 * @hw: pointer to hardware structure
1740 * Configures the integrated KR PHY.
1742 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1744 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1748 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1749 * @hw: pointer to hardware structure
1751 * Configures the integrated KX4 PHY.
1753 s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1758 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1759 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);
1763 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1764 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1766 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1768 /* Advertise 10G support. */
1769 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1770 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1772 /* Advertise 1G support. */
1773 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1774 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1776 /* Restart auto-negotiation. */
1777 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1778 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,
1779 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);
1785 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1786 * @hw: pointer to hardware structure
1788 * Configure the external PHY and the integrated KR PHY for SFP support.
1790 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1791 ixgbe_link_speed speed,
1792 bool autoneg_wait_to_complete)
1795 u16 reg_slice, reg_val;
1796 bool setup_linear = false;
1797 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1799 /* Check if SFP module is supported and linear */
1800 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1802 /* If no SFP module present, then return success. Return success since
1803 * there is no reason to configure CS4227 and SFP not present error is
1804 * not excepted in the setup MAC link flow.
1806 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1807 return IXGBE_SUCCESS;
1809 if (ret_val != IXGBE_SUCCESS)
1812 /* Configure CS4227 LINE side to 10G SR. */
1813 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1814 reg_val = IXGBE_CS4227_SPEED_10G;
1815 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1818 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1819 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1820 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1823 /* Configure CS4227 for HOST connection rate then type. */
1824 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1825 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1826 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1827 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1830 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1832 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1834 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1835 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1838 /* If internal link mode is XFI, then setup XFI internal link. */
1839 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))
1840 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1846 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1847 * @hw: pointer to hardware structure
1848 * @speed: the link speed to force
1850 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1851 * internal and external PHY at a specific speed, without autonegotiation.
1853 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1858 /* Disable AN and force speed to 10G Serial. */
1859 status = ixgbe_read_iosf_sb_reg_x550(hw,
1860 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1861 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1862 if (status != IXGBE_SUCCESS)
1865 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1866 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1868 /* Select forced link speed for internal PHY. */
1870 case IXGBE_LINK_SPEED_10GB_FULL:
1871 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1873 case IXGBE_LINK_SPEED_1GB_FULL:
1874 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1877 /* Other link speeds are not supported by internal KR PHY. */
1878 return IXGBE_ERR_LINK_SETUP;
1881 status = ixgbe_write_iosf_sb_reg_x550(hw,
1882 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1883 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1884 if (status != IXGBE_SUCCESS)
1887 /* Disable training protocol FSM. */
1888 status = ixgbe_read_iosf_sb_reg_x550(hw,
1889 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1890 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1891 if (status != IXGBE_SUCCESS)
1893 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1894 status = ixgbe_write_iosf_sb_reg_x550(hw,
1895 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1896 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1897 if (status != IXGBE_SUCCESS)
1900 /* Disable Flex from training TXFFE. */
1901 status = ixgbe_read_iosf_sb_reg_x550(hw,
1902 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1903 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1904 if (status != IXGBE_SUCCESS)
1906 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1907 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1908 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1909 status = ixgbe_write_iosf_sb_reg_x550(hw,
1910 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1911 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1912 if (status != IXGBE_SUCCESS)
1914 status = ixgbe_read_iosf_sb_reg_x550(hw,
1915 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1916 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1917 if (status != IXGBE_SUCCESS)
1919 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1920 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1921 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1922 status = ixgbe_write_iosf_sb_reg_x550(hw,
1923 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1924 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1925 if (status != IXGBE_SUCCESS)
1928 /* Enable override for coefficients. */
1929 status = ixgbe_read_iosf_sb_reg_x550(hw,
1930 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1931 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1932 if (status != IXGBE_SUCCESS)
1934 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1935 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1936 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1937 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1938 status = ixgbe_write_iosf_sb_reg_x550(hw,
1939 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1940 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1941 if (status != IXGBE_SUCCESS)
1944 /* Toggle port SW reset by AN reset. */
1945 status = ixgbe_read_iosf_sb_reg_x550(hw,
1946 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1947 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1948 if (status != IXGBE_SUCCESS)
1950 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1951 status = ixgbe_write_iosf_sb_reg_x550(hw,
1952 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1953 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1959 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1960 * @hw: address of hardware structure
1961 * @link_up: address of boolean to indicate link status
1963 * Returns error code if unable to get link status.
1965 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1972 /* read this twice back to back to indicate current status */
1973 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1974 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1976 if (ret != IXGBE_SUCCESS)
1979 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1980 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1982 if (ret != IXGBE_SUCCESS)
1985 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1987 return IXGBE_SUCCESS;
1991 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1992 * @hw: point to hardware structure
1994 * Configures the link between the integrated KR PHY and the external X557 PHY
1995 * The driver will call this function when it gets a link status change
1996 * interrupt from the X557 PHY. This function configures the link speed
1997 * between the PHYs to match the link speed of the BASE-T link.
1999 * A return of a non-zero value indicates an error, and the base driver should
2000 * not report link up.
2002 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2004 ixgbe_link_speed force_speed;
2009 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2010 return IXGBE_ERR_CONFIG;
2012 /* If link is not up, then there is no setup necessary so return */
2013 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2014 if (status != IXGBE_SUCCESS)
2018 return IXGBE_SUCCESS;
2020 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2021 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2023 if (status != IXGBE_SUCCESS)
2026 /* If link is not still up, then no setup is necessary so return */
2027 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2028 if (status != IXGBE_SUCCESS)
2031 return IXGBE_SUCCESS;
2033 /* clear everything but the speed and duplex bits */
2034 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2037 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2038 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2040 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2041 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2044 /* Internal PHY does not support anything else */
2045 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2048 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2052 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2053 * @hw: pointer to hardware structure
2055 * Configures the integrated KR PHY to use internal loopback mode.
2057 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2062 /* Disable AN and force speed to 10G Serial. */
2063 status = ixgbe_read_iosf_sb_reg_x550(hw,
2064 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2065 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2066 if (status != IXGBE_SUCCESS)
2068 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2069 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2070 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2071 status = ixgbe_write_iosf_sb_reg_x550(hw,
2072 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2073 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2074 if (status != IXGBE_SUCCESS)
2077 /* Set near-end loopback clocks. */
2078 status = ixgbe_read_iosf_sb_reg_x550(hw,
2079 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2080 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2081 if (status != IXGBE_SUCCESS)
2083 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2084 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2085 status = ixgbe_write_iosf_sb_reg_x550(hw,
2086 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2087 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2088 if (status != IXGBE_SUCCESS)
2091 /* Set loopback enable. */
2092 status = ixgbe_read_iosf_sb_reg_x550(hw,
2093 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2094 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2095 if (status != IXGBE_SUCCESS)
2097 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2098 status = ixgbe_write_iosf_sb_reg_x550(hw,
2099 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2100 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2101 if (status != IXGBE_SUCCESS)
2104 /* Training bypass. */
2105 status = ixgbe_read_iosf_sb_reg_x550(hw,
2106 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2107 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2108 if (status != IXGBE_SUCCESS)
2110 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2111 status = ixgbe_write_iosf_sb_reg_x550(hw,
2112 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2113 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2119 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2120 * assuming that the semaphore is already obtained.
2121 * @hw: pointer to hardware structure
2122 * @offset: offset of word in the EEPROM to read
2123 * @data: word read from the EEPROM
2125 * Reads a 16 bit word from the EEPROM using the hostif.
2127 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2131 struct ixgbe_hic_read_shadow_ram buffer;
2133 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2134 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2135 buffer.hdr.req.buf_lenh = 0;
2136 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2137 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2139 /* convert offset from words to bytes */
2140 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2142 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2144 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2146 IXGBE_HI_COMMAND_TIMEOUT, false);
2151 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2152 FW_NVM_DATA_OFFSET);
2158 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2159 * @hw: pointer to hardware structure
2160 * @offset: offset of word in the EEPROM to read
2161 * @data: word read from the EEPROM
2163 * Reads a 16 bit word from the EEPROM using the hostif.
2165 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2168 s32 status = IXGBE_SUCCESS;
2170 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2172 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2174 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2175 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2177 status = IXGBE_ERR_SWFW_SYNC;
2184 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2185 * @hw: pointer to hardware structure
2186 * @offset: offset of word in the EEPROM to read
2187 * @words: number of words
2188 * @data: word(s) read from the EEPROM
2190 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2192 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2193 u16 offset, u16 words, u16 *data)
2195 struct ixgbe_hic_read_shadow_ram buffer;
2196 u32 current_word = 0;
2201 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2203 /* Take semaphore for the entire operation. */
2204 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2206 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2210 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2211 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2213 words_to_read = words;
2215 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2216 buffer.hdr.req.buf_lenh = 0;
2217 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2218 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2220 /* convert offset from words to bytes */
2221 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2222 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2224 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2226 IXGBE_HI_COMMAND_TIMEOUT,
2230 DEBUGOUT("Host interface command failed\n");
2234 for (i = 0; i < words_to_read; i++) {
2235 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2237 u32 value = IXGBE_READ_REG(hw, reg);
2239 data[current_word] = (u16)(value & 0xffff);
2242 if (i < words_to_read) {
2244 data[current_word] = (u16)(value & 0xffff);
2248 words -= words_to_read;
2252 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2257 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2258 * @hw: pointer to hardware structure
2259 * @offset: offset of word in the EEPROM to write
2260 * @data: word write to the EEPROM
2262 * Write a 16 bit word to the EEPROM using the hostif.
2264 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2268 struct ixgbe_hic_write_shadow_ram buffer;
2270 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2272 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2273 buffer.hdr.req.buf_lenh = 0;
2274 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2275 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2278 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2280 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2282 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2284 IXGBE_HI_COMMAND_TIMEOUT, false);
2290 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2291 * @hw: pointer to hardware structure
2292 * @offset: offset of word in the EEPROM to write
2293 * @data: word write to the EEPROM
2295 * Write a 16 bit word to the EEPROM using the hostif.
2297 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2300 s32 status = IXGBE_SUCCESS;
2302 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2304 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2306 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2307 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2309 DEBUGOUT("write ee hostif failed to get semaphore");
2310 status = IXGBE_ERR_SWFW_SYNC;
2317 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2318 * @hw: pointer to hardware structure
2319 * @offset: offset of word in the EEPROM to write
2320 * @words: number of words
2321 * @data: word(s) write to the EEPROM
2323 * Write a 16 bit word(s) to the EEPROM using the hostif.
2325 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2326 u16 offset, u16 words, u16 *data)
2328 s32 status = IXGBE_SUCCESS;
2331 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2333 /* Take semaphore for the entire operation. */
2334 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2335 if (status != IXGBE_SUCCESS) {
2336 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2340 for (i = 0; i < words; i++) {
2341 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2344 if (status != IXGBE_SUCCESS) {
2345 DEBUGOUT("Eeprom buffered write failed\n");
2350 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2357 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2358 * @hw: pointer to hardware structure
2359 * @ptr: pointer offset in eeprom
2360 * @size: size of section pointed by ptr, if 0 first word will be used as size
2361 * @csum: address of checksum to update
2363 * Returns error status for any failure
2365 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2366 u16 size, u16 *csum, u16 *buffer,
2371 u16 length, bufsz, i, start;
2374 bufsz = sizeof(buf) / sizeof(buf[0]);
2376 /* Read a chunk at the pointer location */
2378 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2380 DEBUGOUT("Failed to read EEPROM image\n");
2385 if (buffer_size < ptr)
2386 return IXGBE_ERR_PARAM;
2387 local_buffer = &buffer[ptr];
2395 length = local_buffer[0];
2397 /* Skip pointer section if length is invalid. */
2398 if (length == 0xFFFF || length == 0 ||
2399 (ptr + length) >= hw->eeprom.word_size)
2400 return IXGBE_SUCCESS;
2403 if (buffer && ((u32)start + (u32)length > buffer_size))
2404 return IXGBE_ERR_PARAM;
2406 for (i = start; length; i++, length--) {
2407 if (i == bufsz && !buffer) {
2413 /* Read a chunk at the pointer location */
2414 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2417 DEBUGOUT("Failed to read EEPROM image\n");
2421 *csum += local_buffer[i];
2423 return IXGBE_SUCCESS;
2427 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2428 * @hw: pointer to hardware structure
2429 * @buffer: pointer to buffer containing calculated checksum
2430 * @buffer_size: size of buffer
2432 * Returns a negative error code on error, or the 16-bit checksum
2434 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2436 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2440 u16 pointer, i, size;
2442 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2444 hw->eeprom.ops.init_params(hw);
2447 /* Read pointer area */
2448 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2449 IXGBE_EEPROM_LAST_WORD + 1,
2452 DEBUGOUT("Failed to read EEPROM image\n");
2455 local_buffer = eeprom_ptrs;
2457 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2458 return IXGBE_ERR_PARAM;
2459 local_buffer = buffer;
2463 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2464 * checksum word itself
2466 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2467 if (i != IXGBE_EEPROM_CHECKSUM)
2468 checksum += local_buffer[i];
2471 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
2472 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2474 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2475 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2478 pointer = local_buffer[i];
2480 /* Skip pointer section if the pointer is invalid. */
2481 if (pointer == 0xFFFF || pointer == 0 ||
2482 pointer >= hw->eeprom.word_size)
2486 case IXGBE_PCIE_GENERAL_PTR:
2487 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2489 case IXGBE_PCIE_CONFIG0_PTR:
2490 case IXGBE_PCIE_CONFIG1_PTR:
2491 size = IXGBE_PCIE_CONFIG_SIZE;
2498 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2499 buffer, buffer_size);
2504 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2506 return (s32)checksum;
2510 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2511 * @hw: pointer to hardware structure
2513 * Returns a negative error code on error, or the 16-bit checksum
2515 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2517 return ixgbe_calc_checksum_X550(hw, NULL, 0);
2521 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2522 * @hw: pointer to hardware structure
2523 * @checksum_val: calculated checksum
2525 * Performs checksum calculation and validates the EEPROM checksum. If the
2526 * caller does not need checksum_val, the value can be NULL.
2528 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2532 u16 read_checksum = 0;
2534 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2536 /* Read the first word from the EEPROM. If this times out or fails, do
2537 * not continue or we could be in for a very long wait while every
2540 status = hw->eeprom.ops.read(hw, 0, &checksum);
2542 DEBUGOUT("EEPROM read failed\n");
2546 status = hw->eeprom.ops.calc_checksum(hw);
2550 checksum = (u16)(status & 0xffff);
2552 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2557 /* Verify read checksum from EEPROM is the same as
2558 * calculated checksum
2560 if (read_checksum != checksum) {
2561 status = IXGBE_ERR_EEPROM_CHECKSUM;
2562 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2563 "Invalid EEPROM checksum");
2566 /* If the user cares, return the calculated checksum */
2568 *checksum_val = checksum;
2574 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2575 * @hw: pointer to hardware structure
2577 * After writing EEPROM to shadow RAM using EEWR register, software calculates
2578 * checksum and updates the EEPROM and instructs the hardware to update
2581 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2586 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2588 /* Read the first word from the EEPROM. If this times out or fails, do
2589 * not continue or we could be in for a very long wait while every
2592 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2594 DEBUGOUT("EEPROM read failed\n");
2598 status = ixgbe_calc_eeprom_checksum_X550(hw);
2602 checksum = (u16)(status & 0xffff);
2604 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2609 status = ixgbe_update_flash_X550(hw);
2615 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2616 * @hw: pointer to hardware structure
2618 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2620 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2622 s32 status = IXGBE_SUCCESS;
2623 union ixgbe_hic_hdr2 buffer;
2625 DEBUGFUNC("ixgbe_update_flash_X550");
2627 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2628 buffer.req.buf_lenh = 0;
2629 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2630 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2632 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2634 IXGBE_HI_COMMAND_TIMEOUT, false);
2640 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2641 * @hw: pointer to hardware structure
2643 * Determines physical layer capabilities of the current configuration.
2645 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2647 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2648 u16 ext_ability = 0;
2650 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2652 hw->phy.ops.identify(hw);
2654 switch (hw->phy.type) {
2655 case ixgbe_phy_x550em_kr:
2656 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2657 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2659 case ixgbe_phy_x550em_kx4:
2660 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2661 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2663 case ixgbe_phy_x550em_ext_t:
2664 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2665 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2667 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2668 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2669 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2670 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2676 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2677 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2679 return physical_layer;
2683 * ixgbe_get_bus_info_x550em - Set PCI bus info
2684 * @hw: pointer to hardware structure
2686 * Sets bus link width and speed to unknown because X550em is
2689 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2692 DEBUGFUNC("ixgbe_get_bus_info_x550em");
2694 hw->bus.width = ixgbe_bus_width_unknown;
2695 hw->bus.speed = ixgbe_bus_speed_unknown;
2697 hw->mac.ops.set_lan_id(hw);
2699 return IXGBE_SUCCESS;
2703 * ixgbe_disable_rx_x550 - Disable RX unit
2705 * Enables the Rx DMA unit for x550
2707 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2709 u32 rxctrl, pfdtxgswc;
2711 struct ixgbe_hic_disable_rxen fw_cmd;
2713 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2715 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2716 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2717 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2718 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2719 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2720 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2721 hw->mac.set_lben = true;
2723 hw->mac.set_lben = false;
2726 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2727 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2728 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2729 fw_cmd.port_number = (u8)hw->bus.lan_id;
2731 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2732 sizeof(struct ixgbe_hic_disable_rxen),
2733 IXGBE_HI_COMMAND_TIMEOUT, true);
2735 /* If we fail - disable RX using register write */
2737 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2738 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2739 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2740 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2747 * ixgbe_enter_lplu_x550em - Transition to low power states
2748 * @hw: pointer to hardware structure
2750 * Configures Low Power Link Up on transition to low power states
2751 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2752 * X557 PHY immediately prior to entering LPLU.
2754 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2756 u16 an_10g_cntl_reg, autoneg_reg, speed;
2758 ixgbe_link_speed lcd_speed;
2762 /* SW LPLU not required on later HW revisions. */
2763 if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2764 return IXGBE_SUCCESS;
2766 /* If blocked by MNG FW, then don't restart AN */
2767 if (ixgbe_check_reset_blocked(hw))
2768 return IXGBE_SUCCESS;
2770 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2771 if (status != IXGBE_SUCCESS)
2774 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2776 if (status != IXGBE_SUCCESS)
2779 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2780 * disabled, then force link down by entering low power mode.
2782 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2783 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2784 return ixgbe_set_copper_phy_power(hw, FALSE);
2787 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2789 if (status != IXGBE_SUCCESS)
2792 /* If no valid LCD link speed, then force link down and exit. */
2793 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2794 return ixgbe_set_copper_phy_power(hw, FALSE);
2796 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2797 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2800 if (status != IXGBE_SUCCESS)
2803 /* If no link now, speed is invalid so take link down */
2804 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2805 if (status != IXGBE_SUCCESS)
2806 return ixgbe_set_copper_phy_power(hw, false);
2808 /* clear everything but the speed bits */
2809 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2811 /* If current speed is already LCD, then exit. */
2812 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2813 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2814 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2815 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2818 /* Clear AN completed indication */
2819 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2820 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2823 if (status != IXGBE_SUCCESS)
2826 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2827 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2830 if (status != IXGBE_SUCCESS)
2833 status = hw->phy.ops.read_reg(hw,
2834 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2835 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2838 if (status != IXGBE_SUCCESS)
2841 save_autoneg = hw->phy.autoneg_advertised;
2843 /* Setup link at least common link speed */
2844 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2846 /* restore autoneg from before setting lplu speed */
2847 hw->phy.autoneg_advertised = save_autoneg;
2853 * ixgbe_get_lcd_x550em - Determine lowest common denominator
2854 * @hw: pointer to hardware structure
2855 * @lcd_speed: pointer to lowest common link speed
2857 * Determine lowest common link speed with link partner.
2859 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2863 u16 word = hw->eeprom.ctrl_word_3;
2865 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2867 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2868 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2871 if (status != IXGBE_SUCCESS)
2874 /* If link partner advertised 1G, return 1G */
2875 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2876 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2880 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2881 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2882 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2885 /* Link partner not capable of lower speeds, return 10G */
2886 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2891 * ixgbe_setup_fc_X550em - Set up flow control
2892 * @hw: pointer to hardware structure
2894 * Called at init time to set up flow control.
2896 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2898 s32 ret_val = IXGBE_SUCCESS;
2899 u32 pause, asm_dir, reg_val;
2901 DEBUGFUNC("ixgbe_setup_fc_X550em");
2903 /* Validate the requested mode */
2904 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2905 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2906 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2907 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2911 /* 10gig parts do not have a word in the EEPROM to determine the
2912 * default flow control setting, so we explicitly set it to full.
2914 if (hw->fc.requested_mode == ixgbe_fc_default)
2915 hw->fc.requested_mode = ixgbe_fc_full;
2917 /* Determine PAUSE and ASM_DIR bits. */
2918 switch (hw->fc.requested_mode) {
2923 case ixgbe_fc_tx_pause:
2927 case ixgbe_fc_rx_pause:
2928 /* Rx Flow control is enabled and Tx Flow control is
2929 * disabled by software override. Since there really
2930 * isn't a way to advertise that we are capable of RX
2931 * Pause ONLY, we will advertise that we support both
2932 * symmetric and asymmetric Rx PAUSE, as such we fall
2933 * through to the fc_full statement. Later, we will
2934 * disable the adapter's ability to send PAUSE frames.
2941 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2942 "Flow control param set incorrectly\n");
2943 ret_val = IXGBE_ERR_CONFIG;
2947 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2948 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2949 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2950 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2951 if (ret_val != IXGBE_SUCCESS)
2953 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2954 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2956 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2958 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2959 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2960 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2961 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2963 /* This device does not fully support AN. */
2964 hw->fc.disable_fc_autoneg = true;
2972 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2973 * @hw: pointer to hardware structure
2974 * @state: set mux if 1, clear if 0
2976 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2980 if (!hw->bus.lan_id)
2982 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2984 esdp |= IXGBE_ESDP_SDP1;
2986 esdp &= ~IXGBE_ESDP_SDP1;
2987 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2988 IXGBE_WRITE_FLUSH(hw);
2992 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2993 * @hw: pointer to hardware structure
2994 * @mask: Mask to specify which semaphore to acquire
2996 * Acquires the SWFW semaphore and sets the I2C MUX
2998 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3002 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3004 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3008 if (mask & IXGBE_GSSR_I2C_MASK)
3009 ixgbe_set_mux(hw, 1);
3011 return IXGBE_SUCCESS;
3015 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3016 * @hw: pointer to hardware structure
3017 * @mask: Mask to specify which semaphore to release
3019 * Releases the SWFW semaphore and sets the I2C MUX
3021 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3023 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3025 if (mask & IXGBE_GSSR_I2C_MASK)
3026 ixgbe_set_mux(hw, 0);
3028 ixgbe_release_swfw_sync_X540(hw, mask);
3032 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3033 * @hw: pointer to hardware structure
3035 * Handle external Base T PHY interrupt. If high temperature
3036 * failure alarm then return error, else if link status change
3037 * then setup internal/external PHY link
3039 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3040 * failure alarm, else return PHY access status.
3042 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3047 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3049 if (status != IXGBE_SUCCESS)
3053 return ixgbe_setup_internal_phy(hw);
3055 return IXGBE_SUCCESS;
3059 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3060 * @hw: pointer to hardware structure
3061 * @speed: new link speed
3062 * @autoneg_wait_to_complete: true when waiting for completion is needed
3064 * Setup internal/external PHY link speed based on link speed, then set
3065 * external PHY auto advertised link speed.
3067 * Returns error status for any failure
3069 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3070 ixgbe_link_speed speed,
3071 bool autoneg_wait_to_complete)
3074 ixgbe_link_speed force_speed;
3076 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3078 /* Setup internal/external PHY link speed to iXFI (10G), unless
3079 * only 1G is auto advertised then setup KX link.
3081 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3082 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3084 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3086 /* If internal link mode is XFI, then setup XFI internal link. */
3087 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3088 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3090 if (status != IXGBE_SUCCESS)
3094 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3098 * ixgbe_check_link_t_X550em - Determine link and speed status
3099 * @hw: pointer to hardware structure
3100 * @speed: pointer to link speed
3101 * @link_up: true when link is up
3102 * @link_up_wait_to_complete: bool used to wait for link up or not
3104 * Check that both the MAC and X557 external PHY have link.
3106 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3107 bool *link_up, bool link_up_wait_to_complete)
3112 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3113 return IXGBE_ERR_CONFIG;
3115 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3116 link_up_wait_to_complete);
3118 /* If check link fails or MAC link is not up, then return */
3119 if (status != IXGBE_SUCCESS || !(*link_up))
3122 /* MAC link is up, so check external PHY link.
3123 * Read this twice back to back to indicate current status.
3125 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3126 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3129 if (status != IXGBE_SUCCESS)
3132 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3133 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3136 if (status != IXGBE_SUCCESS)
3139 /* If external PHY link is not up, then indicate link not up */
3140 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3143 return IXGBE_SUCCESS;
3147 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3148 * @hw: pointer to hardware structure
3150 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3154 status = ixgbe_reset_phy_generic(hw);
3156 if (status != IXGBE_SUCCESS)
3159 /* Configure Link Status Alarm and Temperature Threshold interrupts */
3160 return ixgbe_enable_lasi_ext_t_x550em(hw);
3164 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3165 * @hw: pointer to hardware structure
3166 * @led_idx: led number to turn on
3168 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3172 DEBUGFUNC("ixgbe_led_on_t_X550em");
3174 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3175 return IXGBE_ERR_PARAM;
3177 /* To turn on the LED, set mode to ON. */
3178 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3179 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3180 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3181 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3182 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3184 return IXGBE_SUCCESS;
3188 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3189 * @hw: pointer to hardware structure
3190 * @led_idx: led number to turn off
3192 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3196 DEBUGFUNC("ixgbe_led_off_t_X550em");
3198 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3199 return IXGBE_ERR_PARAM;
3201 /* To turn on the LED, set mode to ON. */
3202 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3203 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3204 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3205 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3206 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3208 return IXGBE_SUCCESS;