1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_interrupts.h>
15 #include <rte_debug.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_memcpy.h>
20 #include <rte_malloc.h>
21 #include <rte_random.h>
23 #include "base/ixgbe_common.h"
24 #include "ixgbe_ethdev.h"
25 #include "rte_pmd_ixgbe.h"
27 #define IXGBE_MAX_VFTA (128)
28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
32 static inline uint16_t
33 dev_num_vf(struct rte_eth_dev *eth_dev)
35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
37 return pci_dev->max_vfs;
41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
43 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
44 struct ixgbe_vf_info *vfinfo =
45 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
48 for (vfn = 0; vfn < vf_num; vfn++) {
49 eth_random_addr(vf_mac_addr);
50 /* keep the random address as default */
51 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
61 struct ixgbe_interrupt *intr =
62 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
64 intr->mask |= IXGBE_EICR_MAILBOX;
69 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
71 struct ixgbe_vf_info **vfinfo =
72 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
73 struct ixgbe_mirror_info *mirror_info =
74 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
75 struct ixgbe_uta_info *uta_info =
76 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
78 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
82 PMD_INIT_FUNC_TRACE();
84 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
85 vf_num = dev_num_vf(eth_dev);
89 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
91 rte_panic("Cannot allocate memory for private VF data\n");
93 rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id);
95 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
96 memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
97 hw->mac.mc_filter_type = 0;
99 if (vf_num >= ETH_32_POOLS) {
101 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
102 } else if (vf_num >= ETH_16_POOLS) {
104 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
107 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
110 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
111 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
112 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
114 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
116 /* init_mailbox_params */
117 hw->mbx.ops.init_params(hw);
119 /* set mb interrupt mask */
120 ixgbe_mb_intr_setup(eth_dev);
123 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
125 struct ixgbe_vf_info **vfinfo;
129 PMD_INIT_FUNC_TRACE();
131 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
133 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
134 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
135 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
136 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
138 ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id);
140 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
142 vf_num = dev_num_vf(eth_dev);
151 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
153 struct ixgbe_hw *hw =
154 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
155 struct ixgbe_filter_info *filter_info =
156 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
159 struct ixgbe_ethertype_filter ethertype_filter;
161 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
162 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
167 i = ixgbe_ethertype_filter_lookup(filter_info,
168 IXGBE_ETHERTYPE_FLOW_CTRL);
170 RTE_LOG(ERR, PMD, "A ether type filter"
171 " entity for flow control already exists!\n");
175 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
176 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
177 IXGBE_ETQF_TX_ANTISPOOF |
178 IXGBE_ETHERTYPE_FLOW_CTRL;
179 ethertype_filter.etqs = 0;
180 ethertype_filter.conf = TRUE;
181 i = ixgbe_ethertype_filter_insert(filter_info,
184 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
185 " entity for flow control.\n");
189 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
190 (IXGBE_ETQF_FILTER_EN |
191 IXGBE_ETQF_TX_ANTISPOOF |
192 IXGBE_ETHERTYPE_FLOW_CTRL));
194 vf_num = dev_num_vf(eth_dev);
195 for (i = 0; i < vf_num; i++)
196 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
199 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
201 uint32_t vtctl, fcrth;
202 uint32_t vfre_slot, vfre_offset;
204 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
205 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
207 uint32_t gpie, gcr_ext;
211 vf_num = dev_num_vf(eth_dev);
215 /* enable VMDq and set the default pool for PF */
216 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
217 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
218 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
219 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
220 << IXGBE_VT_CTL_POOL_SHIFT;
221 vtctl |= IXGBE_VT_CTL_REPLEN;
222 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
224 vfre_offset = vf_num & VFRE_MASK;
225 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
227 /* Enable pools reserved to PF only */
228 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
229 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
230 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
231 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
233 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
234 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
236 /* clear VMDq map to perment rar 0 */
237 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
239 /* clear VMDq map to scan rar 127 */
240 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
241 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
243 /* set VMDq map to default PF pool */
244 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
247 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
249 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
250 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
252 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
253 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
254 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
256 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
258 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
259 gpie |= IXGBE_GPIE_VTMODE_64;
262 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
263 gpie |= IXGBE_GPIE_VTMODE_32;
266 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
267 gpie |= IXGBE_GPIE_VTMODE_16;
271 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
272 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
275 * enable vlan filtering and allow all vlan tags through
277 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
278 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
279 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
281 /* VFTA - enable all vlan filters */
282 for (i = 0; i < IXGBE_MAX_VFTA; i++)
283 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
285 /* Enable MAC Anti-Spoofing */
286 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
288 /* set flow control threshold to max to avoid tx switch hang */
289 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
290 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
291 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
292 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
295 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
301 set_rx_mode(struct rte_eth_dev *dev)
303 struct rte_eth_dev_data *dev_data = dev->data;
304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
305 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
306 uint16_t vfn = dev_num_vf(dev);
308 /* Check for Promiscuous and All Multicast modes */
309 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
311 /* set all bits that we expect to always be set */
312 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
313 fctrl |= IXGBE_FCTRL_BAM;
315 /* clear the bits we are changing the status of */
316 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
318 if (dev_data->promiscuous) {
319 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
320 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
322 if (dev_data->all_multicast) {
323 fctrl |= IXGBE_FCTRL_MPE;
324 vmolr |= IXGBE_VMOLR_MPE;
326 vmolr |= IXGBE_VMOLR_ROMPE;
330 if (hw->mac.type != ixgbe_mac_82598EB) {
331 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
332 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
334 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
337 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
339 ixgbe_vlan_hw_strip_config(dev);
343 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
345 struct ixgbe_hw *hw =
346 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
347 struct ixgbe_vf_info *vfinfo =
348 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
349 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
350 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
352 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
353 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
354 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
356 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
358 /* reset multicast table array for vf */
359 vfinfo[vf].num_vf_mc_hashes = 0;
364 hw->mac.ops.clear_rar(hw, rar_entry);
368 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
372 uint32_t reg_offset, vf_shift;
373 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
374 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
375 uint8_t nb_q_per_pool;
378 vf_shift = vf & VFRE_MASK;
379 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
381 /* enable transmit for vf */
382 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
383 reg |= (reg | (1 << vf_shift));
384 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
386 /* enable all queue drop for IOV */
387 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
388 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
389 IXGBE_WRITE_FLUSH(hw);
390 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
391 reg |= i << IXGBE_QDE_IDX_SHIFT;
392 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
395 /* enable receive for vf */
396 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
397 reg |= (reg | (1 << vf_shift));
398 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
400 /* Enable counting of spoofed packets in the SSVPC register */
401 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
402 reg |= (1 << vf_shift);
403 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
405 ixgbe_vf_reset_event(dev, vf);
409 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
414 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
416 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf);
418 vmolr |= IXGBE_VMOLR_MPE;
420 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
426 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
428 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
431 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
433 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
435 vmolr &= ~IXGBE_VMOLR_MPE;
437 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
443 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
445 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
446 struct ixgbe_vf_info *vfinfo =
447 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
448 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
449 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
450 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
452 ixgbe_vf_reset_msg(dev, vf);
454 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
456 /* Disable multicast promiscuous at reset */
457 ixgbe_disable_vf_mc_promisc(dev, vf);
459 /* reply to reset with ack and vf mac address */
460 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
461 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
463 * Piggyback the multicast filter type so VF can compute the
466 msgbuf[3] = hw->mac.mc_filter_type;
467 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
473 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
476 struct ixgbe_vf_info *vfinfo =
477 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
478 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
479 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
481 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
482 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
483 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
489 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
491 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
492 struct ixgbe_vf_info *vfinfo =
493 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
494 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
495 IXGBE_VT_MSGINFO_SHIFT;
496 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
499 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
500 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
501 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
505 /* Disable multicast promiscuous first */
506 ixgbe_disable_vf_mc_promisc(dev, vf);
508 /* only so many hash values supported */
509 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
511 /* store the mc entries */
512 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
513 for (i = 0; i < nb_entries; i++) {
514 vfinfo->vf_mc_hashes[i] = hash_list[i];
517 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
518 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
519 & IXGBE_MTA_INDEX_MASK;
520 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
521 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
522 reg_val |= (1 << mta_shift);
523 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
530 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct ixgbe_vf_info *vfinfo =
535 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
537 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
538 >> IXGBE_VT_MSGINFO_SHIFT;
539 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
542 vfinfo[vf].vlan_count++;
543 else if (vfinfo[vf].vlan_count)
544 vfinfo[vf].vlan_count--;
545 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
549 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
552 uint32_t new_mtu = msgbuf[1];
554 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
556 /* X540 and X550 support jumbo frames in IOV mode */
557 if (hw->mac.type != ixgbe_mac_X540 &&
558 hw->mac.type != ixgbe_mac_X550 &&
559 hw->mac.type != ixgbe_mac_X550EM_x &&
560 hw->mac.type != ixgbe_mac_X550EM_a)
563 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
566 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
567 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
568 if (max_frs < new_mtu) {
569 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
570 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
577 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
579 uint32_t api_version = msgbuf[1];
580 struct ixgbe_vf_info *vfinfo =
581 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
583 switch (api_version) {
584 case ixgbe_mbox_api_10:
585 case ixgbe_mbox_api_11:
586 case ixgbe_mbox_api_12:
587 vfinfo[vf].api_version = (uint8_t)api_version;
593 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
600 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
602 struct ixgbe_vf_info *vfinfo =
603 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
604 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
605 struct rte_eth_conf *eth_conf;
606 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
610 #define IXGBE_VMVIR_VLANA_MASK 0xC0000000
611 #define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF
612 #define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000
613 #define VLAN_PRIO_SHIFT 13
618 /* Verify if the PF supports the mbox APIs version or not */
619 switch (vfinfo[vf].api_version) {
620 case ixgbe_mbox_api_20:
621 case ixgbe_mbox_api_11:
622 case ixgbe_mbox_api_12:
628 /* Notify VF of Rx and Tx queue number */
629 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
630 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
632 /* Notify VF of default queue */
633 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
635 /* Notify VF of number of DCB traffic classes */
636 eth_conf = &dev->data->dev_conf;
637 switch (eth_conf->txmode.mq_mode) {
640 RTE_LOG(ERR, PMD, "PF must work with virtualization for VF %u"
641 ", but its tx mode = %d\n", vf,
642 eth_conf->txmode.mq_mode);
645 case ETH_MQ_TX_VMDQ_DCB:
646 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf;
647 switch (vmdq_dcb_tx_conf->nb_queue_pools) {
659 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */
660 case ETH_MQ_TX_VMDQ_ONLY:
661 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
662 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
663 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
664 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
666 (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
667 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
668 ((vid != 0) || (user_priority != 0)))
675 RTE_LOG(ERR, PMD, "PF work with invalid mode = %d\n",
676 eth_conf->txmode.mq_mode);
679 msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
685 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
687 struct ixgbe_vf_info *vfinfo =
688 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
689 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */
691 switch (vfinfo[vf].api_version) {
692 case ixgbe_mbox_api_12:
699 return ixgbe_enable_vf_mc_promisc(dev, vf);
701 return ixgbe_disable_vf_mc_promisc(dev, vf);
705 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
707 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
708 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
709 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
711 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
712 struct ixgbe_vf_info *vfinfo =
713 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
714 struct rte_pmd_ixgbe_mb_event_param ret_param;
716 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
718 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
722 /* do nothing with the message already been processed */
723 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
726 /* flush the ack before we write any messages back */
727 IXGBE_WRITE_FLUSH(hw);
730 * initialise structure to send to user application
731 * will return response from user in retval field
733 ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
735 ret_param.msg_type = msgbuf[0] & 0xFFFF;
736 ret_param.msg = (void *)msgbuf;
738 /* perform VF reset */
739 if (msgbuf[0] == IXGBE_VF_RESET) {
740 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
742 vfinfo[vf].clear_to_send = true;
744 /* notify application about VF reset */
745 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
751 * ask user application if we allowed to perform those functions
752 * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
753 * then business as usual,
754 * if 0, do nothing and send ACK to VF
755 * if ret_param.retval > 1, do nothing and send NAK to VF
757 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
760 retval = ret_param.retval;
762 /* check & process VF to PF mailbox message */
763 switch ((msgbuf[0] & 0xFFFF)) {
764 case IXGBE_VF_SET_MAC_ADDR:
765 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
766 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
768 case IXGBE_VF_SET_MULTICAST:
769 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
770 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
772 case IXGBE_VF_SET_LPE:
773 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
774 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
776 case IXGBE_VF_SET_VLAN:
777 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
778 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
780 case IXGBE_VF_API_NEGOTIATE:
781 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
783 case IXGBE_VF_GET_QUEUES:
784 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
785 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
787 case IXGBE_VF_UPDATE_XCAST_MODE:
788 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
789 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
792 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
793 retval = IXGBE_ERR_MBX;
797 /* response the VF according to the message process result */
799 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
801 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
803 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
805 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
811 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
813 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
814 struct ixgbe_hw *hw =
815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
816 struct ixgbe_vf_info *vfinfo =
817 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
819 if (!vfinfo[vf].clear_to_send)
820 ixgbe_write_mbx(hw, &msg, 1, vf);
823 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
826 struct ixgbe_hw *hw =
827 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
829 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
830 /* check & process vf function level reset */
831 if (!ixgbe_check_for_rst(hw, vf))
832 ixgbe_vf_reset_event(eth_dev, vf);
834 /* check & process vf mailbox messages */
835 if (!ixgbe_check_for_msg(hw, vf))
836 ixgbe_rcv_msg_from_vf(eth_dev, vf);
838 /* check & process acks from vf */
839 if (!ixgbe_check_for_ack(hw, vf))
840 ixgbe_rcv_ack_from_vf(eth_dev, vf);