1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <ethdev_driver.h>
31 #include <ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIB_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
234 uint32_t timeout_ms);
236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
237 struct rte_ether_addr *mac_addr,
238 uint32_t index, uint32_t pool);
239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
241 struct rte_ether_addr *mac_addr);
242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
243 static bool is_device_supported(struct rte_eth_dev *dev,
244 struct rte_pci_driver *drv);
246 /* For Virtual Function support */
247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
250 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
252 int wait_to_complete);
253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
262 uint16_t vlan_id, int on);
263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
264 uint16_t queue, int on);
265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
273 uint8_t queue, uint8_t msix_vector);
274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 rte_ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
285 struct rte_eth_mirror_conf *mirror_conf,
286 uint8_t rule_id, uint8_t on);
287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
294 uint8_t queue, uint8_t msix_vector);
295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
298 struct rte_ether_addr *mac_addr,
299 uint32_t index, uint32_t pool);
300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
302 struct rte_ether_addr *mac_addr);
303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
304 struct ixgbe_5tuple_filter *filter);
305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
306 struct ixgbe_5tuple_filter *filter);
307 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
308 const struct rte_flow_ops **ops);
309 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
311 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
312 struct rte_ether_addr *mc_addr_set,
313 uint32_t nb_mc_addr);
314 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
315 struct rte_eth_dcb_info *dcb_info);
317 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
318 static int ixgbe_get_regs(struct rte_eth_dev *dev,
319 struct rte_dev_reg_info *regs);
320 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
321 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
322 struct rte_dev_eeprom_info *eeprom);
323 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
324 struct rte_dev_eeprom_info *eeprom);
326 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
327 struct rte_eth_dev_module_info *modinfo);
328 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
329 struct rte_dev_eeprom_info *info);
331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
333 struct rte_dev_reg_info *regs);
335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
338 struct timespec *timestamp,
340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
341 struct timespec *timestamp);
342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
344 struct timespec *timestamp);
345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
346 const struct timespec *timestamp);
347 static void ixgbevf_dev_interrupt_handler(void *param);
349 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
354 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
355 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
358 * Define VF Stats MACRO for Non "cleared on read" register
360 #define UPDATE_VF_STAT(reg, last, cur) \
362 uint32_t latest = IXGBE_READ_REG(hw, reg); \
363 cur += (latest - last) & UINT_MAX; \
367 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
369 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
370 u64 new_msb = IXGBE_READ_REG(hw, msb); \
371 u64 latest = ((new_msb << 32) | new_lsb); \
372 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
376 #define IXGBE_SET_HWSTRIP(h, q) do {\
377 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
378 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
379 (h)->bitmap[idx] |= 1 << bit;\
382 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
383 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
384 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
385 (h)->bitmap[idx] &= ~(1 << bit);\
388 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
389 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
390 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
391 (r) = (h)->bitmap[idx] >> bit & 1;\
395 * The set of PCI devices this driver supports
397 static const struct rte_pci_id pci_id_ixgbe_map[] = {
398 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
399 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
400 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
401 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
402 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
403 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
404 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
405 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
406 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
407 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
408 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
446 #ifdef RTE_LIBRTE_IXGBE_BYPASS
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
449 { .vendor_id = 0, /* sentinel */ },
453 * The set of PCI devices this driver supports (for 82599 VF)
455 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
466 { .vendor_id = 0, /* sentinel */ },
469 static const struct rte_eth_desc_lim rx_desc_lim = {
470 .nb_max = IXGBE_MAX_RING_DESC,
471 .nb_min = IXGBE_MIN_RING_DESC,
472 .nb_align = IXGBE_RXD_ALIGN,
475 static const struct rte_eth_desc_lim tx_desc_lim = {
476 .nb_max = IXGBE_MAX_RING_DESC,
477 .nb_min = IXGBE_MIN_RING_DESC,
478 .nb_align = IXGBE_TXD_ALIGN,
479 .nb_seg_max = IXGBE_TX_MAX_SEG,
480 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
483 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
484 .dev_configure = ixgbe_dev_configure,
485 .dev_start = ixgbe_dev_start,
486 .dev_stop = ixgbe_dev_stop,
487 .dev_set_link_up = ixgbe_dev_set_link_up,
488 .dev_set_link_down = ixgbe_dev_set_link_down,
489 .dev_close = ixgbe_dev_close,
490 .dev_reset = ixgbe_dev_reset,
491 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
492 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
493 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
494 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
495 .link_update = ixgbe_dev_link_update,
496 .stats_get = ixgbe_dev_stats_get,
497 .xstats_get = ixgbe_dev_xstats_get,
498 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
499 .stats_reset = ixgbe_dev_stats_reset,
500 .xstats_reset = ixgbe_dev_xstats_reset,
501 .xstats_get_names = ixgbe_dev_xstats_get_names,
502 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
503 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
504 .fw_version_get = ixgbe_fw_version_get,
505 .dev_infos_get = ixgbe_dev_info_get,
506 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
507 .mtu_set = ixgbe_dev_mtu_set,
508 .vlan_filter_set = ixgbe_vlan_filter_set,
509 .vlan_tpid_set = ixgbe_vlan_tpid_set,
510 .vlan_offload_set = ixgbe_vlan_offload_set,
511 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
512 .rx_queue_start = ixgbe_dev_rx_queue_start,
513 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
514 .tx_queue_start = ixgbe_dev_tx_queue_start,
515 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
516 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
517 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
518 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
519 .rx_queue_release = ixgbe_dev_rx_queue_release,
520 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
521 .tx_queue_release = ixgbe_dev_tx_queue_release,
522 .dev_led_on = ixgbe_dev_led_on,
523 .dev_led_off = ixgbe_dev_led_off,
524 .flow_ctrl_get = ixgbe_flow_ctrl_get,
525 .flow_ctrl_set = ixgbe_flow_ctrl_set,
526 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
527 .mac_addr_add = ixgbe_add_rar,
528 .mac_addr_remove = ixgbe_remove_rar,
529 .mac_addr_set = ixgbe_set_default_mac_addr,
530 .uc_hash_table_set = ixgbe_uc_hash_table_set,
531 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
532 .mirror_rule_set = ixgbe_mirror_rule_set,
533 .mirror_rule_reset = ixgbe_mirror_rule_reset,
534 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
535 .reta_update = ixgbe_dev_rss_reta_update,
536 .reta_query = ixgbe_dev_rss_reta_query,
537 .rss_hash_update = ixgbe_dev_rss_hash_update,
538 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
539 .flow_ops_get = ixgbe_dev_flow_ops_get,
540 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
541 .rxq_info_get = ixgbe_rxq_info_get,
542 .txq_info_get = ixgbe_txq_info_get,
543 .timesync_enable = ixgbe_timesync_enable,
544 .timesync_disable = ixgbe_timesync_disable,
545 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
546 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
547 .get_reg = ixgbe_get_regs,
548 .get_eeprom_length = ixgbe_get_eeprom_length,
549 .get_eeprom = ixgbe_get_eeprom,
550 .set_eeprom = ixgbe_set_eeprom,
551 .get_module_info = ixgbe_get_module_info,
552 .get_module_eeprom = ixgbe_get_module_eeprom,
553 .get_dcb_info = ixgbe_dev_get_dcb_info,
554 .timesync_adjust_time = ixgbe_timesync_adjust_time,
555 .timesync_read_time = ixgbe_timesync_read_time,
556 .timesync_write_time = ixgbe_timesync_write_time,
557 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
558 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
559 .tm_ops_get = ixgbe_tm_ops_get,
560 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
561 .get_monitor_addr = ixgbe_get_monitor_addr,
565 * dev_ops for virtual function, bare necessities for basic vf
566 * operation have been implemented
568 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
569 .dev_configure = ixgbevf_dev_configure,
570 .dev_start = ixgbevf_dev_start,
571 .dev_stop = ixgbevf_dev_stop,
572 .link_update = ixgbevf_dev_link_update,
573 .stats_get = ixgbevf_dev_stats_get,
574 .xstats_get = ixgbevf_dev_xstats_get,
575 .stats_reset = ixgbevf_dev_stats_reset,
576 .xstats_reset = ixgbevf_dev_stats_reset,
577 .xstats_get_names = ixgbevf_dev_xstats_get_names,
578 .dev_close = ixgbevf_dev_close,
579 .dev_reset = ixgbevf_dev_reset,
580 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
581 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
582 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
583 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
584 .dev_infos_get = ixgbevf_dev_info_get,
585 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
586 .mtu_set = ixgbevf_dev_set_mtu,
587 .vlan_filter_set = ixgbevf_vlan_filter_set,
588 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
589 .vlan_offload_set = ixgbevf_vlan_offload_set,
590 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
591 .rx_queue_release = ixgbe_dev_rx_queue_release,
592 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
593 .tx_queue_release = ixgbe_dev_tx_queue_release,
594 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
595 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
596 .mac_addr_add = ixgbevf_add_mac_addr,
597 .mac_addr_remove = ixgbevf_remove_mac_addr,
598 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
599 .rxq_info_get = ixgbe_rxq_info_get,
600 .txq_info_get = ixgbe_txq_info_get,
601 .mac_addr_set = ixgbevf_set_default_mac_addr,
602 .get_reg = ixgbevf_get_regs,
603 .reta_update = ixgbe_dev_rss_reta_update,
604 .reta_query = ixgbe_dev_rss_reta_query,
605 .rss_hash_update = ixgbe_dev_rss_hash_update,
606 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
607 .tx_done_cleanup = ixgbe_dev_tx_done_cleanup,
610 /* store statistics names and its offset in stats structure */
611 struct rte_ixgbe_xstats_name_off {
612 char name[RTE_ETH_XSTATS_NAME_SIZE];
616 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
617 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
618 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
619 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
620 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
621 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
622 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
623 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
624 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
625 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
626 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
627 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
628 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
629 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
630 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
631 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
633 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
635 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
636 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
637 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
638 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
639 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
640 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
641 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
642 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
643 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
644 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
645 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
646 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
647 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
648 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
649 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
650 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
651 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
653 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
655 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
656 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
657 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
658 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
660 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
662 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
664 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
666 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
668 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
670 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
673 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
674 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
675 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
677 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
678 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
679 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
680 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
681 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
683 {"rx_fcoe_no_direct_data_placement_ext_buff",
684 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
686 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
688 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
690 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
692 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
694 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
697 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
698 sizeof(rte_ixgbe_stats_strings[0]))
700 /* MACsec statistics */
701 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
702 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
704 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
705 out_pkts_encrypted)},
706 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
707 out_pkts_protected)},
708 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
709 out_octets_encrypted)},
710 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
711 out_octets_protected)},
712 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
714 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
716 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
718 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
719 in_pkts_unknownsci)},
720 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
721 in_octets_decrypted)},
722 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
723 in_octets_validated)},
724 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
726 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
728 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
730 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
732 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
734 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
736 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
738 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
739 in_pkts_notusingsa)},
742 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
743 sizeof(rte_ixgbe_macsec_strings[0]))
745 /* Per-queue statistics */
746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
747 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
748 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
749 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
750 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
753 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
754 sizeof(rte_ixgbe_rxq_strings[0]))
755 #define IXGBE_NB_RXQ_PRIO_VALUES 8
757 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
758 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
759 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
760 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
764 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
765 sizeof(rte_ixgbe_txq_strings[0]))
766 #define IXGBE_NB_TXQ_PRIO_VALUES 8
768 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
769 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
772 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
773 sizeof(rte_ixgbevf_stats_strings[0]))
776 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
779 ixgbe_is_sfp(struct ixgbe_hw *hw)
781 switch (hw->phy.type) {
782 case ixgbe_phy_sfp_avago:
783 case ixgbe_phy_sfp_ftl:
784 case ixgbe_phy_sfp_intel:
785 case ixgbe_phy_sfp_unknown:
786 case ixgbe_phy_sfp_passive_tyco:
787 case ixgbe_phy_sfp_passive_unknown:
794 static inline int32_t
795 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
800 status = ixgbe_reset_hw(hw);
802 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
803 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
804 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
805 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
806 IXGBE_WRITE_FLUSH(hw);
808 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
809 status = IXGBE_SUCCESS;
814 ixgbe_enable_intr(struct rte_eth_dev *dev)
816 struct ixgbe_interrupt *intr =
817 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
818 struct ixgbe_hw *hw =
819 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
821 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
822 IXGBE_WRITE_FLUSH(hw);
826 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
829 ixgbe_disable_intr(struct ixgbe_hw *hw)
831 PMD_INIT_FUNC_TRACE();
833 if (hw->mac.type == ixgbe_mac_82598EB) {
834 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
836 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
837 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
838 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
840 IXGBE_WRITE_FLUSH(hw);
844 * This function resets queue statistics mapping registers.
845 * From Niantic datasheet, Initialization of Statistics section:
846 * "...if software requires the queue counters, the RQSMR and TQSM registers
847 * must be re-programmed following a device reset.
850 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
854 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
855 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
856 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
862 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
867 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
868 #define NB_QMAP_FIELDS_PER_QSM_REG 4
869 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
872 struct ixgbe_stat_mapping_registers *stat_mappings =
873 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
874 uint32_t qsmr_mask = 0;
875 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
879 if ((hw->mac.type != ixgbe_mac_82599EB) &&
880 (hw->mac.type != ixgbe_mac_X540) &&
881 (hw->mac.type != ixgbe_mac_X550) &&
882 (hw->mac.type != ixgbe_mac_X550EM_x) &&
883 (hw->mac.type != ixgbe_mac_X550EM_a))
886 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
887 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
890 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
891 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
892 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
895 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
897 /* Now clear any previous stat_idx set */
898 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
900 stat_mappings->tqsm[n] &= ~clearing_mask;
902 stat_mappings->rqsmr[n] &= ~clearing_mask;
904 q_map = (uint32_t)stat_idx;
905 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
906 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
908 stat_mappings->tqsm[n] |= qsmr_mask;
910 stat_mappings->rqsmr[n] |= qsmr_mask;
912 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
913 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
915 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
916 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
918 /* Now write the mapping in the appropriate register */
920 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
921 stat_mappings->rqsmr[n], n);
922 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
924 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
925 stat_mappings->tqsm[n], n);
926 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
932 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
934 struct ixgbe_stat_mapping_registers *stat_mappings =
935 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
936 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 /* write whatever was in stat mapping table to the NIC */
940 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
942 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
950 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
953 struct ixgbe_dcb_tc_config *tc;
954 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
956 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
957 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
958 for (i = 0; i < dcb_max_tc; i++) {
959 tc = &dcb_config->tc_config[i];
960 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
961 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
962 (uint8_t)(100/dcb_max_tc + (i & 1));
963 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
964 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
965 (uint8_t)(100/dcb_max_tc + (i & 1));
966 tc->pfc = ixgbe_dcb_pfc_disabled;
969 /* Initialize default user to priority mapping, UPx->TC0 */
970 tc = &dcb_config->tc_config[0];
971 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
972 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
973 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
974 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
975 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
977 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
978 dcb_config->pfc_mode_enable = false;
979 dcb_config->vt_mode = true;
980 dcb_config->round_robin_enable = false;
981 /* support all DCB capabilities in 82599 */
982 dcb_config->support.capabilities = 0xFF;
984 /*we only support 4 Tcs for X540, X550 */
985 if (hw->mac.type == ixgbe_mac_X540 ||
986 hw->mac.type == ixgbe_mac_X550 ||
987 hw->mac.type == ixgbe_mac_X550EM_x ||
988 hw->mac.type == ixgbe_mac_X550EM_a) {
989 dcb_config->num_tcs.pg_tcs = 4;
990 dcb_config->num_tcs.pfc_tcs = 4;
995 * Ensure that all locks are released before first NVM or PHY access
998 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1003 * Phy lock should not fail in this early stage. If this is the case,
1004 * it is due to an improper exit of the application.
1005 * So force the release of the faulty lock. Release of common lock
1006 * is done automatically by swfw_sync function.
1008 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1009 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1010 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1012 ixgbe_release_swfw_semaphore(hw, mask);
1015 * These ones are more tricky since they are common to all ports; but
1016 * swfw_sync retries last long enough (1s) to be almost sure that if
1017 * lock can not be taken it is due to an improper lock of the
1020 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1021 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1022 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1024 ixgbe_release_swfw_semaphore(hw, mask);
1028 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1029 * It returns 0 on success.
1032 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1034 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1035 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1036 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1037 struct ixgbe_hw *hw =
1038 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1039 struct ixgbe_vfta *shadow_vfta =
1040 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1041 struct ixgbe_hwstrip *hwstrip =
1042 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1043 struct ixgbe_dcb_config *dcb_config =
1044 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1045 struct ixgbe_filter_info *filter_info =
1046 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1047 struct ixgbe_bw_conf *bw_conf =
1048 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1053 PMD_INIT_FUNC_TRACE();
1055 ixgbe_dev_macsec_setting_reset(eth_dev);
1057 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1058 eth_dev->rx_queue_count = ixgbe_dev_rx_queue_count;
1059 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1060 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1061 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1062 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1063 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1064 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1067 * For secondary processes, we don't initialise any further as primary
1068 * has already done this work. Only check we don't need a different
1069 * RX and TX function.
1071 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1072 struct ixgbe_tx_queue *txq;
1073 /* TX queue function in primary, set by last queue initialized
1074 * Tx queue may not initialized by primary process
1076 if (eth_dev->data->tx_queues) {
1077 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1078 ixgbe_set_tx_function(eth_dev, txq);
1080 /* Use default TX function if we get here */
1081 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1082 "Using default TX function.");
1085 ixgbe_set_rx_function(eth_dev);
1090 rte_atomic32_clear(&ad->link_thread_running);
1091 rte_eth_copy_pci_info(eth_dev, pci_dev);
1092 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1094 /* Vendor and Device ID need to be set before init of shared code */
1095 hw->device_id = pci_dev->id.device_id;
1096 hw->vendor_id = pci_dev->id.vendor_id;
1097 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1098 hw->allow_unsupported_sfp = 1;
1100 /* Initialize the shared code (base driver) */
1101 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1102 diag = ixgbe_bypass_init_shared_code(hw);
1104 diag = ixgbe_init_shared_code(hw);
1105 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1107 if (diag != IXGBE_SUCCESS) {
1108 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1112 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1113 PMD_INIT_LOG(ERR, "\nERROR: "
1114 "Firmware recovery mode detected. Limiting functionality.\n"
1115 "Refer to the Intel(R) Ethernet Adapters and Devices "
1116 "User Guide for details on firmware recovery mode.");
1120 /* pick up the PCI bus settings for reporting later */
1121 ixgbe_get_bus_info(hw);
1123 /* Unlock any pending hardware semaphore */
1124 ixgbe_swfw_lock_reset(hw);
1126 #ifdef RTE_LIB_SECURITY
1127 /* Initialize security_ctx only for primary process*/
1128 if (ixgbe_ipsec_ctx_create(eth_dev))
1132 /* Initialize DCB configuration*/
1133 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1134 ixgbe_dcb_init(hw, dcb_config);
1135 /* Get Hardware Flow Control setting */
1136 hw->fc.requested_mode = ixgbe_fc_none;
1137 hw->fc.current_mode = ixgbe_fc_none;
1138 hw->fc.pause_time = IXGBE_FC_PAUSE;
1139 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1140 hw->fc.low_water[i] = IXGBE_FC_LO;
1141 hw->fc.high_water[i] = IXGBE_FC_HI;
1143 hw->fc.send_xon = 1;
1145 /* Make sure we have a good EEPROM before we read from it */
1146 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1147 if (diag != IXGBE_SUCCESS) {
1148 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1152 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1153 diag = ixgbe_bypass_init_hw(hw);
1155 diag = ixgbe_init_hw(hw);
1156 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1160 * is called too soon after the kernel driver unbinding/binding occurs.
1161 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1162 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1163 * also called. See ixgbe_identify_phy_82599(). The reason for the
1164 * failure is not known, and only occuts when virtualisation features
1165 * are disabled in the bios. A delay of 100ms was found to be enough by
1166 * trial-and-error, and is doubled to be safe.
1168 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170 diag = ixgbe_init_hw(hw);
1173 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1174 diag = IXGBE_SUCCESS;
1176 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1177 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1178 "LOM. Please be aware there may be issues associated "
1179 "with your hardware.");
1180 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1181 "please contact your Intel or hardware representative "
1182 "who provided you with this hardware.");
1183 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1184 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1190 /* Reset the hw statistics */
1191 ixgbe_dev_stats_reset(eth_dev);
1193 /* disable interrupt */
1194 ixgbe_disable_intr(hw);
1196 /* reset mappings for queue statistics hw counters*/
1197 ixgbe_reset_qstat_mappings(hw);
1199 /* Allocate memory for storing MAC addresses */
1200 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1201 hw->mac.num_rar_entries, 0);
1202 if (eth_dev->data->mac_addrs == NULL) {
1204 "Failed to allocate %u bytes needed to store "
1206 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209 /* Copy the permanent MAC address */
1210 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1211 ð_dev->data->mac_addrs[0]);
1213 /* Allocate memory for storing hash filter MAC addresses */
1214 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1215 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1216 if (eth_dev->data->hash_mac_addrs == NULL) {
1218 "Failed to allocate %d bytes needed to store MAC addresses",
1219 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1223 /* initialize the vfta */
1224 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226 /* initialize the hw strip bitmap*/
1227 memset(hwstrip, 0, sizeof(*hwstrip));
1229 /* initialize PF if max_vfs not zero */
1230 ret = ixgbe_pf_host_init(eth_dev);
1232 rte_free(eth_dev->data->mac_addrs);
1233 eth_dev->data->mac_addrs = NULL;
1234 rte_free(eth_dev->data->hash_mac_addrs);
1235 eth_dev->data->hash_mac_addrs = NULL;
1239 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1240 /* let hardware know driver is loaded */
1241 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1242 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1243 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1244 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1245 IXGBE_WRITE_FLUSH(hw);
1247 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1248 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1249 (int) hw->mac.type, (int) hw->phy.type,
1250 (int) hw->phy.sfp_type);
1252 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1253 (int) hw->mac.type, (int) hw->phy.type);
1255 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1256 eth_dev->data->port_id, pci_dev->id.vendor_id,
1257 pci_dev->id.device_id);
1259 rte_intr_callback_register(intr_handle,
1260 ixgbe_dev_interrupt_handler, eth_dev);
1262 /* enable uio/vfio intr/eventfd mapping */
1263 rte_intr_enable(intr_handle);
1265 /* enable support intr */
1266 ixgbe_enable_intr(eth_dev);
1268 /* initialize filter info */
1269 memset(filter_info, 0,
1270 sizeof(struct ixgbe_filter_info));
1272 /* initialize 5tuple filter list */
1273 TAILQ_INIT(&filter_info->fivetuple_list);
1275 /* initialize flow director filter list & hash */
1276 ixgbe_fdir_filter_init(eth_dev);
1278 /* initialize l2 tunnel filter list & hash */
1279 ixgbe_l2_tn_filter_init(eth_dev);
1281 /* initialize flow filter lists */
1282 ixgbe_filterlist_init();
1284 /* initialize bandwidth configuration info */
1285 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1287 /* initialize Traffic Manager configuration */
1288 ixgbe_tm_conf_init(eth_dev);
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1296 PMD_INIT_FUNC_TRACE();
1298 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1301 ixgbe_dev_close(eth_dev);
1306 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1308 struct ixgbe_filter_info *filter_info =
1309 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1310 struct ixgbe_5tuple_filter *p_5tuple;
1312 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1313 TAILQ_REMOVE(&filter_info->fivetuple_list,
1318 memset(filter_info->fivetuple_mask, 0,
1319 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1324 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1326 struct ixgbe_hw_fdir_info *fdir_info =
1327 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1328 struct ixgbe_fdir_filter *fdir_filter;
1330 if (fdir_info->hash_map)
1331 rte_free(fdir_info->hash_map);
1332 if (fdir_info->hash_handle)
1333 rte_hash_free(fdir_info->hash_handle);
1335 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1336 TAILQ_REMOVE(&fdir_info->fdir_list,
1339 rte_free(fdir_filter);
1345 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1347 struct ixgbe_l2_tn_info *l2_tn_info =
1348 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1349 struct ixgbe_l2_tn_filter *l2_tn_filter;
1351 if (l2_tn_info->hash_map)
1352 rte_free(l2_tn_info->hash_map);
1353 if (l2_tn_info->hash_handle)
1354 rte_hash_free(l2_tn_info->hash_handle);
1356 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1357 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1360 rte_free(l2_tn_filter);
1366 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1368 struct ixgbe_hw_fdir_info *fdir_info =
1369 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1370 char fdir_hash_name[RTE_HASH_NAMESIZE];
1371 struct rte_hash_parameters fdir_hash_params = {
1372 .name = fdir_hash_name,
1373 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1374 .key_len = sizeof(union ixgbe_atr_input),
1375 .hash_func = rte_hash_crc,
1376 .hash_func_init_val = 0,
1377 .socket_id = rte_socket_id(),
1380 TAILQ_INIT(&fdir_info->fdir_list);
1381 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1382 "fdir_%s", eth_dev->device->name);
1383 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1384 if (!fdir_info->hash_handle) {
1385 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1388 fdir_info->hash_map = rte_zmalloc("ixgbe",
1389 sizeof(struct ixgbe_fdir_filter *) *
1390 IXGBE_MAX_FDIR_FILTER_NUM,
1392 if (!fdir_info->hash_map) {
1394 "Failed to allocate memory for fdir hash map!");
1397 fdir_info->mask_added = FALSE;
1402 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1404 struct ixgbe_l2_tn_info *l2_tn_info =
1405 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1406 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1407 struct rte_hash_parameters l2_tn_hash_params = {
1408 .name = l2_tn_hash_name,
1409 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1410 .key_len = sizeof(struct ixgbe_l2_tn_key),
1411 .hash_func = rte_hash_crc,
1412 .hash_func_init_val = 0,
1413 .socket_id = rte_socket_id(),
1416 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1417 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1418 "l2_tn_%s", eth_dev->device->name);
1419 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1420 if (!l2_tn_info->hash_handle) {
1421 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1424 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1425 sizeof(struct ixgbe_l2_tn_filter *) *
1426 IXGBE_MAX_L2_TN_FILTER_NUM,
1428 if (!l2_tn_info->hash_map) {
1430 "Failed to allocate memory for L2 TN hash map!");
1433 l2_tn_info->e_tag_en = FALSE;
1434 l2_tn_info->e_tag_fwd_en = FALSE;
1435 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1440 * Negotiate mailbox API version with the PF.
1441 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1442 * Then we try to negotiate starting with the most recent one.
1443 * If all negotiation attempts fail, then we will proceed with
1444 * the default one (ixgbe_mbox_api_10).
1447 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1451 /* start with highest supported, proceed down */
1452 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1460 i != RTE_DIM(sup_ver) &&
1461 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1467 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1471 /* Set Organizationally Unique Identifier (OUI) prefix. */
1472 mac_addr->addr_bytes[0] = 0x00;
1473 mac_addr->addr_bytes[1] = 0x09;
1474 mac_addr->addr_bytes[2] = 0xC0;
1475 /* Force indication of locally assigned MAC address. */
1476 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1477 /* Generate the last 3 bytes of the MAC address with a random number. */
1478 random = rte_rand();
1479 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1483 devarg_handle_int(__rte_unused const char *key, const char *value,
1486 uint16_t *n = extra_args;
1488 if (value == NULL || extra_args == NULL)
1491 *n = (uint16_t)strtoul(value, NULL, 0);
1492 if (*n == USHRT_MAX && errno == ERANGE)
1499 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1500 struct rte_devargs *devargs)
1502 struct rte_kvargs *kvlist;
1503 uint16_t pflink_fullchk;
1505 if (devargs == NULL)
1508 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1512 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1513 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1514 devarg_handle_int, &pflink_fullchk) == 0 &&
1515 pflink_fullchk == 1)
1516 adapter->pflink_fullchk = 1;
1518 rte_kvargs_free(kvlist);
1522 * Virtual Function device init
1525 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1529 struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1530 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1531 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1532 struct ixgbe_hw *hw =
1533 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1534 struct ixgbe_vfta *shadow_vfta =
1535 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1536 struct ixgbe_hwstrip *hwstrip =
1537 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1538 struct rte_ether_addr *perm_addr =
1539 (struct rte_ether_addr *)hw->mac.perm_addr;
1541 PMD_INIT_FUNC_TRACE();
1543 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1544 eth_dev->rx_descriptor_done = ixgbe_dev_rx_descriptor_done;
1545 eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1546 eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1547 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1548 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1550 /* for secondary processes, we don't initialise any further as primary
1551 * has already done this work. Only check we don't need a different
1554 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1555 struct ixgbe_tx_queue *txq;
1556 /* TX queue function in primary, set by last queue initialized
1557 * Tx queue may not initialized by primary process
1559 if (eth_dev->data->tx_queues) {
1560 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1561 ixgbe_set_tx_function(eth_dev, txq);
1563 /* Use default TX function if we get here */
1564 PMD_INIT_LOG(NOTICE,
1565 "No TX queues configured yet. Using default TX function.");
1568 ixgbe_set_rx_function(eth_dev);
1573 rte_atomic32_clear(&ad->link_thread_running);
1574 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1575 pci_dev->device.devargs);
1577 rte_eth_copy_pci_info(eth_dev, pci_dev);
1578 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1580 hw->device_id = pci_dev->id.device_id;
1581 hw->vendor_id = pci_dev->id.vendor_id;
1582 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584 /* initialize the vfta */
1585 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587 /* initialize the hw strip bitmap*/
1588 memset(hwstrip, 0, sizeof(*hwstrip));
1590 /* Initialize the shared code (base driver) */
1591 diag = ixgbe_init_shared_code(hw);
1592 if (diag != IXGBE_SUCCESS) {
1593 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1597 /* init_mailbox_params */
1598 hw->mbx.ops.init_params(hw);
1600 /* Reset the hw statistics */
1601 ixgbevf_dev_stats_reset(eth_dev);
1603 /* Disable the interrupts for VF */
1604 ixgbevf_intr_disable(eth_dev);
1606 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1607 diag = hw->mac.ops.reset_hw(hw);
1610 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1611 * the underlying PF driver has not assigned a MAC address to the VF.
1612 * In this case, assign a random MAC address.
1614 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1615 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617 * This error code will be propagated to the app by
1618 * rte_eth_dev_reset, so use a public error code rather than
1619 * the internal-only IXGBE_ERR_RESET_FAILED
1624 /* negotiate mailbox API version to use with the PF. */
1625 ixgbevf_negotiate_api(hw);
1627 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628 ixgbevf_get_queues(hw, &tcs, &tc);
1630 /* Allocate memory for storing MAC addresses */
1631 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1632 hw->mac.num_rar_entries, 0);
1633 if (eth_dev->data->mac_addrs == NULL) {
1635 "Failed to allocate %u bytes needed to store "
1637 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1641 /* Generate a random MAC address, if none was assigned by PF. */
1642 if (rte_is_zero_ether_addr(perm_addr)) {
1643 generate_random_mac_addr(perm_addr);
1644 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646 rte_free(eth_dev->data->mac_addrs);
1647 eth_dev->data->mac_addrs = NULL;
1650 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652 "%02x:%02x:%02x:%02x:%02x:%02x",
1653 perm_addr->addr_bytes[0],
1654 perm_addr->addr_bytes[1],
1655 perm_addr->addr_bytes[2],
1656 perm_addr->addr_bytes[3],
1657 perm_addr->addr_bytes[4],
1658 perm_addr->addr_bytes[5]);
1661 /* Copy the permanent MAC address */
1662 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1664 /* reset the hardware with the new settings */
1665 diag = hw->mac.ops.start_hw(hw);
1671 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1675 rte_intr_callback_register(intr_handle,
1676 ixgbevf_dev_interrupt_handler, eth_dev);
1677 rte_intr_enable(intr_handle);
1678 ixgbevf_intr_enable(eth_dev);
1680 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681 eth_dev->data->port_id, pci_dev->id.vendor_id,
1682 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1687 /* Virtual Function device uninit */
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 PMD_INIT_FUNC_TRACE();
1694 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1697 ixgbevf_dev_close(eth_dev);
1703 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1704 struct rte_pci_device *pci_dev)
1706 char name[RTE_ETH_NAME_MAX_LEN];
1707 struct rte_eth_dev *pf_ethdev;
1708 struct rte_eth_devargs eth_da;
1711 if (pci_dev->device.devargs) {
1712 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1717 memset(ð_da, 0, sizeof(eth_da));
1719 if (eth_da.nb_representor_ports > 0 &&
1720 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1721 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1722 pci_dev->device.devargs->args);
1726 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1727 sizeof(struct ixgbe_adapter),
1728 eth_dev_pci_specific_init, pci_dev,
1729 eth_ixgbe_dev_init, NULL);
1731 if (retval || eth_da.nb_representor_ports < 1)
1734 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1735 if (pf_ethdev == NULL)
1738 /* probe VF representor ports */
1739 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1740 struct ixgbe_vf_info *vfinfo;
1741 struct ixgbe_vf_representor representor;
1743 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1744 pf_ethdev->data->dev_private);
1745 if (vfinfo == NULL) {
1747 "no virtual functions supported by PF");
1751 representor.vf_id = eth_da.representor_ports[i];
1752 representor.switch_domain_id = vfinfo->switch_domain_id;
1753 representor.pf_ethdev = pf_ethdev;
1755 /* representor port net_bdf_port */
1756 snprintf(name, sizeof(name), "net_%s_representor_%d",
1757 pci_dev->device.name,
1758 eth_da.representor_ports[i]);
1760 retval = rte_eth_dev_create(&pci_dev->device, name,
1761 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1762 ixgbe_vf_representor_init, &representor);
1765 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1766 "representor %s.", name);
1772 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1774 struct rte_eth_dev *ethdev;
1776 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1780 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1781 return rte_eth_dev_pci_generic_remove(pci_dev,
1782 ixgbe_vf_representor_uninit);
1784 return rte_eth_dev_pci_generic_remove(pci_dev,
1785 eth_ixgbe_dev_uninit);
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789 .id_table = pci_id_ixgbe_map,
1790 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1791 .probe = eth_ixgbe_pci_probe,
1792 .remove = eth_ixgbe_pci_remove,
1795 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1796 struct rte_pci_device *pci_dev)
1798 return rte_eth_dev_pci_generic_probe(pci_dev,
1799 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1802 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1804 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1808 * virtual function driver struct
1810 static struct rte_pci_driver rte_ixgbevf_pmd = {
1811 .id_table = pci_id_ixgbevf_map,
1812 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1813 .probe = eth_ixgbevf_pci_probe,
1814 .remove = eth_ixgbevf_pci_remove,
1818 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1820 struct ixgbe_hw *hw =
1821 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822 struct ixgbe_vfta *shadow_vfta =
1823 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1828 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1829 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1830 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1835 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1837 /* update local VFTA copy */
1838 shadow_vfta->vfta[vid_idx] = vfta;
1844 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1847 ixgbe_vlan_hw_strip_enable(dev, queue);
1849 ixgbe_vlan_hw_strip_disable(dev, queue);
1853 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1854 enum rte_vlan_type vlan_type,
1857 struct ixgbe_hw *hw =
1858 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864 qinq &= IXGBE_DMATXCTL_GDV;
1866 switch (vlan_type) {
1867 case ETH_VLAN_TYPE_INNER:
1869 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1878 PMD_DRV_LOG(ERR, "Inner type is not supported"
1882 case ETH_VLAN_TYPE_OUTER:
1884 /* Only the high 16-bits is valid */
1885 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1886 IXGBE_EXVET_VET_EXT_SHIFT);
1888 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1889 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1890 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1891 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1893 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1894 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1900 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1908 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1910 struct ixgbe_hw *hw =
1911 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914 PMD_INIT_FUNC_TRACE();
1916 /* Filter Table Disable */
1917 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1920 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1924 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1926 struct ixgbe_hw *hw =
1927 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 struct ixgbe_vfta *shadow_vfta =
1929 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1933 PMD_INIT_FUNC_TRACE();
1935 /* Filter Table Enable */
1936 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1937 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1938 vlnctrl |= IXGBE_VLNCTRL_VFE;
1940 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1942 /* write whatever is in local vfta copy */
1943 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1944 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1948 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1950 struct ixgbe_hwstrip *hwstrip =
1951 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1952 struct ixgbe_rx_queue *rxq;
1954 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1958 IXGBE_SET_HWSTRIP(hwstrip, queue);
1960 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1962 if (queue >= dev->data->nb_rx_queues)
1965 rxq = dev->data->rx_queues[queue];
1968 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1969 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1971 rxq->vlan_flags = PKT_RX_VLAN;
1972 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 struct ixgbe_hw *hw =
1980 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983 PMD_INIT_FUNC_TRACE();
1985 if (hw->mac.type == ixgbe_mac_82598EB) {
1986 /* No queue level support */
1987 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1991 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993 ctrl &= ~IXGBE_RXDCTL_VME;
1994 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996 /* record those setting for HW strip per queue */
1997 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 struct ixgbe_hw *hw =
2004 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007 PMD_INIT_FUNC_TRACE();
2009 if (hw->mac.type == ixgbe_mac_82598EB) {
2010 /* No queue level supported */
2011 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2015 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017 ctrl |= IXGBE_RXDCTL_VME;
2018 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020 /* record those setting for HW strip per queue */
2021 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2025 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031 PMD_INIT_FUNC_TRACE();
2033 /* DMATXCTRL: Geric Double VLAN Disable */
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2035 ctrl &= ~IXGBE_DMATXCTL_GDV;
2036 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2038 /* CTRL_EXT: Global Double VLAN Disable */
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2040 ctrl &= ~IXGBE_EXTENDED_VLAN;
2041 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2046 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2048 struct ixgbe_hw *hw =
2049 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052 PMD_INIT_FUNC_TRACE();
2054 /* DMATXCTRL: Geric Double VLAN Enable */
2055 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056 ctrl |= IXGBE_DMATXCTL_GDV;
2057 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059 /* CTRL_EXT: Global Double VLAN Enable */
2060 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061 ctrl |= IXGBE_EXTENDED_VLAN;
2062 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2064 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2065 if (hw->mac.type == ixgbe_mac_X550 ||
2066 hw->mac.type == ixgbe_mac_X550EM_x ||
2067 hw->mac.type == ixgbe_mac_X550EM_a) {
2068 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2069 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2070 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2074 * VET EXT field in the EXVET register = 0x8100 by default
2075 * So no need to change. Same to VT field of DMATXCTL register
2080 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2082 struct ixgbe_hw *hw =
2083 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2087 struct ixgbe_rx_queue *rxq;
2090 PMD_INIT_FUNC_TRACE();
2092 if (hw->mac.type == ixgbe_mac_82598EB) {
2093 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2094 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2095 ctrl |= IXGBE_VLNCTRL_VME;
2096 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2098 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2099 ctrl &= ~IXGBE_VLNCTRL_VME;
2100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104 * Other 10G NIC, the VLAN strip can be setup
2105 * per queue in RXDCTL
2107 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2108 rxq = dev->data->rx_queues[i];
2109 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2110 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2111 ctrl |= IXGBE_RXDCTL_VME;
2114 ctrl &= ~IXGBE_RXDCTL_VME;
2117 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2119 /* record those setting for HW strip per queue */
2120 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2126 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2129 struct rte_eth_rxmode *rxmode;
2130 struct ixgbe_rx_queue *rxq;
2132 if (mask & ETH_VLAN_STRIP_MASK) {
2133 rxmode = &dev->data->dev_conf.rxmode;
2134 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2135 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2136 rxq = dev->data->rx_queues[i];
2137 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2140 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2141 rxq = dev->data->rx_queues[i];
2142 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2148 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2150 struct rte_eth_rxmode *rxmode;
2151 rxmode = &dev->data->dev_conf.rxmode;
2153 if (mask & ETH_VLAN_STRIP_MASK) {
2154 ixgbe_vlan_hw_strip_config(dev);
2157 if (mask & ETH_VLAN_FILTER_MASK) {
2158 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2159 ixgbe_vlan_hw_filter_enable(dev);
2161 ixgbe_vlan_hw_filter_disable(dev);
2164 if (mask & ETH_VLAN_EXTEND_MASK) {
2165 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2166 ixgbe_vlan_hw_extend_enable(dev);
2168 ixgbe_vlan_hw_extend_disable(dev);
2175 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2177 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2179 ixgbe_vlan_offload_config(dev, mask);
2185 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2187 struct ixgbe_hw *hw =
2188 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2190 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2192 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2193 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2197 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2199 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2204 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2207 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2213 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2214 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2215 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2216 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2221 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2223 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2226 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2228 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2229 /* check multi-queue mode */
2230 switch (dev_conf->rxmode.mq_mode) {
2231 case ETH_MQ_RX_VMDQ_DCB:
2232 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2234 case ETH_MQ_RX_VMDQ_DCB_RSS:
2235 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2236 PMD_INIT_LOG(ERR, "SRIOV active,"
2237 " unsupported mq_mode rx %d.",
2238 dev_conf->rxmode.mq_mode);
2241 case ETH_MQ_RX_VMDQ_RSS:
2242 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2243 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2244 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2245 PMD_INIT_LOG(ERR, "SRIOV is active,"
2246 " invalid queue number"
2247 " for VMDQ RSS, allowed"
2248 " value are 1, 2 or 4.");
2252 case ETH_MQ_RX_VMDQ_ONLY:
2253 case ETH_MQ_RX_NONE:
2254 /* if nothing mq mode configure, use default scheme */
2255 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2257 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2258 /* SRIOV only works in VMDq enable mode */
2259 PMD_INIT_LOG(ERR, "SRIOV is active,"
2260 " wrong mq_mode rx %d.",
2261 dev_conf->rxmode.mq_mode);
2265 switch (dev_conf->txmode.mq_mode) {
2266 case ETH_MQ_TX_VMDQ_DCB:
2267 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2268 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2270 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2271 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2275 /* check valid queue number */
2276 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2277 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2278 PMD_INIT_LOG(ERR, "SRIOV is active,"
2279 " nb_rx_q=%d nb_tx_q=%d queue number"
2280 " must be less than or equal to %d.",
2282 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2286 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2287 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2291 /* check configuration for vmdb+dcb mode */
2292 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2293 const struct rte_eth_vmdq_dcb_conf *conf;
2295 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2296 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2297 IXGBE_VMDQ_DCB_NB_QUEUES);
2300 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2301 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2302 conf->nb_queue_pools == ETH_32_POOLS)) {
2303 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2304 " nb_queue_pools must be %d or %d.",
2305 ETH_16_POOLS, ETH_32_POOLS);
2309 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2310 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2312 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2313 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2314 IXGBE_VMDQ_DCB_NB_QUEUES);
2317 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2318 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2319 conf->nb_queue_pools == ETH_32_POOLS)) {
2320 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2321 " nb_queue_pools != %d and"
2322 " nb_queue_pools != %d.",
2323 ETH_16_POOLS, ETH_32_POOLS);
2328 /* For DCB mode check our configuration before we go further */
2329 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2330 const struct rte_eth_dcb_rx_conf *conf;
2332 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2333 if (!(conf->nb_tcs == ETH_4_TCS ||
2334 conf->nb_tcs == ETH_8_TCS)) {
2335 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2336 " and nb_tcs != %d.",
2337 ETH_4_TCS, ETH_8_TCS);
2342 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2343 const struct rte_eth_dcb_tx_conf *conf;
2345 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2346 if (!(conf->nb_tcs == ETH_4_TCS ||
2347 conf->nb_tcs == ETH_8_TCS)) {
2348 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349 " and nb_tcs != %d.",
2350 ETH_4_TCS, ETH_8_TCS);
2356 * When DCB/VT is off, maximum number of queues changes,
2357 * except for 82598EB, which remains constant.
2359 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2360 hw->mac.type != ixgbe_mac_82598EB) {
2361 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2363 "Neither VT nor DCB are enabled, "
2365 IXGBE_NONE_MODE_TX_NB_QUEUES);
2374 ixgbe_dev_configure(struct rte_eth_dev *dev)
2376 struct ixgbe_interrupt *intr =
2377 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2378 struct ixgbe_adapter *adapter = dev->data->dev_private;
2381 PMD_INIT_FUNC_TRACE();
2383 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2384 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2386 /* multipe queue mode checking */
2387 ret = ixgbe_check_mq_mode(dev);
2389 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2394 /* set flag to update link status after init */
2395 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2398 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2399 * allocation or vector Rx preconditions we will reset it.
2401 adapter->rx_bulk_alloc_allowed = true;
2402 adapter->rx_vec_allowed = true;
2408 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2410 struct ixgbe_hw *hw =
2411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412 struct ixgbe_interrupt *intr =
2413 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2416 /* only set up it on X550EM_X */
2417 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2418 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2419 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2420 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2421 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2422 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2427 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2428 uint16_t tx_rate, uint64_t q_msk)
2430 struct ixgbe_hw *hw;
2431 struct ixgbe_vf_info *vfinfo;
2432 struct rte_eth_link link;
2433 uint8_t nb_q_per_pool;
2434 uint32_t queue_stride;
2435 uint32_t queue_idx, idx = 0, vf_idx;
2437 uint16_t total_rate = 0;
2438 struct rte_pci_device *pci_dev;
2441 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2442 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2446 if (vf >= pci_dev->max_vfs)
2449 if (tx_rate > link.link_speed)
2455 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2457 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2458 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2459 queue_idx = vf * queue_stride;
2460 queue_end = queue_idx + nb_q_per_pool - 1;
2461 if (queue_end >= hw->mac.max_tx_queues)
2465 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2468 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2470 total_rate += vfinfo[vf_idx].tx_rate[idx];
2476 /* Store tx_rate for this vf. */
2477 for (idx = 0; idx < nb_q_per_pool; idx++) {
2478 if (((uint64_t)0x1 << idx) & q_msk) {
2479 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2480 vfinfo[vf].tx_rate[idx] = tx_rate;
2481 total_rate += tx_rate;
2485 if (total_rate > dev->data->dev_link.link_speed) {
2486 /* Reset stored TX rate of the VF if it causes exceed
2489 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2493 /* Set RTTBCNRC of each queue/pool for vf X */
2494 for (; queue_idx <= queue_end; queue_idx++) {
2496 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2504 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2506 struct ixgbe_adapter *adapter = dev->data->dev_private;
2512 err = ixgbe_fc_enable(hw);
2514 /* Not negotiated is not an error case */
2515 if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2517 *check if we want to forward MAC frames - driver doesn't
2518 *have native capability to do that,
2519 *so we'll write the registers ourselves
2522 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2524 /* set or clear MFLCN.PMCF bit depending on configuration */
2525 if (adapter->mac_ctrl_frame_fwd != 0)
2526 mflcn |= IXGBE_MFLCN_PMCF;
2528 mflcn &= ~IXGBE_MFLCN_PMCF;
2530 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2531 IXGBE_WRITE_FLUSH(hw);
2539 * Configure device link speed and setup link.
2540 * It returns 0 on success.
2543 ixgbe_dev_start(struct rte_eth_dev *dev)
2545 struct ixgbe_hw *hw =
2546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547 struct ixgbe_vf_info *vfinfo =
2548 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2550 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2551 uint32_t intr_vector = 0;
2553 bool link_up = false, negotiate = 0;
2555 uint32_t allowed_speeds = 0;
2559 uint32_t *link_speeds;
2560 struct ixgbe_tm_conf *tm_conf =
2561 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2562 struct ixgbe_macsec_setting *macsec_setting =
2563 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2565 PMD_INIT_FUNC_TRACE();
2567 /* Stop the link setup handler before resetting the HW. */
2568 ixgbe_dev_wait_setup_link_complete(dev, 0);
2570 /* disable uio/vfio intr/eventfd mapping */
2571 rte_intr_disable(intr_handle);
2574 hw->adapter_stopped = 0;
2575 ixgbe_stop_adapter(hw);
2577 /* reinitialize adapter
2578 * this calls reset and start
2580 status = ixgbe_pf_reset_hw(hw);
2583 hw->mac.ops.start_hw(hw);
2584 hw->mac.get_link_status = true;
2586 /* configure PF module if SRIOV enabled */
2587 ixgbe_pf_host_configure(dev);
2589 ixgbe_dev_phy_intr_setup(dev);
2591 /* check and configure queue intr-vector mapping */
2592 if ((rte_intr_cap_multiple(intr_handle) ||
2593 !RTE_ETH_DEV_SRIOV(dev).active) &&
2594 dev->data->dev_conf.intr_conf.rxq != 0) {
2595 intr_vector = dev->data->nb_rx_queues;
2596 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2597 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2598 IXGBE_MAX_INTR_QUEUE_NUM);
2601 if (rte_intr_efd_enable(intr_handle, intr_vector))
2605 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2606 intr_handle->intr_vec =
2607 rte_zmalloc("intr_vec",
2608 dev->data->nb_rx_queues * sizeof(int), 0);
2609 if (intr_handle->intr_vec == NULL) {
2610 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2611 " intr_vec", dev->data->nb_rx_queues);
2616 /* confiugre msix for sleep until rx interrupt */
2617 ixgbe_configure_msix(dev);
2619 /* initialize transmission unit */
2620 ixgbe_dev_tx_init(dev);
2622 /* This can fail when allocating mbufs for descriptor rings */
2623 err = ixgbe_dev_rx_init(dev);
2625 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2629 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2630 ETH_VLAN_EXTEND_MASK;
2631 err = ixgbe_vlan_offload_config(dev, mask);
2633 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2637 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2638 /* Enable vlan filtering for VMDq */
2639 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2642 /* Configure DCB hw */
2643 ixgbe_configure_dcb(dev);
2645 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2646 err = ixgbe_fdir_configure(dev);
2651 /* Restore vf rate limit */
2652 if (vfinfo != NULL) {
2653 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2654 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2655 if (vfinfo[vf].tx_rate[idx] != 0)
2656 ixgbe_set_vf_rate_limit(
2658 vfinfo[vf].tx_rate[idx],
2662 ixgbe_restore_statistics_mapping(dev);
2664 err = ixgbe_flow_ctrl_enable(dev, hw);
2666 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2670 err = ixgbe_dev_rxtx_start(dev);
2672 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2676 /* Skip link setup if loopback mode is enabled. */
2677 if (dev->data->dev_conf.lpbk_mode != 0) {
2678 err = ixgbe_check_supported_loopback_mode(dev);
2680 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2683 goto skip_link_setup;
2687 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2688 err = hw->mac.ops.setup_sfp(hw);
2693 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2694 /* Turn on the copper */
2695 ixgbe_set_phy_power(hw, true);
2697 /* Turn on the laser */
2698 ixgbe_enable_tx_laser(hw);
2701 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2704 dev->data->dev_link.link_status = link_up;
2706 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2710 switch (hw->mac.type) {
2711 case ixgbe_mac_X550:
2712 case ixgbe_mac_X550EM_x:
2713 case ixgbe_mac_X550EM_a:
2714 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2715 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2717 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2718 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2719 allowed_speeds = ETH_LINK_SPEED_10M |
2720 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2723 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2727 link_speeds = &dev->data->dev_conf.link_speeds;
2729 /* Ignore autoneg flag bit and check the validity ofÂ
2732 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2733 PMD_INIT_LOG(ERR, "Invalid link setting");
2738 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2739 switch (hw->mac.type) {
2740 case ixgbe_mac_82598EB:
2741 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2743 case ixgbe_mac_82599EB:
2744 case ixgbe_mac_X540:
2745 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2747 case ixgbe_mac_X550:
2748 case ixgbe_mac_X550EM_x:
2749 case ixgbe_mac_X550EM_a:
2750 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2753 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2756 if (*link_speeds & ETH_LINK_SPEED_10G)
2757 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2758 if (*link_speeds & ETH_LINK_SPEED_5G)
2759 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2760 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2761 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2762 if (*link_speeds & ETH_LINK_SPEED_1G)
2763 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2764 if (*link_speeds & ETH_LINK_SPEED_100M)
2765 speed |= IXGBE_LINK_SPEED_100_FULL;
2766 if (*link_speeds & ETH_LINK_SPEED_10M)
2767 speed |= IXGBE_LINK_SPEED_10_FULL;
2770 err = ixgbe_setup_link(hw, speed, link_up);
2776 if (rte_intr_allow_others(intr_handle)) {
2777 /* check if lsc interrupt is enabled */
2778 if (dev->data->dev_conf.intr_conf.lsc != 0)
2779 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2781 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2782 ixgbe_dev_macsec_interrupt_setup(dev);
2784 rte_intr_callback_unregister(intr_handle,
2785 ixgbe_dev_interrupt_handler, dev);
2786 if (dev->data->dev_conf.intr_conf.lsc != 0)
2787 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2788 " no intr multiplex");
2791 /* check if rxq interrupt is enabled */
2792 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2793 rte_intr_dp_is_en(intr_handle))
2794 ixgbe_dev_rxq_interrupt_setup(dev);
2796 /* enable uio/vfio intr/eventfd mapping */
2797 rte_intr_enable(intr_handle);
2799 /* resume enabled intr since hw reset */
2800 ixgbe_enable_intr(dev);
2801 ixgbe_l2_tunnel_conf(dev);
2802 ixgbe_filter_restore(dev);
2804 if (tm_conf->root && !tm_conf->committed)
2805 PMD_DRV_LOG(WARNING,
2806 "please call hierarchy_commit() "
2807 "before starting the port");
2809 /* wait for the controller to acquire link */
2810 err = ixgbe_wait_for_link_up(hw);
2815 * Update link status right before return, because it may
2816 * start link configuration process in a separate thread.
2818 ixgbe_dev_link_update(dev, 0);
2820 /* setup the macsec setting register */
2821 if (macsec_setting->offload_en)
2822 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2827 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2828 ixgbe_dev_clear_queues(dev);
2833 * Stop device: disable rx and tx functions to allow for reconfiguring.
2836 ixgbe_dev_stop(struct rte_eth_dev *dev)
2838 struct rte_eth_link link;
2839 struct ixgbe_adapter *adapter = dev->data->dev_private;
2840 struct ixgbe_hw *hw =
2841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct ixgbe_vf_info *vfinfo =
2843 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2844 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2845 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2847 struct ixgbe_tm_conf *tm_conf =
2848 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2850 if (hw->adapter_stopped)
2853 PMD_INIT_FUNC_TRACE();
2855 ixgbe_dev_wait_setup_link_complete(dev, 0);
2857 /* disable interrupts */
2858 ixgbe_disable_intr(hw);
2861 ixgbe_pf_reset_hw(hw);
2862 hw->adapter_stopped = 0;
2865 ixgbe_stop_adapter(hw);
2867 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2868 vfinfo[vf].clear_to_send = false;
2870 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2871 /* Turn off the copper */
2872 ixgbe_set_phy_power(hw, false);
2874 /* Turn off the laser */
2875 ixgbe_disable_tx_laser(hw);
2878 ixgbe_dev_clear_queues(dev);
2880 /* Clear stored conf */
2881 dev->data->scattered_rx = 0;
2884 /* Clear recorded link status */
2885 memset(&link, 0, sizeof(link));
2886 rte_eth_linkstatus_set(dev, &link);
2888 if (!rte_intr_allow_others(intr_handle))
2889 /* resume to the default handler */
2890 rte_intr_callback_register(intr_handle,
2891 ixgbe_dev_interrupt_handler,
2894 /* Clean datapath event and queue/vec mapping */
2895 rte_intr_efd_disable(intr_handle);
2896 if (intr_handle->intr_vec != NULL) {
2897 rte_free(intr_handle->intr_vec);
2898 intr_handle->intr_vec = NULL;
2901 /* reset hierarchy commit */
2902 tm_conf->committed = false;
2904 adapter->rss_reta_updated = 0;
2906 hw->adapter_stopped = true;
2907 dev->data->dev_started = 0;
2913 * Set device link up: enable tx.
2916 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2918 struct ixgbe_hw *hw =
2919 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920 if (hw->mac.type == ixgbe_mac_82599EB) {
2921 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2922 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2923 /* Not suported in bypass mode */
2924 PMD_INIT_LOG(ERR, "Set link up is not supported "
2925 "by device id 0x%x", hw->device_id);
2931 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2932 /* Turn on the copper */
2933 ixgbe_set_phy_power(hw, true);
2935 /* Turn on the laser */
2936 ixgbe_enable_tx_laser(hw);
2937 ixgbe_dev_link_update(dev, 0);
2944 * Set device link down: disable tx.
2947 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2949 struct ixgbe_hw *hw =
2950 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951 if (hw->mac.type == ixgbe_mac_82599EB) {
2952 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2953 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2954 /* Not suported in bypass mode */
2955 PMD_INIT_LOG(ERR, "Set link down is not supported "
2956 "by device id 0x%x", hw->device_id);
2962 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2963 /* Turn off the copper */
2964 ixgbe_set_phy_power(hw, false);
2966 /* Turn off the laser */
2967 ixgbe_disable_tx_laser(hw);
2968 ixgbe_dev_link_update(dev, 0);
2975 * Reset and stop device.
2978 ixgbe_dev_close(struct rte_eth_dev *dev)
2980 struct ixgbe_hw *hw =
2981 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2983 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2987 PMD_INIT_FUNC_TRACE();
2988 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2991 ixgbe_pf_reset_hw(hw);
2993 ret = ixgbe_dev_stop(dev);
2995 ixgbe_dev_free_queues(dev);
2997 ixgbe_disable_pcie_master(hw);
2999 /* reprogram the RAR[0] in case user changed it. */
3000 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3002 /* Unlock any pending hardware semaphore */
3003 ixgbe_swfw_lock_reset(hw);
3005 /* disable uio intr before callback unregister */
3006 rte_intr_disable(intr_handle);
3009 ret = rte_intr_callback_unregister(intr_handle,
3010 ixgbe_dev_interrupt_handler, dev);
3011 if (ret >= 0 || ret == -ENOENT) {
3013 } else if (ret != -EAGAIN) {
3015 "intr callback unregister failed: %d",
3019 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3021 /* cancel the delay handler before remove dev */
3022 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3024 /* uninitialize PF if max_vfs not zero */
3025 ixgbe_pf_host_uninit(dev);
3027 /* remove all the fdir filters & hash */
3028 ixgbe_fdir_filter_uninit(dev);
3030 /* remove all the L2 tunnel filters & hash */
3031 ixgbe_l2_tn_filter_uninit(dev);
3033 /* Remove all ntuple filters of the device */
3034 ixgbe_ntuple_filter_uninit(dev);
3036 /* clear all the filters list */
3037 ixgbe_filterlist_flush();
3039 /* Remove all Traffic Manager configuration */
3040 ixgbe_tm_conf_uninit(dev);
3042 #ifdef RTE_LIB_SECURITY
3043 rte_free(dev->security_ctx);
3053 ixgbe_dev_reset(struct rte_eth_dev *dev)
3057 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3058 * its VF to make them align with it. The detailed notification
3059 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3060 * To avoid unexpected behavior in VF, currently reset of PF with
3061 * SR-IOV activation is not supported. It might be supported later.
3063 if (dev->data->sriov.active)
3066 ret = eth_ixgbe_dev_uninit(dev);
3070 ret = eth_ixgbe_dev_init(dev, NULL);
3076 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3077 struct ixgbe_hw_stats *hw_stats,
3078 struct ixgbe_macsec_stats *macsec_stats,
3079 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3080 uint64_t *total_qprc, uint64_t *total_qprdc)
3082 uint32_t bprc, lxon, lxoff, total;
3083 uint32_t delta_gprc = 0;
3085 /* Workaround for RX byte count not including CRC bytes when CRC
3086 * strip is enabled. CRC bytes are removed from counters when crc_strip
3089 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3090 IXGBE_HLREG0_RXCRCSTRP);
3092 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3093 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3094 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3095 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3097 for (i = 0; i < 8; i++) {
3098 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3100 /* global total per queue */
3101 hw_stats->mpc[i] += mp;
3102 /* Running comprehensive total for stats display */
3103 *total_missed_rx += hw_stats->mpc[i];
3104 if (hw->mac.type == ixgbe_mac_82598EB) {
3105 hw_stats->rnbc[i] +=
3106 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3107 hw_stats->pxonrxc[i] +=
3108 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3109 hw_stats->pxoffrxc[i] +=
3110 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3112 hw_stats->pxonrxc[i] +=
3113 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3114 hw_stats->pxoffrxc[i] +=
3115 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3116 hw_stats->pxon2offc[i] +=
3117 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3119 hw_stats->pxontxc[i] +=
3120 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3121 hw_stats->pxofftxc[i] +=
3122 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3124 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3125 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3126 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3127 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3129 delta_gprc += delta_qprc;
3131 hw_stats->qprc[i] += delta_qprc;
3132 hw_stats->qptc[i] += delta_qptc;
3134 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3135 hw_stats->qbrc[i] +=
3136 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3138 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3140 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3141 hw_stats->qbtc[i] +=
3142 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3144 hw_stats->qprdc[i] += delta_qprdc;
3145 *total_qprdc += hw_stats->qprdc[i];
3147 *total_qprc += hw_stats->qprc[i];
3148 *total_qbrc += hw_stats->qbrc[i];
3150 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3151 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3152 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3155 * An errata states that gprc actually counts good + missed packets:
3156 * Workaround to set gprc to summated queue packet receives
3158 hw_stats->gprc = *total_qprc;
3160 if (hw->mac.type != ixgbe_mac_82598EB) {
3161 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3162 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3163 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3164 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3165 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3166 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3167 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3168 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3170 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3171 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3172 /* 82598 only has a counter in the high register */
3173 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3174 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3175 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3177 uint64_t old_tpr = hw_stats->tpr;
3179 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3180 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3183 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3185 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3186 hw_stats->gptc += delta_gptc;
3187 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3188 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3191 * Workaround: mprc hardware is incorrectly counting
3192 * broadcasts, so for now we subtract those.
3194 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3195 hw_stats->bprc += bprc;
3196 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3197 if (hw->mac.type == ixgbe_mac_82598EB)
3198 hw_stats->mprc -= bprc;
3200 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3201 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3202 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3203 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3204 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3205 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3207 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3208 hw_stats->lxontxc += lxon;
3209 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3210 hw_stats->lxofftxc += lxoff;
3211 total = lxon + lxoff;
3213 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3214 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3215 hw_stats->gptc -= total;
3216 hw_stats->mptc -= total;
3217 hw_stats->ptc64 -= total;
3218 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3220 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3221 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3222 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3223 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3224 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3225 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3226 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3227 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3228 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3229 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3230 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3231 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3232 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3233 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3234 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3235 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3236 /* Only read FCOE on 82599 */
3237 if (hw->mac.type != ixgbe_mac_82598EB) {
3238 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3239 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3240 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3241 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3242 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3245 /* Flow Director Stats registers */
3246 if (hw->mac.type != ixgbe_mac_82598EB) {
3247 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3248 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3249 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3250 IXGBE_FDIRUSTAT) & 0xFFFF;
3251 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3252 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3253 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3254 IXGBE_FDIRFSTAT) & 0xFFFF;
3255 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3256 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3258 /* MACsec Stats registers */
3259 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3260 macsec_stats->out_pkts_encrypted +=
3261 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3262 macsec_stats->out_pkts_protected +=
3263 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3264 macsec_stats->out_octets_encrypted +=
3265 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3266 macsec_stats->out_octets_protected +=
3267 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3268 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3269 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3270 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3271 macsec_stats->in_pkts_unknownsci +=
3272 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3273 macsec_stats->in_octets_decrypted +=
3274 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3275 macsec_stats->in_octets_validated +=
3276 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3277 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3278 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3279 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3280 for (i = 0; i < 2; i++) {
3281 macsec_stats->in_pkts_ok +=
3282 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3283 macsec_stats->in_pkts_invalid +=
3284 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3285 macsec_stats->in_pkts_notvalid +=
3286 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3288 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3289 macsec_stats->in_pkts_notusingsa +=
3290 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3294 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3297 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3299 struct ixgbe_hw *hw =
3300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 struct ixgbe_hw_stats *hw_stats =
3302 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3303 struct ixgbe_macsec_stats *macsec_stats =
3304 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3305 dev->data->dev_private);
3306 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3309 total_missed_rx = 0;
3314 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3315 &total_qbrc, &total_qprc, &total_qprdc);
3320 /* Fill out the rte_eth_stats statistics structure */
3321 stats->ipackets = total_qprc;
3322 stats->ibytes = total_qbrc;
3323 stats->opackets = hw_stats->gptc;
3324 stats->obytes = hw_stats->gotc;
3326 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3327 stats->q_ipackets[i] = hw_stats->qprc[i];
3328 stats->q_opackets[i] = hw_stats->qptc[i];
3329 stats->q_ibytes[i] = hw_stats->qbrc[i];
3330 stats->q_obytes[i] = hw_stats->qbtc[i];
3331 stats->q_errors[i] = hw_stats->qprdc[i];
3335 stats->imissed = total_missed_rx;
3336 stats->ierrors = hw_stats->crcerrs +
3353 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3355 struct ixgbe_hw_stats *stats =
3356 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3358 /* HW registers are cleared on read */
3359 ixgbe_dev_stats_get(dev, NULL);
3361 /* Reset software totals */
3362 memset(stats, 0, sizeof(*stats));
3367 /* This function calculates the number of xstats based on the current config */
3369 ixgbe_xstats_calc_num(void) {
3370 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3371 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3372 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3375 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3376 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3378 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3379 unsigned stat, i, count;
3381 if (xstats_names != NULL) {
3384 /* Note: limit >= cnt_stats checked upstream
3385 * in rte_eth_xstats_names()
3388 /* Extended stats from ixgbe_hw_stats */
3389 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3390 strlcpy(xstats_names[count].name,
3391 rte_ixgbe_stats_strings[i].name,
3392 sizeof(xstats_names[count].name));
3397 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3398 strlcpy(xstats_names[count].name,
3399 rte_ixgbe_macsec_strings[i].name,
3400 sizeof(xstats_names[count].name));
3404 /* RX Priority Stats */
3405 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3406 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3407 snprintf(xstats_names[count].name,
3408 sizeof(xstats_names[count].name),
3409 "rx_priority%u_%s", i,
3410 rte_ixgbe_rxq_strings[stat].name);
3415 /* TX Priority Stats */
3416 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3417 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3418 snprintf(xstats_names[count].name,
3419 sizeof(xstats_names[count].name),
3420 "tx_priority%u_%s", i,
3421 rte_ixgbe_txq_strings[stat].name);
3429 static int ixgbe_dev_xstats_get_names_by_id(
3430 struct rte_eth_dev *dev,
3431 struct rte_eth_xstat_name *xstats_names,
3432 const uint64_t *ids,
3436 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3437 unsigned int stat, i, count;
3439 if (xstats_names != NULL) {
3442 /* Note: limit >= cnt_stats checked upstream
3443 * in rte_eth_xstats_names()
3446 /* Extended stats from ixgbe_hw_stats */
3447 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3448 strlcpy(xstats_names[count].name,
3449 rte_ixgbe_stats_strings[i].name,
3450 sizeof(xstats_names[count].name));
3455 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3456 strlcpy(xstats_names[count].name,
3457 rte_ixgbe_macsec_strings[i].name,
3458 sizeof(xstats_names[count].name));
3462 /* RX Priority Stats */
3463 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3464 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3465 snprintf(xstats_names[count].name,
3466 sizeof(xstats_names[count].name),
3467 "rx_priority%u_%s", i,
3468 rte_ixgbe_rxq_strings[stat].name);
3473 /* TX Priority Stats */
3474 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3475 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3476 snprintf(xstats_names[count].name,
3477 sizeof(xstats_names[count].name),
3478 "tx_priority%u_%s", i,
3479 rte_ixgbe_txq_strings[stat].name);
3488 uint16_t size = ixgbe_xstats_calc_num();
3489 struct rte_eth_xstat_name xstats_names_copy[size];
3491 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3494 for (i = 0; i < limit; i++) {
3495 if (ids[i] >= size) {
3496 PMD_INIT_LOG(ERR, "id value isn't valid");
3499 strcpy(xstats_names[i].name,
3500 xstats_names_copy[ids[i]].name);
3505 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3506 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3510 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3513 if (xstats_names != NULL)
3514 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3515 strlcpy(xstats_names[i].name,
3516 rte_ixgbevf_stats_strings[i].name,
3517 sizeof(xstats_names[i].name));
3518 return IXGBEVF_NB_XSTATS;
3522 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3525 struct ixgbe_hw *hw =
3526 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3527 struct ixgbe_hw_stats *hw_stats =
3528 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3529 struct ixgbe_macsec_stats *macsec_stats =
3530 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3531 dev->data->dev_private);
3532 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3533 unsigned i, stat, count = 0;
3535 count = ixgbe_xstats_calc_num();
3540 total_missed_rx = 0;
3545 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3546 &total_qbrc, &total_qprc, &total_qprdc);
3548 /* If this is a reset xstats is NULL, and we have cleared the
3549 * registers by reading them.
3554 /* Extended stats from ixgbe_hw_stats */
3556 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3557 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3558 rte_ixgbe_stats_strings[i].offset);
3559 xstats[count].id = count;
3564 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3565 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3566 rte_ixgbe_macsec_strings[i].offset);
3567 xstats[count].id = count;
3571 /* RX Priority Stats */
3572 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3573 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3574 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3575 rte_ixgbe_rxq_strings[stat].offset +
3576 (sizeof(uint64_t) * i));
3577 xstats[count].id = count;
3582 /* TX Priority Stats */
3583 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3584 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3585 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3586 rte_ixgbe_txq_strings[stat].offset +
3587 (sizeof(uint64_t) * i));
3588 xstats[count].id = count;
3596 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3597 uint64_t *values, unsigned int n)
3600 struct ixgbe_hw *hw =
3601 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 struct ixgbe_hw_stats *hw_stats =
3603 IXGBE_DEV_PRIVATE_TO_STATS(
3604 dev->data->dev_private);
3605 struct ixgbe_macsec_stats *macsec_stats =
3606 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3607 dev->data->dev_private);
3608 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3609 unsigned int i, stat, count = 0;
3611 count = ixgbe_xstats_calc_num();
3613 if (!ids && n < count)
3616 total_missed_rx = 0;
3621 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3622 &total_missed_rx, &total_qbrc, &total_qprc,
3625 /* If this is a reset xstats is NULL, and we have cleared the
3626 * registers by reading them.
3628 if (!ids && !values)
3631 /* Extended stats from ixgbe_hw_stats */
3633 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3634 values[count] = *(uint64_t *)(((char *)hw_stats) +
3635 rte_ixgbe_stats_strings[i].offset);
3640 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3641 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3642 rte_ixgbe_macsec_strings[i].offset);
3646 /* RX Priority Stats */
3647 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3648 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3650 *(uint64_t *)(((char *)hw_stats) +
3651 rte_ixgbe_rxq_strings[stat].offset +
3652 (sizeof(uint64_t) * i));
3657 /* TX Priority Stats */
3658 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3659 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3661 *(uint64_t *)(((char *)hw_stats) +
3662 rte_ixgbe_txq_strings[stat].offset +
3663 (sizeof(uint64_t) * i));
3671 uint16_t size = ixgbe_xstats_calc_num();
3672 uint64_t values_copy[size];
3674 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3676 for (i = 0; i < n; i++) {
3677 if (ids[i] >= size) {
3678 PMD_INIT_LOG(ERR, "id value isn't valid");
3681 values[i] = values_copy[ids[i]];
3687 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3689 struct ixgbe_hw_stats *stats =
3690 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3691 struct ixgbe_macsec_stats *macsec_stats =
3692 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3693 dev->data->dev_private);
3695 unsigned count = ixgbe_xstats_calc_num();
3697 /* HW registers are cleared on read */
3698 ixgbe_dev_xstats_get(dev, NULL, count);
3700 /* Reset software totals */
3701 memset(stats, 0, sizeof(*stats));
3702 memset(macsec_stats, 0, sizeof(*macsec_stats));
3708 ixgbevf_update_stats(struct rte_eth_dev *dev)
3710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3712 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3714 /* Good Rx packet, include VF loopback */
3715 UPDATE_VF_STAT(IXGBE_VFGPRC,
3716 hw_stats->last_vfgprc, hw_stats->vfgprc);
3718 /* Good Rx octets, include VF loopback */
3719 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3720 hw_stats->last_vfgorc, hw_stats->vfgorc);
3722 /* Good Tx packet, include VF loopback */
3723 UPDATE_VF_STAT(IXGBE_VFGPTC,
3724 hw_stats->last_vfgptc, hw_stats->vfgptc);
3726 /* Good Tx octets, include VF loopback */
3727 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3728 hw_stats->last_vfgotc, hw_stats->vfgotc);
3730 /* Rx Multicst Packet */
3731 UPDATE_VF_STAT(IXGBE_VFMPRC,
3732 hw_stats->last_vfmprc, hw_stats->vfmprc);
3736 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3739 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3740 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3743 if (n < IXGBEVF_NB_XSTATS)
3744 return IXGBEVF_NB_XSTATS;
3746 ixgbevf_update_stats(dev);
3751 /* Extended stats */
3752 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3754 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3755 rte_ixgbevf_stats_strings[i].offset);
3758 return IXGBEVF_NB_XSTATS;
3762 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3764 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3765 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3767 ixgbevf_update_stats(dev);
3772 stats->ipackets = hw_stats->vfgprc;
3773 stats->ibytes = hw_stats->vfgorc;
3774 stats->opackets = hw_stats->vfgptc;
3775 stats->obytes = hw_stats->vfgotc;
3780 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3782 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3783 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3785 /* Sync HW register to the last stats */
3786 ixgbevf_dev_stats_get(dev, NULL);
3788 /* reset HW current stats*/
3789 hw_stats->vfgprc = 0;
3790 hw_stats->vfgorc = 0;
3791 hw_stats->vfgptc = 0;
3792 hw_stats->vfgotc = 0;
3798 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801 u16 eeprom_verh, eeprom_verl;
3805 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3806 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3808 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3809 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3811 ret += 1; /* add the size of '\0' */
3812 if (fw_size < (u32)ret)
3819 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3821 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3822 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3825 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3826 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3827 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3829 * When DCB/VT is off, maximum number of queues changes,
3830 * except for 82598EB, which remains constant.
3832 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3833 hw->mac.type != ixgbe_mac_82598EB)
3834 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3836 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3837 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3838 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3839 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3840 dev_info->max_vfs = pci_dev->max_vfs;
3841 if (hw->mac.type == ixgbe_mac_82598EB)
3842 dev_info->max_vmdq_pools = ETH_16_POOLS;
3844 dev_info->max_vmdq_pools = ETH_64_POOLS;
3845 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3846 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3847 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3848 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3849 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3850 dev_info->rx_queue_offload_capa);
3851 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3852 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3854 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3856 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3857 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3858 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3860 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3865 dev_info->default_txconf = (struct rte_eth_txconf) {
3867 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3868 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3869 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3871 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3872 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3876 dev_info->rx_desc_lim = rx_desc_lim;
3877 dev_info->tx_desc_lim = tx_desc_lim;
3879 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3880 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3881 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3883 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3884 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3885 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3886 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3887 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3889 if (hw->mac.type == ixgbe_mac_X540 ||
3890 hw->mac.type == ixgbe_mac_X540_vf ||
3891 hw->mac.type == ixgbe_mac_X550 ||
3892 hw->mac.type == ixgbe_mac_X550_vf) {
3893 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3895 if (hw->mac.type == ixgbe_mac_X550) {
3896 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3897 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3900 /* Driver-preferred Rx/Tx parameters */
3901 dev_info->default_rxportconf.burst_size = 32;
3902 dev_info->default_txportconf.burst_size = 32;
3903 dev_info->default_rxportconf.nb_queues = 1;
3904 dev_info->default_txportconf.nb_queues = 1;
3905 dev_info->default_rxportconf.ring_size = 256;
3906 dev_info->default_txportconf.ring_size = 256;
3911 static const uint32_t *
3912 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3914 static const uint32_t ptypes[] = {
3915 /* For non-vec functions,
3916 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3917 * for vec functions,
3918 * refers to _recv_raw_pkts_vec().
3922 RTE_PTYPE_L3_IPV4_EXT,
3924 RTE_PTYPE_L3_IPV6_EXT,
3928 RTE_PTYPE_TUNNEL_IP,
3929 RTE_PTYPE_INNER_L3_IPV6,
3930 RTE_PTYPE_INNER_L3_IPV6_EXT,
3931 RTE_PTYPE_INNER_L4_TCP,
3932 RTE_PTYPE_INNER_L4_UDP,
3936 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3937 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3938 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3939 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3942 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3943 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3944 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3951 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3952 struct rte_eth_dev_info *dev_info)
3954 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3958 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3959 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3960 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3961 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3962 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3963 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3964 dev_info->max_vfs = pci_dev->max_vfs;
3965 if (hw->mac.type == ixgbe_mac_82598EB)
3966 dev_info->max_vmdq_pools = ETH_16_POOLS;
3968 dev_info->max_vmdq_pools = ETH_64_POOLS;
3969 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3970 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3971 dev_info->rx_queue_offload_capa);
3972 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3973 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3974 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3975 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3976 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3978 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3980 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3981 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3982 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3984 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3989 dev_info->default_txconf = (struct rte_eth_txconf) {
3991 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3992 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3993 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3995 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3996 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4000 dev_info->rx_desc_lim = rx_desc_lim;
4001 dev_info->tx_desc_lim = tx_desc_lim;
4007 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4008 bool *link_up, int wait_to_complete)
4010 struct ixgbe_adapter *adapter = container_of(hw,
4011 struct ixgbe_adapter, hw);
4012 struct ixgbe_mbx_info *mbx = &hw->mbx;
4013 struct ixgbe_mac_info *mac = &hw->mac;
4014 uint32_t links_reg, in_msg;
4017 /* If we were hit with a reset drop the link */
4018 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4019 mac->get_link_status = true;
4021 if (!mac->get_link_status)
4024 /* if link status is down no point in checking to see if pf is up */
4025 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4026 if (!(links_reg & IXGBE_LINKS_UP))
4029 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4030 * before the link status is correct
4032 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4035 for (i = 0; i < 5; i++) {
4037 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4039 if (!(links_reg & IXGBE_LINKS_UP))
4044 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4045 case IXGBE_LINKS_SPEED_10G_82599:
4046 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4047 if (hw->mac.type >= ixgbe_mac_X550) {
4048 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4049 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4052 case IXGBE_LINKS_SPEED_1G_82599:
4053 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4055 case IXGBE_LINKS_SPEED_100_82599:
4056 *speed = IXGBE_LINK_SPEED_100_FULL;
4057 if (hw->mac.type == ixgbe_mac_X550) {
4058 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4059 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4062 case IXGBE_LINKS_SPEED_10_X550EM_A:
4063 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4064 /* Since Reserved in older MAC's */
4065 if (hw->mac.type >= ixgbe_mac_X550)
4066 *speed = IXGBE_LINK_SPEED_10_FULL;
4069 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4072 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4073 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4074 mac->get_link_status = true;
4076 mac->get_link_status = false;
4081 /* if the read failed it could just be a mailbox collision, best wait
4082 * until we are called again and don't report an error
4084 if (mbx->ops.read(hw, &in_msg, 1, 0))
4087 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4088 /* msg is not CTS and is NACK we must have lost CTS status */
4089 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4090 mac->get_link_status = false;
4094 /* the pf is talking, if we timed out in the past we reinit */
4095 if (!mbx->timeout) {
4100 /* if we passed all the tests above then the link is up and we no
4101 * longer need to check for link
4103 mac->get_link_status = false;
4106 *link_up = !mac->get_link_status;
4111 * If @timeout_ms was 0, it means that it will not return until link complete.
4112 * It returns 1 on complete, return 0 on timeout.
4115 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4117 #define WARNING_TIMEOUT 9000 /* 9s in total */
4118 struct ixgbe_adapter *ad = dev->data->dev_private;
4119 uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4121 while (rte_atomic32_read(&ad->link_thread_running)) {
4128 } else if (!timeout) {
4129 /* It will not return until link complete */
4130 timeout = WARNING_TIMEOUT;
4131 PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4139 ixgbe_dev_setup_link_thread_handler(void *param)
4141 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4142 struct ixgbe_adapter *ad = dev->data->dev_private;
4143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144 struct ixgbe_interrupt *intr =
4145 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4147 bool autoneg = false;
4149 pthread_detach(pthread_self());
4150 speed = hw->phy.autoneg_advertised;
4152 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4154 ixgbe_setup_link(hw, speed, true);
4156 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4157 rte_atomic32_clear(&ad->link_thread_running);
4162 * In freebsd environment, nic_uio drivers do not support interrupts,
4163 * rte_intr_callback_register() will fail to register interrupts.
4164 * We can not make link status to change from down to up by interrupt
4165 * callback. So we need to wait for the controller to acquire link
4167 * It returns 0 on link up.
4170 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4172 #ifdef RTE_EXEC_ENV_FREEBSD
4174 bool link_up = false;
4176 const int nb_iter = 25;
4178 for (i = 0; i < nb_iter; i++) {
4179 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4194 /* return 0 means link status changed, -1 means not changed */
4196 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4197 int wait_to_complete, int vf)
4199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200 struct ixgbe_adapter *ad = dev->data->dev_private;
4201 struct rte_eth_link link;
4202 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4203 struct ixgbe_interrupt *intr =
4204 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4210 memset(&link, 0, sizeof(link));
4211 link.link_status = ETH_LINK_DOWN;
4212 link.link_speed = ETH_SPEED_NUM_NONE;
4213 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4214 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4215 ETH_LINK_SPEED_FIXED);
4217 hw->mac.get_link_status = true;
4219 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4220 return rte_eth_linkstatus_set(dev, &link);
4222 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4223 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4226 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4227 #ifdef RTE_EXEC_ENV_FREEBSD
4232 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4234 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4237 link.link_speed = ETH_SPEED_NUM_100M;
4238 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4239 return rte_eth_linkstatus_set(dev, &link);
4242 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4243 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4244 if ((esdp_reg & IXGBE_ESDP_SDP3))
4249 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4250 ixgbe_dev_wait_setup_link_complete(dev, 0);
4251 if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4252 /* To avoid race condition between threads, set
4253 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4254 * when there is no link thread running.
4256 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4257 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4258 "ixgbe-link-handler",
4260 ixgbe_dev_setup_link_thread_handler,
4263 "Create link thread failed!");
4264 rte_atomic32_clear(&ad->link_thread_running);
4268 "Other link thread is running now!");
4271 return rte_eth_linkstatus_set(dev, &link);
4274 link.link_status = ETH_LINK_UP;
4275 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4277 switch (link_speed) {
4279 case IXGBE_LINK_SPEED_UNKNOWN:
4280 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4283 case IXGBE_LINK_SPEED_10_FULL:
4284 link.link_speed = ETH_SPEED_NUM_10M;
4287 case IXGBE_LINK_SPEED_100_FULL:
4288 link.link_speed = ETH_SPEED_NUM_100M;
4291 case IXGBE_LINK_SPEED_1GB_FULL:
4292 link.link_speed = ETH_SPEED_NUM_1G;
4295 case IXGBE_LINK_SPEED_2_5GB_FULL:
4296 link.link_speed = ETH_SPEED_NUM_2_5G;
4299 case IXGBE_LINK_SPEED_5GB_FULL:
4300 link.link_speed = ETH_SPEED_NUM_5G;
4303 case IXGBE_LINK_SPEED_10GB_FULL:
4304 link.link_speed = ETH_SPEED_NUM_10G;
4308 return rte_eth_linkstatus_set(dev, &link);
4312 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4314 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4318 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4320 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4324 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4330 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4331 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4337 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4343 fctrl &= (~IXGBE_FCTRL_UPE);
4344 if (dev->data->all_multicast == 1)
4345 fctrl |= IXGBE_FCTRL_MPE;
4347 fctrl &= (~IXGBE_FCTRL_MPE);
4348 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4354 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4360 fctrl |= IXGBE_FCTRL_MPE;
4361 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4367 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372 if (dev->data->promiscuous == 1)
4373 return 0; /* must remain in all_multicast mode */
4375 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4376 fctrl &= (~IXGBE_FCTRL_MPE);
4377 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4383 * It clears the interrupt causes and enables the interrupt.
4384 * It will be called once only during nic initialized.
4387 * Pointer to struct rte_eth_dev.
4389 * Enable or Disable.
4392 * - On success, zero.
4393 * - On failure, a negative value.
4396 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4398 struct ixgbe_interrupt *intr =
4399 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4401 ixgbe_dev_link_status_print(dev);
4403 intr->mask |= IXGBE_EICR_LSC;
4405 intr->mask &= ~IXGBE_EICR_LSC;
4411 * It clears the interrupt causes and enables the interrupt.
4412 * It will be called once only during nic initialized.
4415 * Pointer to struct rte_eth_dev.
4418 * - On success, zero.
4419 * - On failure, a negative value.
4422 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4424 struct ixgbe_interrupt *intr =
4425 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4427 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4433 * It clears the interrupt causes and enables the interrupt.
4434 * It will be called once only during nic initialized.
4437 * Pointer to struct rte_eth_dev.
4440 * - On success, zero.
4441 * - On failure, a negative value.
4444 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4446 struct ixgbe_interrupt *intr =
4447 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4449 intr->mask |= IXGBE_EICR_LINKSEC;
4455 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4458 * Pointer to struct rte_eth_dev.
4461 * - On success, zero.
4462 * - On failure, a negative value.
4465 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469 struct ixgbe_interrupt *intr =
4470 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4472 /* clear all cause mask */
4473 ixgbe_disable_intr(hw);
4475 /* read-on-clear nic registers here */
4476 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4477 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4481 /* set flag for async link update */
4482 if (eicr & IXGBE_EICR_LSC)
4483 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4485 if (eicr & IXGBE_EICR_MAILBOX)
4486 intr->flags |= IXGBE_FLAG_MAILBOX;
4488 if (eicr & IXGBE_EICR_LINKSEC)
4489 intr->flags |= IXGBE_FLAG_MACSEC;
4491 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4492 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4493 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4494 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4500 * It gets and then prints the link status.
4503 * Pointer to struct rte_eth_dev.
4506 * - On success, zero.
4507 * - On failure, a negative value.
4510 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4512 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4513 struct rte_eth_link link;
4515 rte_eth_linkstatus_get(dev, &link);
4517 if (link.link_status) {
4518 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4519 (int)(dev->data->port_id),
4520 (unsigned)link.link_speed,
4521 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4522 "full-duplex" : "half-duplex");
4524 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4525 (int)(dev->data->port_id));
4527 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4528 pci_dev->addr.domain,
4530 pci_dev->addr.devid,
4531 pci_dev->addr.function);
4535 * It executes link_update after knowing an interrupt occurred.
4538 * Pointer to struct rte_eth_dev.
4541 * - On success, zero.
4542 * - On failure, a negative value.
4545 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4547 struct ixgbe_interrupt *intr =
4548 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4550 struct ixgbe_hw *hw =
4551 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4555 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4556 ixgbe_pf_mbx_process(dev);
4557 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4560 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4561 ixgbe_handle_lasi(hw);
4562 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4565 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4566 struct rte_eth_link link;
4568 /* get the link status before link update, for predicting later */
4569 rte_eth_linkstatus_get(dev, &link);
4571 ixgbe_dev_link_update(dev, 0);
4574 if (!link.link_status)
4575 /* handle it 1 sec later, wait it being stable */
4576 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4577 /* likely to down */
4579 /* handle it 4 sec later, wait it being stable */
4580 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4582 ixgbe_dev_link_status_print(dev);
4583 if (rte_eal_alarm_set(timeout * 1000,
4584 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4585 PMD_DRV_LOG(ERR, "Error setting alarm");
4587 /* remember original mask */
4588 intr->mask_original = intr->mask;
4589 /* only disable lsc interrupt */
4590 intr->mask &= ~IXGBE_EIMS_LSC;
4594 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4595 ixgbe_enable_intr(dev);
4601 * Interrupt handler which shall be registered for alarm callback for delayed
4602 * handling specific interrupt to wait for the stable nic state. As the
4603 * NIC interrupt state is not stable for ixgbe after link is just down,
4604 * it needs to wait 4 seconds to get the stable status.
4607 * Pointer to interrupt handle.
4609 * The address of parameter (struct rte_eth_dev *) regsitered before.
4615 ixgbe_dev_interrupt_delayed_handler(void *param)
4617 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4618 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4619 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4620 struct ixgbe_interrupt *intr =
4621 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4622 struct ixgbe_hw *hw =
4623 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626 ixgbe_disable_intr(hw);
4628 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4629 if (eicr & IXGBE_EICR_MAILBOX)
4630 ixgbe_pf_mbx_process(dev);
4632 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4633 ixgbe_handle_lasi(hw);
4634 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4637 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4638 ixgbe_dev_link_update(dev, 0);
4639 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4640 ixgbe_dev_link_status_print(dev);
4641 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4644 if (intr->flags & IXGBE_FLAG_MACSEC) {
4645 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4646 intr->flags &= ~IXGBE_FLAG_MACSEC;
4649 /* restore original mask */
4650 intr->mask = intr->mask_original;
4651 intr->mask_original = 0;
4653 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4654 ixgbe_enable_intr(dev);
4655 rte_intr_ack(intr_handle);
4659 * Interrupt handler triggered by NIC for handling
4660 * specific interrupt.
4663 * Pointer to interrupt handle.
4665 * The address of parameter (struct rte_eth_dev *) regsitered before.
4671 ixgbe_dev_interrupt_handler(void *param)
4673 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4675 ixgbe_dev_interrupt_get_status(dev);
4676 ixgbe_dev_interrupt_action(dev);
4680 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4682 struct ixgbe_hw *hw;
4684 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4689 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4691 struct ixgbe_hw *hw;
4693 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4698 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4700 struct ixgbe_hw *hw;
4706 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708 fc_conf->pause_time = hw->fc.pause_time;
4709 fc_conf->high_water = hw->fc.high_water[0];
4710 fc_conf->low_water = hw->fc.low_water[0];
4711 fc_conf->send_xon = hw->fc.send_xon;
4712 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4715 * Return rx_pause status according to actual setting of
4718 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4719 if (mflcn_reg & IXGBE_MFLCN_PMCF)
4720 fc_conf->mac_ctrl_frame_fwd = 1;
4722 fc_conf->mac_ctrl_frame_fwd = 0;
4724 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4730 * Return tx_pause status according to actual setting of
4733 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4734 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4739 if (rx_pause && tx_pause)
4740 fc_conf->mode = RTE_FC_FULL;
4742 fc_conf->mode = RTE_FC_RX_PAUSE;
4744 fc_conf->mode = RTE_FC_TX_PAUSE;
4746 fc_conf->mode = RTE_FC_NONE;
4752 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4754 struct ixgbe_hw *hw;
4755 struct ixgbe_adapter *adapter = dev->data->dev_private;
4757 uint32_t rx_buf_size;
4758 uint32_t max_high_water;
4759 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4766 PMD_INIT_FUNC_TRACE();
4768 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4770 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4773 * At least reserve one Ethernet frame for watermark
4774 * high_water/low_water in kilo bytes for ixgbe
4776 max_high_water = (rx_buf_size -
4777 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4778 if ((fc_conf->high_water > max_high_water) ||
4779 (fc_conf->high_water < fc_conf->low_water)) {
4780 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4781 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4785 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4786 hw->fc.pause_time = fc_conf->pause_time;
4787 hw->fc.high_water[0] = fc_conf->high_water;
4788 hw->fc.low_water[0] = fc_conf->low_water;
4789 hw->fc.send_xon = fc_conf->send_xon;
4790 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4791 adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4793 err = ixgbe_flow_ctrl_enable(dev, hw);
4795 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4802 * ixgbe_pfc_enable_generic - Enable flow control
4803 * @hw: pointer to hardware structure
4804 * @tc_num: traffic class number
4805 * Enable flow control according to the current settings.
4808 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4811 uint32_t mflcn_reg, fccfg_reg;
4813 uint32_t fcrtl, fcrth;
4817 /* Validate the water mark configuration */
4818 if (!hw->fc.pause_time) {
4819 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4823 /* Low water mark of zero causes XOFF floods */
4824 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4825 /* High/Low water can not be 0 */
4826 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4827 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4828 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4832 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4833 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4834 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4838 /* Negotiate the fc mode to use */
4839 ixgbe_fc_autoneg(hw);
4841 /* Disable any previous flow control settings */
4842 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4843 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4845 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4846 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4848 switch (hw->fc.current_mode) {
4851 * If the count of enabled RX Priority Flow control >1,
4852 * and the TX pause can not be disabled
4855 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4856 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4857 if (reg & IXGBE_FCRTH_FCEN)
4861 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4863 case ixgbe_fc_rx_pause:
4865 * Rx Flow control is enabled and Tx Flow control is
4866 * disabled by software override. Since there really
4867 * isn't a way to advertise that we are capable of RX
4868 * Pause ONLY, we will advertise that we support both
4869 * symmetric and asymmetric Rx PAUSE. Later, we will
4870 * disable the adapter's ability to send PAUSE frames.
4872 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4874 * If the count of enabled RX Priority Flow control >1,
4875 * and the TX pause can not be disabled
4878 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4879 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4880 if (reg & IXGBE_FCRTH_FCEN)
4884 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4886 case ixgbe_fc_tx_pause:
4888 * Tx Flow control is enabled, and Rx Flow control is
4889 * disabled by software override.
4891 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4894 /* Flow control (both Rx and Tx) is enabled by SW override. */
4895 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4896 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4899 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4900 ret_val = IXGBE_ERR_CONFIG;
4904 /* Set 802.3x based flow control settings. */
4905 mflcn_reg |= IXGBE_MFLCN_DPF;
4906 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4907 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4909 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4910 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4911 hw->fc.high_water[tc_num]) {
4912 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4913 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4914 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4916 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4918 * In order to prevent Tx hangs when the internal Tx
4919 * switch is enabled we must set the high water mark
4920 * to the maximum FCRTH value. This allows the Tx
4921 * switch to function even under heavy Rx workloads.
4923 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4925 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4927 /* Configure pause time (2 TCs per register) */
4928 reg = hw->fc.pause_time * 0x00010001;
4929 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4930 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4932 /* Configure flow control refresh threshold value */
4933 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4940 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4945 if (hw->mac.type != ixgbe_mac_82598EB) {
4946 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4952 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4955 uint32_t rx_buf_size;
4956 uint32_t max_high_water;
4958 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4959 struct ixgbe_hw *hw =
4960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961 struct ixgbe_dcb_config *dcb_config =
4962 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4964 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4971 PMD_INIT_FUNC_TRACE();
4973 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4974 tc_num = map[pfc_conf->priority];
4975 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4976 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4978 * At least reserve one Ethernet frame for watermark
4979 * high_water/low_water in kilo bytes for ixgbe
4981 max_high_water = (rx_buf_size -
4982 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4983 if ((pfc_conf->fc.high_water > max_high_water) ||
4984 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4985 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4986 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4990 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4991 hw->fc.pause_time = pfc_conf->fc.pause_time;
4992 hw->fc.send_xon = pfc_conf->fc.send_xon;
4993 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4994 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4996 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4998 /* Not negotiated is not an error case */
4999 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5002 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5007 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5008 struct rte_eth_rss_reta_entry64 *reta_conf,
5011 uint16_t i, sp_reta_size;
5014 uint16_t idx, shift;
5015 struct ixgbe_adapter *adapter = dev->data->dev_private;
5016 struct rte_eth_dev_data *dev_data = dev->data;
5017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 PMD_INIT_FUNC_TRACE();
5022 if (!dev_data->dev_started) {
5024 "port %d must be started before rss reta update",
5029 if (!ixgbe_rss_update_sp(hw->mac.type)) {
5030 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5035 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5036 if (reta_size != sp_reta_size) {
5037 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5038 "(%d) doesn't match the number hardware can supported "
5039 "(%d)", reta_size, sp_reta_size);
5043 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5044 idx = i / RTE_RETA_GROUP_SIZE;
5045 shift = i % RTE_RETA_GROUP_SIZE;
5046 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5050 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5051 if (mask == IXGBE_4_BIT_MASK)
5054 r = IXGBE_READ_REG(hw, reta_reg);
5055 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5056 if (mask & (0x1 << j))
5057 reta |= reta_conf[idx].reta[shift + j] <<
5060 reta |= r & (IXGBE_8_BIT_MASK <<
5063 IXGBE_WRITE_REG(hw, reta_reg, reta);
5065 adapter->rss_reta_updated = 1;
5071 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5072 struct rte_eth_rss_reta_entry64 *reta_conf,
5075 uint16_t i, sp_reta_size;
5078 uint16_t idx, shift;
5079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082 PMD_INIT_FUNC_TRACE();
5083 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5084 if (reta_size != sp_reta_size) {
5085 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5086 "(%d) doesn't match the number hardware can supported "
5087 "(%d)", reta_size, sp_reta_size);
5091 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5092 idx = i / RTE_RETA_GROUP_SIZE;
5093 shift = i % RTE_RETA_GROUP_SIZE;
5094 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5099 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5100 reta = IXGBE_READ_REG(hw, reta_reg);
5101 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5102 if (mask & (0x1 << j))
5103 reta_conf[idx].reta[shift + j] =
5104 ((reta >> (CHAR_BIT * j)) &
5113 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5114 uint32_t index, uint32_t pool)
5116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117 uint32_t enable_addr = 1;
5119 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5124 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5128 ixgbe_clear_rar(hw, index);
5132 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5134 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5136 ixgbe_remove_rar(dev, 0);
5137 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5143 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5145 if (strcmp(dev->device->driver->name, drv->driver.name))
5152 is_ixgbe_supported(struct rte_eth_dev *dev)
5154 return is_device_supported(dev, &rte_ixgbe_pmd);
5158 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5162 struct ixgbe_hw *hw;
5163 struct rte_eth_dev_info dev_info;
5164 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5165 struct rte_eth_dev_data *dev_data = dev->data;
5168 ret = ixgbe_dev_info_get(dev, &dev_info);
5172 /* check that mtu is within the allowed range */
5173 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5176 /* If device is started, refuse mtu that requires the support of
5177 * scattered packets when this feature has not been enabled before.
5179 if (dev_data->dev_started && !dev_data->scattered_rx &&
5180 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5181 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5182 PMD_INIT_LOG(ERR, "Stop port first.");
5186 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5187 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5189 /* switch to jumbo mode if needed */
5190 if (frame_size > IXGBE_ETH_MAX_LEN) {
5191 dev->data->dev_conf.rxmode.offloads |=
5192 DEV_RX_OFFLOAD_JUMBO_FRAME;
5193 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5195 dev->data->dev_conf.rxmode.offloads &=
5196 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5197 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5199 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5201 /* update max frame size */
5202 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5204 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5205 maxfrs &= 0x0000FFFF;
5206 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5207 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5213 * Virtual Function operations
5216 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5218 struct ixgbe_interrupt *intr =
5219 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5220 struct ixgbe_hw *hw =
5221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223 PMD_INIT_FUNC_TRACE();
5225 /* Clear interrupt mask to stop from interrupts being generated */
5226 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5228 IXGBE_WRITE_FLUSH(hw);
5230 /* Clear mask value. */
5235 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5237 struct ixgbe_interrupt *intr =
5238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5239 struct ixgbe_hw *hw =
5240 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242 PMD_INIT_FUNC_TRACE();
5244 /* VF enable interrupt autoclean */
5245 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5246 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5247 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5249 IXGBE_WRITE_FLUSH(hw);
5251 /* Save IXGBE_VTEIMS value to mask. */
5252 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5256 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5258 struct rte_eth_conf *conf = &dev->data->dev_conf;
5259 struct ixgbe_adapter *adapter = dev->data->dev_private;
5261 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5262 dev->data->port_id);
5264 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5265 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5268 * VF has no ability to enable/disable HW CRC
5269 * Keep the persistent behavior the same as Host PF
5271 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5272 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5273 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5274 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5277 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5278 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5279 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5284 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5285 * allocation or vector Rx preconditions we will reset it.
5287 adapter->rx_bulk_alloc_allowed = true;
5288 adapter->rx_vec_allowed = true;
5294 ixgbevf_dev_start(struct rte_eth_dev *dev)
5296 struct ixgbe_hw *hw =
5297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298 uint32_t intr_vector = 0;
5299 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5300 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5304 PMD_INIT_FUNC_TRACE();
5306 /* Stop the link setup handler before resetting the HW. */
5307 ixgbe_dev_wait_setup_link_complete(dev, 0);
5309 err = hw->mac.ops.reset_hw(hw);
5312 * In this case, reuses the MAC address assigned by VF
5315 if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5316 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5320 hw->mac.get_link_status = true;
5322 /* negotiate mailbox API version to use with the PF. */
5323 ixgbevf_negotiate_api(hw);
5325 ixgbevf_dev_tx_init(dev);
5327 /* This can fail when allocating mbufs for descriptor rings */
5328 err = ixgbevf_dev_rx_init(dev);
5330 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5331 ixgbe_dev_clear_queues(dev);
5336 ixgbevf_set_vfta_all(dev, 1);
5339 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5340 ETH_VLAN_EXTEND_MASK;
5341 err = ixgbevf_vlan_offload_config(dev, mask);
5343 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5344 ixgbe_dev_clear_queues(dev);
5348 ixgbevf_dev_rxtx_start(dev);
5350 /* check and configure queue intr-vector mapping */
5351 if (rte_intr_cap_multiple(intr_handle) &&
5352 dev->data->dev_conf.intr_conf.rxq) {
5353 /* According to datasheet, only vector 0/1/2 can be used,
5354 * now only one vector is used for Rx queue
5357 if (rte_intr_efd_enable(intr_handle, intr_vector))
5361 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5362 intr_handle->intr_vec =
5363 rte_zmalloc("intr_vec",
5364 dev->data->nb_rx_queues * sizeof(int), 0);
5365 if (intr_handle->intr_vec == NULL) {
5366 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5367 " intr_vec", dev->data->nb_rx_queues);
5371 ixgbevf_configure_msix(dev);
5373 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5374 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5375 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5376 * is not cleared, it will fail when following rte_intr_enable( ) tries
5377 * to map Rx queue interrupt to other VFIO vectors.
5378 * So clear uio/vfio intr/evevnfd first to avoid failure.
5380 rte_intr_disable(intr_handle);
5382 rte_intr_enable(intr_handle);
5384 /* Re-enable interrupt for VF */
5385 ixgbevf_intr_enable(dev);
5388 * Update link status right before return, because it may
5389 * start link configuration process in a separate thread.
5391 ixgbevf_dev_link_update(dev, 0);
5393 hw->adapter_stopped = false;
5399 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5401 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5402 struct ixgbe_adapter *adapter = dev->data->dev_private;
5403 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5404 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5406 if (hw->adapter_stopped)
5409 PMD_INIT_FUNC_TRACE();
5411 ixgbe_dev_wait_setup_link_complete(dev, 0);
5413 ixgbevf_intr_disable(dev);
5415 dev->data->dev_started = 0;
5416 hw->adapter_stopped = 1;
5417 ixgbe_stop_adapter(hw);
5420 * Clear what we set, but we still keep shadow_vfta to
5421 * restore after device starts
5423 ixgbevf_set_vfta_all(dev, 0);
5425 /* Clear stored conf */
5426 dev->data->scattered_rx = 0;
5428 ixgbe_dev_clear_queues(dev);
5430 /* Clean datapath event and queue/vec mapping */
5431 rte_intr_efd_disable(intr_handle);
5432 if (intr_handle->intr_vec != NULL) {
5433 rte_free(intr_handle->intr_vec);
5434 intr_handle->intr_vec = NULL;
5437 adapter->rss_reta_updated = 0;
5443 ixgbevf_dev_close(struct rte_eth_dev *dev)
5445 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5447 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5450 PMD_INIT_FUNC_TRACE();
5451 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5456 ret = ixgbevf_dev_stop(dev);
5458 ixgbe_dev_free_queues(dev);
5461 * Remove the VF MAC address ro ensure
5462 * that the VF traffic goes to the PF
5463 * after stop, close and detach of the VF
5465 ixgbevf_remove_mac_addr(dev, 0);
5467 rte_intr_disable(intr_handle);
5468 rte_intr_callback_unregister(intr_handle,
5469 ixgbevf_dev_interrupt_handler, dev);
5478 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5482 ret = eth_ixgbevf_dev_uninit(dev);
5486 ret = eth_ixgbevf_dev_init(dev);
5491 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5493 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494 struct ixgbe_vfta *shadow_vfta =
5495 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5496 int i = 0, j = 0, vfta = 0, mask = 1;
5498 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5499 vfta = shadow_vfta->vfta[i];
5502 for (j = 0; j < 32; j++) {
5504 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5514 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5516 struct ixgbe_hw *hw =
5517 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5518 struct ixgbe_vfta *shadow_vfta =
5519 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5520 uint32_t vid_idx = 0;
5521 uint32_t vid_bit = 0;
5524 PMD_INIT_FUNC_TRACE();
5526 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5527 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5529 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5532 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5533 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5535 /* Save what we set and retore it after device reset */
5537 shadow_vfta->vfta[vid_idx] |= vid_bit;
5539 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5545 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5547 struct ixgbe_hw *hw =
5548 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5551 PMD_INIT_FUNC_TRACE();
5553 if (queue >= hw->mac.max_rx_queues)
5556 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5558 ctrl |= IXGBE_RXDCTL_VME;
5560 ctrl &= ~IXGBE_RXDCTL_VME;
5561 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5563 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5567 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5569 struct ixgbe_rx_queue *rxq;
5573 /* VF function only support hw strip feature, others are not support */
5574 if (mask & ETH_VLAN_STRIP_MASK) {
5575 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5576 rxq = dev->data->rx_queues[i];
5577 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5578 ixgbevf_vlan_strip_queue_set(dev, i, on);
5586 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5588 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5590 ixgbevf_vlan_offload_config(dev, mask);
5596 ixgbe_vt_check(struct ixgbe_hw *hw)
5600 /* if Virtualization Technology is enabled */
5601 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5602 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5603 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5611 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5613 uint32_t vector = 0;
5615 switch (hw->mac.mc_filter_type) {
5616 case 0: /* use bits [47:36] of the address */
5617 vector = ((uc_addr->addr_bytes[4] >> 4) |
5618 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5620 case 1: /* use bits [46:35] of the address */
5621 vector = ((uc_addr->addr_bytes[4] >> 3) |
5622 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5624 case 2: /* use bits [45:34] of the address */
5625 vector = ((uc_addr->addr_bytes[4] >> 2) |
5626 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5628 case 3: /* use bits [43:32] of the address */
5629 vector = ((uc_addr->addr_bytes[4]) |
5630 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5632 default: /* Invalid mc_filter_type */
5636 /* vector can only be 12-bits or boundary will be exceeded */
5642 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5643 struct rte_ether_addr *mac_addr, uint8_t on)
5650 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5651 const uint32_t ixgbe_uta_bit_shift = 5;
5652 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5653 const uint32_t bit1 = 0x1;
5655 struct ixgbe_hw *hw =
5656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657 struct ixgbe_uta_info *uta_info =
5658 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5660 /* The UTA table only exists on 82599 hardware and newer */
5661 if (hw->mac.type < ixgbe_mac_82599EB)
5664 vector = ixgbe_uta_vector(hw, mac_addr);
5665 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5666 uta_shift = vector & ixgbe_uta_bit_mask;
5668 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5672 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5674 uta_info->uta_in_use++;
5675 reg_val |= (bit1 << uta_shift);
5676 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5678 uta_info->uta_in_use--;
5679 reg_val &= ~(bit1 << uta_shift);
5680 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5683 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5685 if (uta_info->uta_in_use > 0)
5686 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5687 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5689 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5695 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5698 struct ixgbe_hw *hw =
5699 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5700 struct ixgbe_uta_info *uta_info =
5701 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5703 /* The UTA table only exists on 82599 hardware and newer */
5704 if (hw->mac.type < ixgbe_mac_82599EB)
5708 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5709 uta_info->uta_shadow[i] = ~0;
5710 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5713 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5714 uta_info->uta_shadow[i] = 0;
5715 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5723 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5725 uint32_t new_val = orig_val;
5727 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5728 new_val |= IXGBE_VMOLR_AUPE;
5729 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5730 new_val |= IXGBE_VMOLR_ROMPE;
5731 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5732 new_val |= IXGBE_VMOLR_ROPE;
5733 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5734 new_val |= IXGBE_VMOLR_BAM;
5735 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5736 new_val |= IXGBE_VMOLR_MPE;
5741 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5742 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5743 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5744 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5745 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5746 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5747 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5750 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5751 struct rte_eth_mirror_conf *mirror_conf,
5752 uint8_t rule_id, uint8_t on)
5754 uint32_t mr_ctl, vlvf;
5755 uint32_t mp_lsb = 0;
5756 uint32_t mv_msb = 0;
5757 uint32_t mv_lsb = 0;
5758 uint32_t mp_msb = 0;
5761 uint64_t vlan_mask = 0;
5763 const uint8_t pool_mask_offset = 32;
5764 const uint8_t vlan_mask_offset = 32;
5765 const uint8_t dst_pool_offset = 8;
5766 const uint8_t rule_mr_offset = 4;
5767 const uint8_t mirror_rule_mask = 0x0F;
5769 struct ixgbe_mirror_info *mr_info =
5770 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5771 struct ixgbe_hw *hw =
5772 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773 uint8_t mirror_type = 0;
5775 if (ixgbe_vt_check(hw) < 0)
5778 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5781 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5782 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5783 mirror_conf->rule_type);
5787 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5788 mirror_type |= IXGBE_MRCTL_VLME;
5789 /* Check if vlan id is valid and find conresponding VLAN ID
5792 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5793 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5794 /* search vlan id related pool vlan filter
5797 reg_index = ixgbe_find_vlvf_slot(
5799 mirror_conf->vlan.vlan_id[i],
5803 vlvf = IXGBE_READ_REG(hw,
5804 IXGBE_VLVF(reg_index));
5805 if ((vlvf & IXGBE_VLVF_VIEN) &&
5806 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5807 mirror_conf->vlan.vlan_id[i]))
5808 vlan_mask |= (1ULL << reg_index);
5815 mv_lsb = vlan_mask & 0xFFFFFFFF;
5816 mv_msb = vlan_mask >> vlan_mask_offset;
5818 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5819 mirror_conf->vlan.vlan_mask;
5820 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5821 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5822 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5823 mirror_conf->vlan.vlan_id[i];
5828 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5829 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5830 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5835 * if enable pool mirror, write related pool mask register,if disable
5836 * pool mirror, clear PFMRVM register
5838 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5839 mirror_type |= IXGBE_MRCTL_VPME;
5841 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5842 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5843 mr_info->mr_conf[rule_id].pool_mask =
5844 mirror_conf->pool_mask;
5849 mr_info->mr_conf[rule_id].pool_mask = 0;
5852 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5853 mirror_type |= IXGBE_MRCTL_UPME;
5854 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5855 mirror_type |= IXGBE_MRCTL_DPME;
5857 /* read mirror control register and recalculate it */
5858 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5861 mr_ctl |= mirror_type;
5862 mr_ctl &= mirror_rule_mask;
5863 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5865 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5868 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5869 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5871 /* write mirrror control register */
5872 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5874 /* write pool mirrror control register */
5875 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5876 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5877 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5880 /* write VLAN mirrror control register */
5881 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5882 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5883 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5891 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5894 uint32_t lsb_val = 0;
5895 uint32_t msb_val = 0;
5896 const uint8_t rule_mr_offset = 4;
5898 struct ixgbe_hw *hw =
5899 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900 struct ixgbe_mirror_info *mr_info =
5901 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5903 if (ixgbe_vt_check(hw) < 0)
5906 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5909 memset(&mr_info->mr_conf[rule_id], 0,
5910 sizeof(struct rte_eth_mirror_conf));
5912 /* clear PFVMCTL register */
5913 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5915 /* clear pool mask register */
5916 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5917 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5919 /* clear vlan mask register */
5920 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5921 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5927 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5929 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5930 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5931 struct ixgbe_interrupt *intr =
5932 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5933 struct ixgbe_hw *hw =
5934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935 uint32_t vec = IXGBE_MISC_VEC_ID;
5937 if (rte_intr_allow_others(intr_handle))
5938 vec = IXGBE_RX_VEC_START;
5939 intr->mask |= (1 << vec);
5940 RTE_SET_USED(queue_id);
5941 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5943 rte_intr_ack(intr_handle);
5949 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5951 struct ixgbe_interrupt *intr =
5952 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5953 struct ixgbe_hw *hw =
5954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5955 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5956 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5957 uint32_t vec = IXGBE_MISC_VEC_ID;
5959 if (rte_intr_allow_others(intr_handle))
5960 vec = IXGBE_RX_VEC_START;
5961 intr->mask &= ~(1 << vec);
5962 RTE_SET_USED(queue_id);
5963 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5969 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5972 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5974 struct ixgbe_hw *hw =
5975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976 struct ixgbe_interrupt *intr =
5977 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5979 if (queue_id < 16) {
5980 ixgbe_disable_intr(hw);
5981 intr->mask |= (1 << queue_id);
5982 ixgbe_enable_intr(dev);
5983 } else if (queue_id < 32) {
5984 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5985 mask &= (1 << queue_id);
5986 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5987 } else if (queue_id < 64) {
5988 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5989 mask &= (1 << (queue_id - 32));
5990 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5992 rte_intr_ack(intr_handle);
5998 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6001 struct ixgbe_hw *hw =
6002 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6003 struct ixgbe_interrupt *intr =
6004 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6006 if (queue_id < 16) {
6007 ixgbe_disable_intr(hw);
6008 intr->mask &= ~(1 << queue_id);
6009 ixgbe_enable_intr(dev);
6010 } else if (queue_id < 32) {
6011 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6012 mask &= ~(1 << queue_id);
6013 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6014 } else if (queue_id < 64) {
6015 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6016 mask &= ~(1 << (queue_id - 32));
6017 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6024 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6025 uint8_t queue, uint8_t msix_vector)
6029 if (direction == -1) {
6031 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6032 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6035 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6037 /* rx or tx cause */
6038 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6039 idx = ((16 * (queue & 1)) + (8 * direction));
6040 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6041 tmp &= ~(0xFF << idx);
6042 tmp |= (msix_vector << idx);
6043 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6048 * set the IVAR registers, mapping interrupt causes to vectors
6050 * pointer to ixgbe_hw struct
6052 * 0 for Rx, 1 for Tx, -1 for other causes
6054 * queue to map the corresponding interrupt to
6056 * the vector to map to the corresponding queue
6059 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6060 uint8_t queue, uint8_t msix_vector)
6064 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6065 if (hw->mac.type == ixgbe_mac_82598EB) {
6066 if (direction == -1)
6068 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6069 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6070 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6071 tmp |= (msix_vector << (8 * (queue & 0x3)));
6072 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6073 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6074 (hw->mac.type == ixgbe_mac_X540) ||
6075 (hw->mac.type == ixgbe_mac_X550) ||
6076 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6077 if (direction == -1) {
6079 idx = ((queue & 1) * 8);
6080 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6081 tmp &= ~(0xFF << idx);
6082 tmp |= (msix_vector << idx);
6083 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6085 /* rx or tx causes */
6086 idx = ((16 * (queue & 1)) + (8 * direction));
6087 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6088 tmp &= ~(0xFF << idx);
6089 tmp |= (msix_vector << idx);
6090 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6096 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6098 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6099 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6100 struct ixgbe_hw *hw =
6101 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6104 uint32_t base = IXGBE_MISC_VEC_ID;
6106 /* Configure VF other cause ivar */
6107 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6109 /* won't configure msix register if no mapping is done
6110 * between intr vector and event fd.
6112 if (!rte_intr_dp_is_en(intr_handle))
6115 if (rte_intr_allow_others(intr_handle)) {
6116 base = IXGBE_RX_VEC_START;
6117 vector_idx = IXGBE_RX_VEC_START;
6120 /* Configure all RX queues of VF */
6121 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6122 /* Force all queue use vector 0,
6123 * as IXGBE_VF_MAXMSIVECOTR = 1
6125 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6126 intr_handle->intr_vec[q_idx] = vector_idx;
6127 if (vector_idx < base + intr_handle->nb_efd - 1)
6131 /* As RX queue setting above show, all queues use the vector 0.
6132 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6134 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6135 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6136 | IXGBE_EITR_CNT_WDIS);
6140 * Sets up the hardware to properly generate MSI-X interrupts
6142 * board private structure
6145 ixgbe_configure_msix(struct rte_eth_dev *dev)
6147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6148 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6149 struct ixgbe_hw *hw =
6150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6151 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6152 uint32_t vec = IXGBE_MISC_VEC_ID;
6156 /* won't configure msix register if no mapping is done
6157 * between intr vector and event fd
6158 * but if misx has been enabled already, need to configure
6159 * auto clean, auto mask and throttling.
6161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6162 if (!rte_intr_dp_is_en(intr_handle) &&
6163 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6166 if (rte_intr_allow_others(intr_handle))
6167 vec = base = IXGBE_RX_VEC_START;
6169 /* setup GPIE for MSI-x mode */
6170 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6171 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6172 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6173 /* auto clearing and auto setting corresponding bits in EIMS
6174 * when MSI-X interrupt is triggered
6176 if (hw->mac.type == ixgbe_mac_82598EB) {
6177 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6179 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6180 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6184 /* Populate the IVAR table and set the ITR values to the
6185 * corresponding register.
6187 if (rte_intr_dp_is_en(intr_handle)) {
6188 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6190 /* by default, 1:1 mapping */
6191 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6192 intr_handle->intr_vec[queue_id] = vec;
6193 if (vec < base + intr_handle->nb_efd - 1)
6197 switch (hw->mac.type) {
6198 case ixgbe_mac_82598EB:
6199 ixgbe_set_ivar_map(hw, -1,
6200 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6203 case ixgbe_mac_82599EB:
6204 case ixgbe_mac_X540:
6205 case ixgbe_mac_X550:
6206 case ixgbe_mac_X550EM_x:
6207 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6213 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6214 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6215 | IXGBE_EITR_CNT_WDIS);
6217 /* set up to autoclear timer, and the vectors */
6218 mask = IXGBE_EIMS_ENABLE_MASK;
6219 mask &= ~(IXGBE_EIMS_OTHER |
6220 IXGBE_EIMS_MAILBOX |
6223 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6227 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6228 uint16_t queue_idx, uint16_t tx_rate)
6230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6231 struct rte_eth_rxmode *rxmode;
6232 uint32_t rf_dec, rf_int;
6234 uint16_t link_speed = dev->data->dev_link.link_speed;
6236 if (queue_idx >= hw->mac.max_tx_queues)
6240 /* Calculate the rate factor values to set */
6241 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6242 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6243 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6245 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6246 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6247 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6248 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6253 rxmode = &dev->data->dev_conf.rxmode;
6255 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6256 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6259 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6260 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6261 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6262 IXGBE_MMW_SIZE_JUMBO_FRAME);
6264 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6265 IXGBE_MMW_SIZE_DEFAULT);
6267 /* Set RTTBCNRC of queue X */
6268 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6269 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6270 IXGBE_WRITE_FLUSH(hw);
6276 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6277 __rte_unused uint32_t index,
6278 __rte_unused uint32_t pool)
6280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6284 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6285 * operation. Trap this case to avoid exhausting the [very limited]
6286 * set of PF resources used to store VF MAC addresses.
6288 if (memcmp(hw->mac.perm_addr, mac_addr,
6289 sizeof(struct rte_ether_addr)) == 0)
6291 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6293 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6294 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6295 mac_addr->addr_bytes[0],
6296 mac_addr->addr_bytes[1],
6297 mac_addr->addr_bytes[2],
6298 mac_addr->addr_bytes[3],
6299 mac_addr->addr_bytes[4],
6300 mac_addr->addr_bytes[5],
6306 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6308 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6309 struct rte_ether_addr *perm_addr =
6310 (struct rte_ether_addr *)hw->mac.perm_addr;
6311 struct rte_ether_addr *mac_addr;
6316 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6317 * not support the deletion of a given MAC address.
6318 * Instead, it imposes to delete all MAC addresses, then to add again
6319 * all MAC addresses with the exception of the one to be deleted.
6321 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6324 * Add again all MAC addresses, with the exception of the deleted one
6325 * and of the permanent MAC address.
6327 for (i = 0, mac_addr = dev->data->mac_addrs;
6328 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6329 /* Skip the deleted MAC address */
6332 /* Skip NULL MAC addresses */
6333 if (rte_is_zero_ether_addr(mac_addr))
6335 /* Skip the permanent MAC address */
6336 if (memcmp(perm_addr, mac_addr,
6337 sizeof(struct rte_ether_addr)) == 0)
6339 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6342 "Adding again MAC address "
6343 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6345 mac_addr->addr_bytes[0],
6346 mac_addr->addr_bytes[1],
6347 mac_addr->addr_bytes[2],
6348 mac_addr->addr_bytes[3],
6349 mac_addr->addr_bytes[4],
6350 mac_addr->addr_bytes[5],
6356 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6357 struct rte_ether_addr *addr)
6359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6361 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6367 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6368 struct rte_eth_syn_filter *filter,
6371 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372 struct ixgbe_filter_info *filter_info =
6373 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6377 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6380 syn_info = filter_info->syn_info;
6383 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6385 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6386 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6388 if (filter->hig_pri)
6389 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6391 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6393 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6394 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6396 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6399 filter_info->syn_info = synqf;
6400 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6401 IXGBE_WRITE_FLUSH(hw);
6406 static inline enum ixgbe_5tuple_protocol
6407 convert_protocol_type(uint8_t protocol_value)
6409 if (protocol_value == IPPROTO_TCP)
6410 return IXGBE_FILTER_PROTOCOL_TCP;
6411 else if (protocol_value == IPPROTO_UDP)
6412 return IXGBE_FILTER_PROTOCOL_UDP;
6413 else if (protocol_value == IPPROTO_SCTP)
6414 return IXGBE_FILTER_PROTOCOL_SCTP;
6416 return IXGBE_FILTER_PROTOCOL_NONE;
6419 /* inject a 5-tuple filter to HW */
6421 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6422 struct ixgbe_5tuple_filter *filter)
6424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6426 uint32_t ftqf, sdpqf;
6427 uint32_t l34timir = 0;
6428 uint8_t mask = 0xff;
6432 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6433 IXGBE_SDPQF_DSTPORT_SHIFT);
6434 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6436 ftqf = (uint32_t)(filter->filter_info.proto &
6437 IXGBE_FTQF_PROTOCOL_MASK);
6438 ftqf |= (uint32_t)((filter->filter_info.priority &
6439 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6440 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6441 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6442 if (filter->filter_info.dst_ip_mask == 0)
6443 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6444 if (filter->filter_info.src_port_mask == 0)
6445 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6446 if (filter->filter_info.dst_port_mask == 0)
6447 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6448 if (filter->filter_info.proto_mask == 0)
6449 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6450 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6451 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6452 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6454 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6455 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6456 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6457 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6459 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6460 l34timir |= (uint32_t)(filter->queue <<
6461 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6462 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6466 * add a 5tuple filter
6469 * dev: Pointer to struct rte_eth_dev.
6470 * index: the index the filter allocates.
6471 * filter: ponter to the filter that will be added.
6472 * rx_queue: the queue id the filter assigned to.
6475 * - On success, zero.
6476 * - On failure, a negative value.
6479 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6480 struct ixgbe_5tuple_filter *filter)
6482 struct ixgbe_filter_info *filter_info =
6483 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6487 * look for an unused 5tuple filter index,
6488 * and insert the filter to list.
6490 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6491 idx = i / (sizeof(uint32_t) * NBBY);
6492 shift = i % (sizeof(uint32_t) * NBBY);
6493 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6494 filter_info->fivetuple_mask[idx] |= 1 << shift;
6496 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6502 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6503 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6507 ixgbe_inject_5tuple_filter(dev, filter);
6513 * remove a 5tuple filter
6516 * dev: Pointer to struct rte_eth_dev.
6517 * filter: the pointer of the filter will be removed.
6520 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6521 struct ixgbe_5tuple_filter *filter)
6523 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6524 struct ixgbe_filter_info *filter_info =
6525 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6526 uint16_t index = filter->index;
6528 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6529 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6530 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6533 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6534 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6535 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6536 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6537 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6541 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6543 struct ixgbe_hw *hw;
6544 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6545 struct rte_eth_dev_data *dev_data = dev->data;
6547 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6549 if (mtu < RTE_ETHER_MIN_MTU ||
6550 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6553 /* If device is started, refuse mtu that requires the support of
6554 * scattered packets when this feature has not been enabled before.
6556 if (dev_data->dev_started && !dev_data->scattered_rx &&
6557 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6558 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6559 PMD_INIT_LOG(ERR, "Stop port first.");
6564 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6565 * request of the version 2.0 of the mailbox API.
6566 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6567 * of the mailbox API.
6568 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6569 * prior to 3.11.33 which contains the following change:
6570 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6572 if (ixgbevf_rlpml_set_vf(hw, max_frame))
6575 /* update max frame size */
6576 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6580 static inline struct ixgbe_5tuple_filter *
6581 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6582 struct ixgbe_5tuple_filter_info *key)
6584 struct ixgbe_5tuple_filter *it;
6586 TAILQ_FOREACH(it, filter_list, entries) {
6587 if (memcmp(key, &it->filter_info,
6588 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6595 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6597 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6598 struct ixgbe_5tuple_filter_info *filter_info)
6600 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6601 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6602 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6605 switch (filter->dst_ip_mask) {
6607 filter_info->dst_ip_mask = 0;
6608 filter_info->dst_ip = filter->dst_ip;
6611 filter_info->dst_ip_mask = 1;
6614 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6618 switch (filter->src_ip_mask) {
6620 filter_info->src_ip_mask = 0;
6621 filter_info->src_ip = filter->src_ip;
6624 filter_info->src_ip_mask = 1;
6627 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6631 switch (filter->dst_port_mask) {
6633 filter_info->dst_port_mask = 0;
6634 filter_info->dst_port = filter->dst_port;
6637 filter_info->dst_port_mask = 1;
6640 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6644 switch (filter->src_port_mask) {
6646 filter_info->src_port_mask = 0;
6647 filter_info->src_port = filter->src_port;
6650 filter_info->src_port_mask = 1;
6653 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6657 switch (filter->proto_mask) {
6659 filter_info->proto_mask = 0;
6660 filter_info->proto =
6661 convert_protocol_type(filter->proto);
6664 filter_info->proto_mask = 1;
6667 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6671 filter_info->priority = (uint8_t)filter->priority;
6676 * add or delete a ntuple filter
6679 * dev: Pointer to struct rte_eth_dev.
6680 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6681 * add: if true, add filter, if false, remove filter
6684 * - On success, zero.
6685 * - On failure, a negative value.
6688 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6689 struct rte_eth_ntuple_filter *ntuple_filter,
6692 struct ixgbe_filter_info *filter_info =
6693 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6694 struct ixgbe_5tuple_filter_info filter_5tuple;
6695 struct ixgbe_5tuple_filter *filter;
6698 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6699 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6703 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6704 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6708 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6710 if (filter != NULL && add) {
6711 PMD_DRV_LOG(ERR, "filter exists.");
6714 if (filter == NULL && !add) {
6715 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6720 filter = rte_zmalloc("ixgbe_5tuple_filter",
6721 sizeof(struct ixgbe_5tuple_filter), 0);
6724 rte_memcpy(&filter->filter_info,
6726 sizeof(struct ixgbe_5tuple_filter_info));
6727 filter->queue = ntuple_filter->queue;
6728 ret = ixgbe_add_5tuple_filter(dev, filter);
6734 ixgbe_remove_5tuple_filter(dev, filter);
6740 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6741 struct rte_eth_ethertype_filter *filter,
6744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745 struct ixgbe_filter_info *filter_info =
6746 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6750 struct ixgbe_ethertype_filter ethertype_filter;
6752 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6755 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6756 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6757 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6758 " ethertype filter.", filter->ether_type);
6762 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6763 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6766 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6767 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6771 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6772 if (ret >= 0 && add) {
6773 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6774 filter->ether_type);
6777 if (ret < 0 && !add) {
6778 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6779 filter->ether_type);
6784 etqf = IXGBE_ETQF_FILTER_EN;
6785 etqf |= (uint32_t)filter->ether_type;
6786 etqs |= (uint32_t)((filter->queue <<
6787 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6788 IXGBE_ETQS_RX_QUEUE);
6789 etqs |= IXGBE_ETQS_QUEUE_EN;
6791 ethertype_filter.ethertype = filter->ether_type;
6792 ethertype_filter.etqf = etqf;
6793 ethertype_filter.etqs = etqs;
6794 ethertype_filter.conf = FALSE;
6795 ret = ixgbe_ethertype_filter_insert(filter_info,
6798 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6802 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6806 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6807 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6808 IXGBE_WRITE_FLUSH(hw);
6814 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6815 const struct rte_flow_ops **ops)
6817 *ops = &ixgbe_flow_ops;
6822 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6823 u8 **mc_addr_ptr, u32 *vmdq)
6828 mc_addr = *mc_addr_ptr;
6829 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6834 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6835 struct rte_ether_addr *mc_addr_set,
6836 uint32_t nb_mc_addr)
6838 struct ixgbe_hw *hw;
6841 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6842 mc_addr_list = (u8 *)mc_addr_set;
6843 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6844 ixgbe_dev_addr_list_itr, TRUE);
6848 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6851 uint64_t systime_cycles;
6853 switch (hw->mac.type) {
6854 case ixgbe_mac_X550:
6855 case ixgbe_mac_X550EM_x:
6856 case ixgbe_mac_X550EM_a:
6857 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6858 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6859 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6863 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6864 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6868 return systime_cycles;
6872 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6874 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875 uint64_t rx_tstamp_cycles;
6877 switch (hw->mac.type) {
6878 case ixgbe_mac_X550:
6879 case ixgbe_mac_X550EM_x:
6880 case ixgbe_mac_X550EM_a:
6881 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6882 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6883 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6887 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6888 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6889 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6893 return rx_tstamp_cycles;
6897 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900 uint64_t tx_tstamp_cycles;
6902 switch (hw->mac.type) {
6903 case ixgbe_mac_X550:
6904 case ixgbe_mac_X550EM_x:
6905 case ixgbe_mac_X550EM_a:
6906 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6907 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6908 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6912 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6913 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6914 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6918 return tx_tstamp_cycles;
6922 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925 struct ixgbe_adapter *adapter = dev->data->dev_private;
6926 struct rte_eth_link link;
6927 uint32_t incval = 0;
6930 /* Get current link speed. */
6931 ixgbe_dev_link_update(dev, 1);
6932 rte_eth_linkstatus_get(dev, &link);
6934 switch (link.link_speed) {
6935 case ETH_SPEED_NUM_100M:
6936 incval = IXGBE_INCVAL_100;
6937 shift = IXGBE_INCVAL_SHIFT_100;
6939 case ETH_SPEED_NUM_1G:
6940 incval = IXGBE_INCVAL_1GB;
6941 shift = IXGBE_INCVAL_SHIFT_1GB;
6943 case ETH_SPEED_NUM_10G:
6945 incval = IXGBE_INCVAL_10GB;
6946 shift = IXGBE_INCVAL_SHIFT_10GB;
6950 switch (hw->mac.type) {
6951 case ixgbe_mac_X550:
6952 case ixgbe_mac_X550EM_x:
6953 case ixgbe_mac_X550EM_a:
6954 /* Independent of link speed. */
6956 /* Cycles read will be interpreted as ns. */
6959 case ixgbe_mac_X540:
6960 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6962 case ixgbe_mac_82599EB:
6963 incval >>= IXGBE_INCVAL_SHIFT_82599;
6964 shift -= IXGBE_INCVAL_SHIFT_82599;
6965 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6966 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6969 /* Not supported. */
6973 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6974 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6975 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6977 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6978 adapter->systime_tc.cc_shift = shift;
6979 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6981 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6982 adapter->rx_tstamp_tc.cc_shift = shift;
6983 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6985 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6986 adapter->tx_tstamp_tc.cc_shift = shift;
6987 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6991 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6993 struct ixgbe_adapter *adapter = dev->data->dev_private;
6995 adapter->systime_tc.nsec += delta;
6996 adapter->rx_tstamp_tc.nsec += delta;
6997 adapter->tx_tstamp_tc.nsec += delta;
7003 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7006 struct ixgbe_adapter *adapter = dev->data->dev_private;
7008 ns = rte_timespec_to_ns(ts);
7009 /* Set the timecounters to a new value. */
7010 adapter->systime_tc.nsec = ns;
7011 adapter->rx_tstamp_tc.nsec = ns;
7012 adapter->tx_tstamp_tc.nsec = ns;
7018 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7020 uint64_t ns, systime_cycles;
7021 struct ixgbe_adapter *adapter = dev->data->dev_private;
7023 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7024 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7025 *ts = rte_ns_to_timespec(ns);
7031 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7033 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037 /* Stop the timesync system time. */
7038 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7039 /* Reset the timesync system time value. */
7040 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7041 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7043 /* Enable system time for platforms where it isn't on by default. */
7044 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7045 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7046 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7048 ixgbe_start_timecounters(dev);
7050 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7051 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7052 (RTE_ETHER_TYPE_1588 |
7053 IXGBE_ETQF_FILTER_EN |
7056 /* Enable timestamping of received PTP packets. */
7057 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7058 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7059 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7061 /* Enable timestamping of transmitted PTP packets. */
7062 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7063 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7064 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7066 IXGBE_WRITE_FLUSH(hw);
7072 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7077 /* Disable timestamping of transmitted PTP packets. */
7078 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7079 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7080 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7082 /* Disable timestamping of received PTP packets. */
7083 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7084 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7085 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7087 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7088 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7090 /* Stop incrementating the System Time registers. */
7091 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7097 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7098 struct timespec *timestamp,
7099 uint32_t flags __rte_unused)
7101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7102 struct ixgbe_adapter *adapter = dev->data->dev_private;
7103 uint32_t tsync_rxctl;
7104 uint64_t rx_tstamp_cycles;
7107 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7108 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7111 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7112 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7113 *timestamp = rte_ns_to_timespec(ns);
7119 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7120 struct timespec *timestamp)
7122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123 struct ixgbe_adapter *adapter = dev->data->dev_private;
7124 uint32_t tsync_txctl;
7125 uint64_t tx_tstamp_cycles;
7128 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7129 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7132 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7133 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7134 *timestamp = rte_ns_to_timespec(ns);
7140 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7142 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145 const struct reg_info *reg_group;
7146 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7147 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7149 while ((reg_group = reg_set[g_ind++]))
7150 count += ixgbe_regs_group_count(reg_group);
7156 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7160 const struct reg_info *reg_group;
7162 while ((reg_group = ixgbevf_regs[g_ind++]))
7163 count += ixgbe_regs_group_count(reg_group);
7169 ixgbe_get_regs(struct rte_eth_dev *dev,
7170 struct rte_dev_reg_info *regs)
7172 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7173 uint32_t *data = regs->data;
7176 const struct reg_info *reg_group;
7177 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7178 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7181 regs->length = ixgbe_get_reg_length(dev);
7182 regs->width = sizeof(uint32_t);
7186 /* Support only full register dump */
7187 if ((regs->length == 0) ||
7188 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7189 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7191 while ((reg_group = reg_set[g_ind++]))
7192 count += ixgbe_read_regs_group(dev, &data[count],
7201 ixgbevf_get_regs(struct rte_eth_dev *dev,
7202 struct rte_dev_reg_info *regs)
7204 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7205 uint32_t *data = regs->data;
7208 const struct reg_info *reg_group;
7211 regs->length = ixgbevf_get_reg_length(dev);
7212 regs->width = sizeof(uint32_t);
7216 /* Support only full register dump */
7217 if ((regs->length == 0) ||
7218 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7219 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7221 while ((reg_group = ixgbevf_regs[g_ind++]))
7222 count += ixgbe_read_regs_group(dev, &data[count],
7231 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7235 /* Return unit is byte count */
7236 return hw->eeprom.word_size * 2;
7240 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7241 struct rte_dev_eeprom_info *in_eeprom)
7243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7244 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7245 uint16_t *data = in_eeprom->data;
7248 first = in_eeprom->offset >> 1;
7249 length = in_eeprom->length >> 1;
7250 if ((first > hw->eeprom.word_size) ||
7251 ((first + length) > hw->eeprom.word_size))
7254 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7256 return eeprom->ops.read_buffer(hw, first, length, data);
7260 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7261 struct rte_dev_eeprom_info *in_eeprom)
7263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7265 uint16_t *data = in_eeprom->data;
7268 first = in_eeprom->offset >> 1;
7269 length = in_eeprom->length >> 1;
7270 if ((first > hw->eeprom.word_size) ||
7271 ((first + length) > hw->eeprom.word_size))
7274 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7276 return eeprom->ops.write_buffer(hw, first, length, data);
7280 ixgbe_get_module_info(struct rte_eth_dev *dev,
7281 struct rte_eth_dev_module_info *modinfo)
7283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7285 uint8_t sff8472_rev, addr_mode;
7286 bool page_swap = false;
7288 /* Check whether we support SFF-8472 or not */
7289 status = hw->phy.ops.read_i2c_eeprom(hw,
7290 IXGBE_SFF_SFF_8472_COMP,
7295 /* addressing mode is not supported */
7296 status = hw->phy.ops.read_i2c_eeprom(hw,
7297 IXGBE_SFF_SFF_8472_SWAP,
7302 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7304 "Address change required to access page 0xA2, "
7305 "but not supported. Please report the module "
7306 "type to the driver maintainers.");
7310 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7311 /* We have a SFP, but it does not support SFF-8472 */
7312 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7313 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7315 /* We have a SFP which supports a revision of SFF-8472. */
7316 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7317 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7324 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7325 struct rte_dev_eeprom_info *info)
7327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7328 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7329 uint8_t databyte = 0xFF;
7330 uint8_t *data = info->data;
7333 if (info->length == 0)
7336 for (i = info->offset; i < info->offset + info->length; i++) {
7337 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7338 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7340 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7345 data[i - info->offset] = databyte;
7352 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7354 case ixgbe_mac_X550:
7355 case ixgbe_mac_X550EM_x:
7356 case ixgbe_mac_X550EM_a:
7357 return ETH_RSS_RETA_SIZE_512;
7358 case ixgbe_mac_X550_vf:
7359 case ixgbe_mac_X550EM_x_vf:
7360 case ixgbe_mac_X550EM_a_vf:
7361 return ETH_RSS_RETA_SIZE_64;
7362 case ixgbe_mac_X540_vf:
7363 case ixgbe_mac_82599_vf:
7366 return ETH_RSS_RETA_SIZE_128;
7371 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7373 case ixgbe_mac_X550:
7374 case ixgbe_mac_X550EM_x:
7375 case ixgbe_mac_X550EM_a:
7376 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7377 return IXGBE_RETA(reta_idx >> 2);
7379 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7380 case ixgbe_mac_X550_vf:
7381 case ixgbe_mac_X550EM_x_vf:
7382 case ixgbe_mac_X550EM_a_vf:
7383 return IXGBE_VFRETA(reta_idx >> 2);
7385 return IXGBE_RETA(reta_idx >> 2);
7390 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7392 case ixgbe_mac_X550_vf:
7393 case ixgbe_mac_X550EM_x_vf:
7394 case ixgbe_mac_X550EM_a_vf:
7395 return IXGBE_VFMRQC;
7402 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7404 case ixgbe_mac_X550_vf:
7405 case ixgbe_mac_X550EM_x_vf:
7406 case ixgbe_mac_X550EM_a_vf:
7407 return IXGBE_VFRSSRK(i);
7409 return IXGBE_RSSRK(i);
7414 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7416 case ixgbe_mac_82599_vf:
7417 case ixgbe_mac_X540_vf:
7425 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7426 struct rte_eth_dcb_info *dcb_info)
7428 struct ixgbe_dcb_config *dcb_config =
7429 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7430 struct ixgbe_dcb_tc_config *tc;
7431 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7435 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7436 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7438 dcb_info->nb_tcs = 1;
7440 tc_queue = &dcb_info->tc_queue;
7441 nb_tcs = dcb_info->nb_tcs;
7443 if (dcb_config->vt_mode) { /* vt is enabled*/
7444 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7445 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7446 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7447 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7448 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7449 for (j = 0; j < nb_tcs; j++) {
7450 tc_queue->tc_rxq[0][j].base = j;
7451 tc_queue->tc_rxq[0][j].nb_queue = 1;
7452 tc_queue->tc_txq[0][j].base = j;
7453 tc_queue->tc_txq[0][j].nb_queue = 1;
7456 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7457 for (j = 0; j < nb_tcs; j++) {
7458 tc_queue->tc_rxq[i][j].base =
7460 tc_queue->tc_rxq[i][j].nb_queue = 1;
7461 tc_queue->tc_txq[i][j].base =
7463 tc_queue->tc_txq[i][j].nb_queue = 1;
7467 } else { /* vt is disabled*/
7468 struct rte_eth_dcb_rx_conf *rx_conf =
7469 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7470 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7471 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7472 if (dcb_info->nb_tcs == ETH_4_TCS) {
7473 for (i = 0; i < dcb_info->nb_tcs; i++) {
7474 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7475 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7477 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7478 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7479 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7480 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7481 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7482 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7483 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7484 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7485 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7486 for (i = 0; i < dcb_info->nb_tcs; i++) {
7487 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7488 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7490 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7491 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7492 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7493 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7494 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7495 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7496 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7497 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7498 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7499 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7500 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7501 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7502 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7503 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7504 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7505 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7508 for (i = 0; i < dcb_info->nb_tcs; i++) {
7509 tc = &dcb_config->tc_config[i];
7510 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7515 /* Update e-tag ether type */
7517 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7518 uint16_t ether_type)
7520 uint32_t etag_etype;
7522 if (hw->mac.type != ixgbe_mac_X550 &&
7523 hw->mac.type != ixgbe_mac_X550EM_x &&
7524 hw->mac.type != ixgbe_mac_X550EM_a) {
7528 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7529 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7530 etag_etype |= ether_type;
7531 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7532 IXGBE_WRITE_FLUSH(hw);
7537 /* Enable e-tag tunnel */
7539 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7541 uint32_t etag_etype;
7543 if (hw->mac.type != ixgbe_mac_X550 &&
7544 hw->mac.type != ixgbe_mac_X550EM_x &&
7545 hw->mac.type != ixgbe_mac_X550EM_a) {
7549 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7550 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7551 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7552 IXGBE_WRITE_FLUSH(hw);
7558 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7559 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7563 uint32_t i, rar_entries;
7564 uint32_t rar_low, rar_high;
7566 if (hw->mac.type != ixgbe_mac_X550 &&
7567 hw->mac.type != ixgbe_mac_X550EM_x &&
7568 hw->mac.type != ixgbe_mac_X550EM_a) {
7572 rar_entries = ixgbe_get_num_rx_addrs(hw);
7574 for (i = 1; i < rar_entries; i++) {
7575 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7576 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7577 if ((rar_high & IXGBE_RAH_AV) &&
7578 (rar_high & IXGBE_RAH_ADTYPE) &&
7579 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7580 l2_tunnel->tunnel_id)) {
7581 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7582 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7584 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7594 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7595 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7599 uint32_t i, rar_entries;
7600 uint32_t rar_low, rar_high;
7602 if (hw->mac.type != ixgbe_mac_X550 &&
7603 hw->mac.type != ixgbe_mac_X550EM_x &&
7604 hw->mac.type != ixgbe_mac_X550EM_a) {
7608 /* One entry for one tunnel. Try to remove potential existing entry. */
7609 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7611 rar_entries = ixgbe_get_num_rx_addrs(hw);
7613 for (i = 1; i < rar_entries; i++) {
7614 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7615 if (rar_high & IXGBE_RAH_AV) {
7618 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7619 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7620 rar_low = l2_tunnel->tunnel_id;
7622 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7623 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7629 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7630 " Please remove a rule before adding a new one.");
7634 static inline struct ixgbe_l2_tn_filter *
7635 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7636 struct ixgbe_l2_tn_key *key)
7640 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7644 return l2_tn_info->hash_map[ret];
7648 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7649 struct ixgbe_l2_tn_filter *l2_tn_filter)
7653 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7654 &l2_tn_filter->key);
7658 "Failed to insert L2 tunnel filter"
7659 " to hash table %d!",
7664 l2_tn_info->hash_map[ret] = l2_tn_filter;
7666 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7672 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7673 struct ixgbe_l2_tn_key *key)
7676 struct ixgbe_l2_tn_filter *l2_tn_filter;
7678 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7682 "No such L2 tunnel filter to delete %d!",
7687 l2_tn_filter = l2_tn_info->hash_map[ret];
7688 l2_tn_info->hash_map[ret] = NULL;
7690 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7691 rte_free(l2_tn_filter);
7696 /* Add l2 tunnel filter */
7698 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7699 struct ixgbe_l2_tunnel_conf *l2_tunnel,
7703 struct ixgbe_l2_tn_info *l2_tn_info =
7704 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7705 struct ixgbe_l2_tn_key key;
7706 struct ixgbe_l2_tn_filter *node;
7709 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7710 key.tn_id = l2_tunnel->tunnel_id;
7712 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7716 "The L2 tunnel filter already exists!");
7720 node = rte_zmalloc("ixgbe_l2_tn",
7721 sizeof(struct ixgbe_l2_tn_filter),
7726 rte_memcpy(&node->key,
7728 sizeof(struct ixgbe_l2_tn_key));
7729 node->pool = l2_tunnel->pool;
7730 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7737 switch (l2_tunnel->l2_tunnel_type) {
7738 case RTE_L2_TUNNEL_TYPE_E_TAG:
7739 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7742 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7747 if ((!restore) && (ret < 0))
7748 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7753 /* Delete l2 tunnel filter */
7755 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7756 struct ixgbe_l2_tunnel_conf *l2_tunnel)
7759 struct ixgbe_l2_tn_info *l2_tn_info =
7760 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7761 struct ixgbe_l2_tn_key key;
7763 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7764 key.tn_id = l2_tunnel->tunnel_id;
7765 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7769 switch (l2_tunnel->l2_tunnel_type) {
7770 case RTE_L2_TUNNEL_TYPE_E_TAG:
7771 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7774 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7783 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7787 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7789 if (hw->mac.type != ixgbe_mac_X550 &&
7790 hw->mac.type != ixgbe_mac_X550EM_x &&
7791 hw->mac.type != ixgbe_mac_X550EM_a) {
7795 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7796 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7798 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7799 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7805 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7808 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7809 IXGBE_WRITE_FLUSH(hw);
7814 /* There's only one register for VxLAN UDP port.
7815 * So, we cannot add several ports. Will update it.
7818 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7822 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7826 return ixgbe_update_vxlan_port(hw, port);
7829 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7830 * UDP port, it must have a value.
7831 * So, will reset it to the original value 0.
7834 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7839 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7841 if (cur_port != port) {
7842 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7846 return ixgbe_update_vxlan_port(hw, 0);
7849 /* Add UDP tunneling port */
7851 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7852 struct rte_eth_udp_tunnel *udp_tunnel)
7855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7857 if (hw->mac.type != ixgbe_mac_X550 &&
7858 hw->mac.type != ixgbe_mac_X550EM_x &&
7859 hw->mac.type != ixgbe_mac_X550EM_a) {
7863 if (udp_tunnel == NULL)
7866 switch (udp_tunnel->prot_type) {
7867 case RTE_TUNNEL_TYPE_VXLAN:
7868 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7871 case RTE_TUNNEL_TYPE_GENEVE:
7872 case RTE_TUNNEL_TYPE_TEREDO:
7873 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7878 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886 /* Remove UDP tunneling port */
7888 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7889 struct rte_eth_udp_tunnel *udp_tunnel)
7892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7894 if (hw->mac.type != ixgbe_mac_X550 &&
7895 hw->mac.type != ixgbe_mac_X550EM_x &&
7896 hw->mac.type != ixgbe_mac_X550EM_a) {
7900 if (udp_tunnel == NULL)
7903 switch (udp_tunnel->prot_type) {
7904 case RTE_TUNNEL_TYPE_VXLAN:
7905 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7907 case RTE_TUNNEL_TYPE_GENEVE:
7908 case RTE_TUNNEL_TYPE_TEREDO:
7909 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7913 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7922 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7927 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7931 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7943 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7945 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7948 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7952 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7964 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7968 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7970 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7974 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7986 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7991 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7995 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8006 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8011 /* peek the message first */
8012 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8014 /* PF reset VF event */
8015 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8016 /* dummy mbx read to ack pf */
8017 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8019 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8025 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8029 struct ixgbe_interrupt *intr =
8030 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8031 ixgbevf_intr_disable(dev);
8033 /* read-on-clear nic registers here */
8034 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8037 /* only one misc vector supported - mailbox */
8038 eicr &= IXGBE_VTEICR_MASK;
8039 if (eicr == IXGBE_MISC_VEC_ID)
8040 intr->flags |= IXGBE_FLAG_MAILBOX;
8046 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8048 struct ixgbe_interrupt *intr =
8049 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8051 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8052 ixgbevf_mbx_process(dev);
8053 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8056 ixgbevf_intr_enable(dev);
8062 ixgbevf_dev_interrupt_handler(void *param)
8064 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8066 ixgbevf_dev_interrupt_get_status(dev);
8067 ixgbevf_dev_interrupt_action(dev);
8071 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8072 * @hw: pointer to hardware structure
8074 * Stops the transmit data path and waits for the HW to internally empty
8075 * the Tx security block
8077 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8079 #define IXGBE_MAX_SECTX_POLL 40
8084 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8085 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8086 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8087 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8088 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8089 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8091 /* Use interrupt-safe sleep just in case */
8095 /* For informational purposes only */
8096 if (i >= IXGBE_MAX_SECTX_POLL)
8097 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8098 "path fully disabled. Continuing with init.");
8100 return IXGBE_SUCCESS;
8104 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8105 * @hw: pointer to hardware structure
8107 * Enables the transmit data path.
8109 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8113 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8114 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8115 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8116 IXGBE_WRITE_FLUSH(hw);
8118 return IXGBE_SUCCESS;
8121 /* restore n-tuple filter */
8123 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8125 struct ixgbe_filter_info *filter_info =
8126 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8127 struct ixgbe_5tuple_filter *node;
8129 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8130 ixgbe_inject_5tuple_filter(dev, node);
8134 /* restore ethernet type filter */
8136 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8138 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8139 struct ixgbe_filter_info *filter_info =
8140 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8143 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8144 if (filter_info->ethertype_mask & (1 << i)) {
8145 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8146 filter_info->ethertype_filters[i].etqf);
8147 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8148 filter_info->ethertype_filters[i].etqs);
8149 IXGBE_WRITE_FLUSH(hw);
8154 /* restore SYN filter */
8156 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8159 struct ixgbe_filter_info *filter_info =
8160 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8163 synqf = filter_info->syn_info;
8165 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8166 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8167 IXGBE_WRITE_FLUSH(hw);
8171 /* restore L2 tunnel filter */
8173 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8175 struct ixgbe_l2_tn_info *l2_tn_info =
8176 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8177 struct ixgbe_l2_tn_filter *node;
8178 struct ixgbe_l2_tunnel_conf l2_tn_conf;
8180 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8181 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8182 l2_tn_conf.tunnel_id = node->key.tn_id;
8183 l2_tn_conf.pool = node->pool;
8184 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8188 /* restore rss filter */
8190 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8192 struct ixgbe_filter_info *filter_info =
8193 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8195 if (filter_info->rss_info.conf.queue_num)
8196 ixgbe_config_rss_filter(dev,
8197 &filter_info->rss_info, TRUE);
8201 ixgbe_filter_restore(struct rte_eth_dev *dev)
8203 ixgbe_ntuple_filter_restore(dev);
8204 ixgbe_ethertype_filter_restore(dev);
8205 ixgbe_syn_filter_restore(dev);
8206 ixgbe_fdir_filter_restore(dev);
8207 ixgbe_l2_tn_filter_restore(dev);
8208 ixgbe_rss_filter_restore(dev);
8214 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8216 struct ixgbe_l2_tn_info *l2_tn_info =
8217 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8220 if (l2_tn_info->e_tag_en)
8221 (void)ixgbe_e_tag_enable(hw);
8223 if (l2_tn_info->e_tag_fwd_en)
8224 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8226 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8229 /* remove all the n-tuple filters */
8231 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8233 struct ixgbe_filter_info *filter_info =
8234 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8235 struct ixgbe_5tuple_filter *p_5tuple;
8237 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8238 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8241 /* remove all the ether type filters */
8243 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8245 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8246 struct ixgbe_filter_info *filter_info =
8247 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8250 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8251 if (filter_info->ethertype_mask & (1 << i) &&
8252 !filter_info->ethertype_filters[i].conf) {
8253 (void)ixgbe_ethertype_filter_remove(filter_info,
8255 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8256 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8257 IXGBE_WRITE_FLUSH(hw);
8262 /* remove the SYN filter */
8264 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267 struct ixgbe_filter_info *filter_info =
8268 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8270 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8271 filter_info->syn_info = 0;
8273 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8274 IXGBE_WRITE_FLUSH(hw);
8278 /* remove all the L2 tunnel filters */
8280 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8282 struct ixgbe_l2_tn_info *l2_tn_info =
8283 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8284 struct ixgbe_l2_tn_filter *l2_tn_filter;
8285 struct ixgbe_l2_tunnel_conf l2_tn_conf;
8288 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8289 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8290 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8291 l2_tn_conf.pool = l2_tn_filter->pool;
8292 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8301 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8302 struct ixgbe_macsec_setting *macsec_setting)
8304 struct ixgbe_macsec_setting *macsec =
8305 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8307 macsec->offload_en = macsec_setting->offload_en;
8308 macsec->encrypt_en = macsec_setting->encrypt_en;
8309 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8313 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8315 struct ixgbe_macsec_setting *macsec =
8316 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8318 macsec->offload_en = 0;
8319 macsec->encrypt_en = 0;
8320 macsec->replayprotect_en = 0;
8324 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8325 struct ixgbe_macsec_setting *macsec_setting)
8327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8329 uint8_t en = macsec_setting->encrypt_en;
8330 uint8_t rp = macsec_setting->replayprotect_en;
8334 * As no ixgbe_disable_sec_rx_path equivalent is
8335 * implemented for tx in the base code, and we are
8336 * not allowed to modify the base code in DPDK, so
8337 * just call the hand-written one directly for now.
8338 * The hardware support has been checked by
8339 * ixgbe_disable_sec_rx_path().
8341 ixgbe_disable_sec_tx_path_generic(hw);
8343 /* Enable Ethernet CRC (required by MACsec offload) */
8344 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8345 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8346 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8348 /* Enable the TX and RX crypto engines */
8349 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8350 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8351 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8353 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8354 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8355 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8357 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8358 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8360 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8362 /* Enable SA lookup */
8363 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8364 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8365 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8366 IXGBE_LSECTXCTRL_AUTH;
8367 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8368 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8369 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8370 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8372 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8373 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8374 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8375 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8377 ctrl |= IXGBE_LSECRXCTRL_RP;
8379 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8380 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8382 /* Start the data paths */
8383 ixgbe_enable_sec_rx_path(hw);
8386 * As no ixgbe_enable_sec_rx_path equivalent is
8387 * implemented for tx in the base code, and we are
8388 * not allowed to modify the base code in DPDK, so
8389 * just call the hand-written one directly for now.
8391 ixgbe_enable_sec_tx_path_generic(hw);
8395 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8397 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8402 * As no ixgbe_disable_sec_rx_path equivalent is
8403 * implemented for tx in the base code, and we are
8404 * not allowed to modify the base code in DPDK, so
8405 * just call the hand-written one directly for now.
8406 * The hardware support has been checked by
8407 * ixgbe_disable_sec_rx_path().
8409 ixgbe_disable_sec_tx_path_generic(hw);
8411 /* Disable the TX and RX crypto engines */
8412 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8413 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8414 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8416 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8417 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8418 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8420 /* Disable SA lookup */
8421 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8422 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8423 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8424 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8426 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8427 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8428 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8429 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8431 /* Start the data paths */
8432 ixgbe_enable_sec_rx_path(hw);
8435 * As no ixgbe_enable_sec_rx_path equivalent is
8436 * implemented for tx in the base code, and we are
8437 * not allowed to modify the base code in DPDK, so
8438 * just call the hand-written one directly for now.
8440 ixgbe_enable_sec_tx_path_generic(hw);
8443 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8444 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8445 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8446 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8447 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8448 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8449 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8450 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8452 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8453 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8455 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8456 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8458 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8459 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8461 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8462 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);