4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "ixgbe/ixgbe_api.h"
49 #include "ixgbe/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
65 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */
66 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */
67 #define IXGBE_MAX_FLX_SOURCE_OFF 62
68 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
69 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
71 #define IXGBE_FDIR_FLOW_TYPES ( \
72 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
73 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
74 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
75 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
76 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
77 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
78 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
79 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
80 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
81 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
83 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
84 uint8_t ipv6_addr[16]; \
86 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
88 for (i = 0; i < sizeof(ipv6_addr); i++) { \
89 if (ipv6_addr[i] == UINT8_MAX) \
91 else if (ipv6_addr[i] != 0) { \
92 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
98 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
99 uint8_t ipv6_addr[16]; \
101 for (i = 0; i < sizeof(ipv6_addr); i++) { \
102 if ((ipv6m) & (1 << i)) \
103 ipv6_addr[i] = UINT8_MAX; \
107 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
110 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
111 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
112 const struct rte_eth_fdir_masks *input_mask);
113 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
114 const struct rte_eth_fdir_flex_conf *conf);
115 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
116 static int ixgbe_fdir_filter_to_atr_input(
117 const struct rte_eth_fdir_filter *fdir_filter,
118 union ixgbe_atr_input *input);
119 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
121 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
122 enum rte_fdir_pballoc_type pballoc);
123 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
124 enum rte_fdir_pballoc_type pballoc);
125 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
126 union ixgbe_atr_input *input, uint8_t queue,
127 uint32_t fdircmd, uint32_t fdirhash);
128 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
129 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
131 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
132 const struct rte_eth_fdir_filter *fdir_filter,
135 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
136 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
137 struct rte_eth_fdir_info *fdir_info);
138 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
139 struct rte_eth_fdir_stats *fdir_stats);
142 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
143 * It adds extra configuration of fdirctrl that is common for all filter types.
145 * Initialize Flow Director control registers
146 * @hw: pointer to hardware structure
147 * @fdirctrl: value to write to flow director control register
150 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
154 PMD_INIT_FUNC_TRACE();
156 /* Prime the keys for hashing */
157 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
158 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
161 * Continue setup of fdirctrl register bits:
162 * Set the maximum length per hash bucket to 0xA filters
163 * Send interrupt when 64 filters are left
165 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
166 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
169 * Poll init-done after we write the register. Estimated times:
170 * 10G: PBALLOC = 11b, timing is 60us
171 * 1G: PBALLOC = 11b, timing is 600us
172 * 100M: PBALLOC = 11b, timing is 6ms
174 * Multiple these timings by 4 if under full Rx load
176 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
177 * 1 msec per poll time. If we're at line rate and drop to 100M, then
178 * this might not finish in our poll time, but we can live with that
181 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
182 IXGBE_WRITE_FLUSH(hw);
183 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
184 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
185 IXGBE_FDIRCTRL_INIT_DONE)
190 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
191 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded "
199 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
200 * flexbytes matching field, and drop queue (only for perfect matching mode).
203 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
207 switch (conf->pballoc) {
208 case RTE_FDIR_PBALLOC_64K:
209 /* 8k - 1 signature filters */
210 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
212 case RTE_FDIR_PBALLOC_128K:
213 /* 16k - 1 signature filters */
214 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
216 case RTE_FDIR_PBALLOC_256K:
217 /* 32k - 1 signature filters */
218 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
222 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
226 /* status flags: write hash & swindex in the rx descriptor */
227 switch (conf->status) {
228 case RTE_FDIR_NO_REPORT_STATUS:
229 /* do nothing, default mode */
231 case RTE_FDIR_REPORT_STATUS:
232 /* report status when the packet matches a fdir rule */
233 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
235 case RTE_FDIR_REPORT_STATUS_ALWAYS:
236 /* always report status */
237 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
241 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
245 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
246 IXGBE_FDIRCTRL_FLEX_SHIFT;
248 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
249 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
250 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
253 * Continue setup of fdirctrl register bits:
254 * Set the maximum length per hash bucket to 0xA filters
255 * Send interrupt when 64 filters are left
257 *fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
258 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
264 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
266 * @hi_dword: Bits 31:16 mask to be bit swapped.
267 * @lo_dword: Bits 15:0 mask to be bit swapped.
269 * Flow director uses several registers to store 2 x 16 bit masks with the
270 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
271 * mask affects the MS bit/byte of the target. This function reverses the
272 * bits in these masks.
274 static inline uint32_t
275 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
277 uint32_t mask = hi_dword << 16;
279 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
280 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
281 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
282 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
286 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
287 * but makes use of the rte_fdir_masks structure to see which bits to set.
290 fdir_set_input_mask_82599(struct rte_eth_dev *dev,
291 const struct rte_eth_fdir_masks *input_mask)
293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
294 struct ixgbe_hw_fdir_info *info =
295 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
297 * mask VM pool and DIPv6 since there are currently not supported
298 * mask FLEX byte, it will be set in flex_conf
300 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
301 uint32_t fdirtcpm; /* TCP source and destination port masks. */
302 uint32_t fdiripv6m; /* IPv6 source and destination masks. */
303 uint16_t dst_ipv6m = 0;
304 uint16_t src_ipv6m = 0;
306 PMD_INIT_FUNC_TRACE();
309 * Program the relevant mask registers. If src/dst_port or src/dst_addr
310 * are zero, then assume a full mask for that field. Also assume that
311 * a VLAN of 0 is unspecified, so mask that out as well. L4type
312 * cannot be masked out in this implementation.
314 if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
315 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
316 fdirm |= IXGBE_FDIRM_L4P;
318 if (input_mask->vlan_tci_mask == 0x0FFF)
319 /* mask VLAN Priority */
320 fdirm |= IXGBE_FDIRM_VLANP;
321 else if (input_mask->vlan_tci_mask == 0xE000)
323 fdirm |= IXGBE_FDIRM_VLANID;
324 else if (input_mask->vlan_tci_mask == 0)
325 /* mask VLAN ID and Priority */
326 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
327 else if (input_mask->vlan_tci_mask != 0xEFFF) {
328 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
331 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
333 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
335 /* store the TCP/UDP port masks, bit reversed from port layout */
336 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
337 input_mask->src_port_mask);
339 /* write both the same so that UDP and TCP use the same mask */
340 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
341 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
342 info->mask.src_port_mask = input_mask->src_port_mask;
343 info->mask.dst_port_mask = input_mask->dst_port_mask;
345 /* Store source and destination IPv4 masks (big-endian) */
346 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));
347 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));
348 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
349 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
351 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
353 * IPv6 mask is only meaningful in signature mode
354 * Store source and destination IPv6 masks (bit reversed)
356 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
357 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
358 fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
360 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
361 info->mask.src_ipv6_mask = src_ipv6m;
362 info->mask.dst_ipv6_mask = dst_ipv6m;
365 return IXGBE_SUCCESS;
369 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
370 * arguments are valid
373 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
374 const struct rte_eth_fdir_flex_conf *conf)
376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
377 struct ixgbe_hw_fdir_info *info =
378 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
379 const struct rte_eth_flex_payload_cfg *flex_cfg;
380 const struct rte_eth_fdir_flex_mask *flex_mask;
381 uint32_t fdirctrl, fdirm;
382 uint16_t flexbytes = 0;
385 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
386 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
389 PMD_DRV_LOG(INFO, "NULL pointer.");
393 for (i = 0; i < conf->nb_payloads; i++) {
394 flex_cfg = &conf->flex_set[i];
395 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
396 PMD_DRV_LOG(ERR, "unsupported payload type.");
399 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
400 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
401 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
402 fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
403 fdirctrl |= (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
404 IXGBE_FDIRCTRL_FLEX_SHIFT;
406 PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
411 for (i = 0; i < conf->nb_flexmasks; i++) {
412 flex_mask = &conf->flex_mask[i];
413 if (flex_mask->flow_type != RTE_ETH_FLOW_RAW) {
414 PMD_DRV_LOG(ERR, "unsupported flow type.");
417 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
418 ((flex_mask->mask[1]) & 0xFF));
419 if (flexbytes == UINT16_MAX)
420 fdirm &= ~IXGBE_FDIRM_FLEX;
421 else if (flexbytes != 0) {
422 /* IXGBE_FDIRM_FLEX is set by default when set mask */
423 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
427 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
428 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
429 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
430 info->flex_bytes_offset = (uint8_t)((fdirctrl &
431 IXGBE_FDIRCTRL_FLEX_MASK) >>
432 IXGBE_FDIRCTRL_FLEX_SHIFT);
437 ixgbe_fdir_configure(struct rte_eth_dev *dev)
439 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
441 uint32_t fdirctrl, pbsize;
444 PMD_INIT_FUNC_TRACE();
446 if (hw->mac.type != ixgbe_mac_82599EB &&
447 hw->mac.type != ixgbe_mac_X540 &&
448 hw->mac.type != ixgbe_mac_X550 &&
449 hw->mac.type != ixgbe_mac_X550EM_x)
452 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
457 * Before enabling Flow Director, the Rx Packet Buffer size
458 * must be reduced. The new value is the current size minus
459 * flow director memory usage size.
461 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
462 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
463 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
466 * The defaults in the HW for RX PB 1-7 are not zero and so should be
467 * intialized to zero for non DCB mode otherwise actual total RX PB
468 * would be bigger than programmed and filter space would run into
471 for (i = 1; i < 8; i++)
472 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
474 err = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);
476 PMD_INIT_LOG(ERR, " Error on setting FD mask");
479 err = ixgbe_set_fdir_flex_conf(dev,
480 &dev->data->dev_conf.fdir_conf.flex_conf);
482 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
486 err = fdir_enable_82599(hw, fdirctrl);
488 PMD_INIT_LOG(ERR, " Error on enabling FD.");
495 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
496 * by the IXGBE driver code.
499 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
500 union ixgbe_atr_input *input)
502 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
503 input->formatted.flex_bytes = (uint16_t)(
504 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
505 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
507 switch (fdir_filter->input.flow_type) {
508 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
509 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
511 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
512 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
514 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
515 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
517 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
518 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
520 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
521 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
523 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
524 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
526 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
527 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
529 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
530 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
533 PMD_DRV_LOG(ERR, " Error on flow_type input");
537 switch (fdir_filter->input.flow_type) {
538 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
539 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
540 input->formatted.src_port =
541 fdir_filter->input.flow.udp4_flow.src_port;
542 input->formatted.dst_port =
543 fdir_filter->input.flow.udp4_flow.dst_port;
544 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
545 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
546 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
547 input->formatted.src_ip[0] =
548 fdir_filter->input.flow.ip4_flow.src_ip;
549 input->formatted.dst_ip[0] =
550 fdir_filter->input.flow.ip4_flow.dst_ip;
553 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
554 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
555 input->formatted.src_port =
556 fdir_filter->input.flow.udp6_flow.src_port;
557 input->formatted.dst_port =
558 fdir_filter->input.flow.udp6_flow.dst_port;
559 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
560 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
561 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
562 rte_memcpy(input->formatted.src_ip,
563 fdir_filter->input.flow.ipv6_flow.src_ip,
564 sizeof(input->formatted.src_ip));
565 rte_memcpy(input->formatted.dst_ip,
566 fdir_filter->input.flow.ipv6_flow.dst_ip,
567 sizeof(input->formatted.dst_ip));
570 PMD_DRV_LOG(ERR, " Error on flow_type input");
578 * The below function is taken from the FreeBSD IXGBE drivers release
579 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
580 * before returning, as the signature hash can use 16bits.
582 * The newer driver has optimised functions for calculating bucket and
583 * signature hashes. However they don't support IPv6 type packets for signature
584 * filters so are not used here.
586 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
589 * Compute the hashes for SW ATR
590 * @stream: input bitstream to compute the hash on
591 * @key: 32-bit hash key
594 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
598 * The algorithm is as follows:
599 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
600 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
601 * and A[n] x B[n] is bitwise AND between same length strings
603 * K[n] is 16 bits, defined as:
604 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
605 * for n modulo 32 < 15, K[n] =
606 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
608 * S[n] is 16 bits, defined as:
609 * for n >= 15, S[n] = S[n:n - 15]
610 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
612 * To simplify for programming, the algorithm is implemented
613 * in software this way:
615 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
617 * for (i = 0; i < 352; i+=32)
618 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
620 * lo_hash_dword[15:0] ^= Stream[15:0];
621 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
622 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
624 * hi_hash_dword[31:0] ^= Stream[351:320];
627 * hash[15:0] ^= Stream[15:0];
629 * for (i = 0; i < 16; i++) {
631 * hash[15:0] ^= lo_hash_dword[(i+15):i];
633 * hash[15:0] ^= hi_hash_dword[(i+15):i];
637 __be32 common_hash_dword = 0;
638 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
642 /* record the flow_vm_vlan bits as they are a key part to the hash */
643 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
645 /* generate common hash dword */
646 for (i = 1; i <= 13; i++)
647 common_hash_dword ^= atr_input->dword_stream[i];
649 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
651 /* low dword is word swapped version of common */
652 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
654 /* apply flow ID/VM pool/VLAN ID bits to hash words */
655 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
657 /* Process bits 0 and 16 */
658 if (key & 0x0001) hash_result ^= lo_hash_dword;
659 if (key & 0x00010000) hash_result ^= hi_hash_dword;
662 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
663 * delay this because bit 0 of the stream should not be processed
664 * so we do not add the vlan until after bit 0 was processed
666 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
669 /* process the remaining 30 bits in the key 2 bits at a time */
670 for (i = 15; i; i-- ) {
671 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
672 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
679 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
680 enum rte_fdir_pballoc_type pballoc)
682 if (pballoc == RTE_FDIR_PBALLOC_256K)
683 return ixgbe_atr_compute_hash_82599(input,
684 IXGBE_ATR_BUCKET_HASH_KEY) &
685 PERFECT_BUCKET_256KB_HASH_MASK;
686 else if (pballoc == RTE_FDIR_PBALLOC_128K)
687 return ixgbe_atr_compute_hash_82599(input,
688 IXGBE_ATR_BUCKET_HASH_KEY) &
689 PERFECT_BUCKET_128KB_HASH_MASK;
691 return ixgbe_atr_compute_hash_82599(input,
692 IXGBE_ATR_BUCKET_HASH_KEY) &
693 PERFECT_BUCKET_64KB_HASH_MASK;
697 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
698 * @hw: pointer to hardware structure
701 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
705 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
706 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
707 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
709 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
716 * Calculate the hash value needed for signature-match filters. In the FreeBSD
717 * driver, this is done by the optimised function
718 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
719 * doesn't support calculating a hash for an IPv6 filter.
722 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
723 enum rte_fdir_pballoc_type pballoc)
725 uint32_t bucket_hash, sig_hash;
727 if (pballoc == RTE_FDIR_PBALLOC_256K)
728 bucket_hash = ixgbe_atr_compute_hash_82599(input,
729 IXGBE_ATR_BUCKET_HASH_KEY) &
730 SIG_BUCKET_256KB_HASH_MASK;
731 else if (pballoc == RTE_FDIR_PBALLOC_128K)
732 bucket_hash = ixgbe_atr_compute_hash_82599(input,
733 IXGBE_ATR_BUCKET_HASH_KEY) &
734 SIG_BUCKET_128KB_HASH_MASK;
736 bucket_hash = ixgbe_atr_compute_hash_82599(input,
737 IXGBE_ATR_BUCKET_HASH_KEY) &
738 SIG_BUCKET_64KB_HASH_MASK;
740 sig_hash = ixgbe_atr_compute_hash_82599(input,
741 IXGBE_ATR_SIGNATURE_HASH_KEY);
743 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
747 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
748 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
749 * added, and IPv6 support also added. The hash value is also pre-calculated
750 * as the pballoc value is needed to do it.
753 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
754 union ixgbe_atr_input *input, uint8_t queue,
755 uint32_t fdircmd, uint32_t fdirhash)
757 uint32_t fdirport, fdirvlan;
760 /* record the IPv4 address (big-endian) */
761 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
762 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
764 /* record source and destination port (little-endian)*/
765 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
766 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
767 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
768 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
770 /* record vlan (little-endian) and flex_bytes(big-endian) */
771 fdirvlan = input->formatted.flex_bytes;
772 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
773 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
774 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
776 /* configure FDIRHASH register */
777 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
780 * flush all previous writes to make certain registers are
781 * programmed prior to issuing the command
783 IXGBE_WRITE_FLUSH(hw);
785 /* configure FDIRCMD register */
786 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
787 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
788 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
789 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
790 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
792 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
794 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
796 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
798 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
804 * This function is based on ixgbe_atr_add_signature_filter_82599() in
805 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
806 * setting extra fields in the FDIRCMD register, and removes the code that was
807 * verifying the flow_type field. According to the documentation, a flow type of
808 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
811 * Adds a signature hash filter
812 * @hw: pointer to hardware structure
813 * @input: unique input dword
814 * @queue: queue index to direct traffic to
815 * @fdircmd: any extra flags to set in fdircmd register
816 * @fdirhash: pre-calculated hash value for the filter
819 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
820 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
825 PMD_INIT_FUNC_TRACE();
827 /* configure FDIRCMD register */
828 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
829 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
830 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
831 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
833 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
834 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
836 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
838 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
840 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
846 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
847 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
848 * that it can be used for removing signature and perfect filters.
851 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
853 uint32_t fdircmd = 0;
856 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
858 /* flush hash to HW */
859 IXGBE_WRITE_FLUSH(hw);
861 /* Query if filter is present */
862 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
864 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
866 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
870 /* if filter exists in hardware then remove it */
871 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
872 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
873 IXGBE_WRITE_FLUSH(hw);
874 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
875 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
877 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
879 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
885 * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
886 * @dev: pointer to the structure rte_eth_dev
887 * @fdir_filter: fdir filter entry
888 * @del: 1 - delete, 0 - add
889 * @update: 1 - update
892 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
893 const struct rte_eth_fdir_filter *fdir_filter,
897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
898 uint32_t fdircmd_flags;
900 union ixgbe_atr_input input;
902 bool is_perfect = FALSE;
905 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)
908 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
911 memset(&input, 0, sizeof(input));
913 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);
918 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
919 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
923 fdirhash = atr_compute_perfect_hash_82599(&input,
924 dev->data->dev_conf.fdir_conf.pballoc);
925 fdirhash |= fdir_filter->soft_id <<
926 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
928 fdirhash = atr_compute_sig_hash_82599(&input,
929 dev->data->dev_conf.fdir_conf.pballoc);
932 err = fdir_erase_filter_82599(hw, fdirhash);
934 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
936 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
939 /* add or update an fdir filter*/
940 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
941 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
943 queue = dev->data->dev_conf.fdir_conf.drop_queue;
944 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
946 PMD_DRV_LOG(ERR, "Drop option is not supported in"
950 } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
951 queue = (uint8_t)fdir_filter->action.rx_queue;
956 err = fdir_write_perfect_filter_82599(hw, &input, queue,
957 fdircmd_flags, fdirhash);
959 err = fdir_add_signature_filter_82599(hw, &input, queue,
960 fdircmd_flags, fdirhash);
963 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
965 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
971 ixgbe_fdir_flush(struct rte_eth_dev *dev)
973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
974 struct ixgbe_hw_fdir_info *info =
975 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
978 ret = ixgbe_reinit_fdir_tables_82599(hw);
980 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
992 #define FDIRENTRIES_NUM_SHIFT 10
994 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
997 struct ixgbe_hw_fdir_info *info =
998 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
999 uint32_t fdirctrl, max_num;
1002 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1003 offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1004 IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1006 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1007 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1008 (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1009 if (fdir_info->mode == RTE_FDIR_MODE_PERFECT)
1010 fdir_info->guarant_spc = max_num;
1011 else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1012 fdir_info->guarant_spc = max_num * 4;
1014 fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1015 fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1016 fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1017 IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1018 fdir_info->mask.ipv6_mask.src_ip);
1019 IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1020 fdir_info->mask.ipv6_mask.dst_ip);
1021 fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1022 fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1023 fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1024 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1025 fdir_info->flex_payload_unit = sizeof(uint16_t);
1026 fdir_info->max_flex_payload_segment_num = 1;
1027 fdir_info->flex_payload_limit = 62;
1028 fdir_info->flex_conf.nb_payloads = 1;
1029 fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1030 fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1031 fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1032 fdir_info->flex_conf.nb_flexmasks = 1;
1033 fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_RAW;
1034 fdir_info->flex_conf.flex_mask[0].mask[0] =
1035 (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1036 fdir_info->flex_conf.flex_mask[0].mask[1] =
1037 (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1041 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 struct ixgbe_hw_fdir_info *info =
1045 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1046 uint32_t reg, max_num;
1048 /* Get the information from registers */
1049 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1050 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1051 IXGBE_FDIRFREE_COLL_SHIFT);
1052 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1053 IXGBE_FDIRFREE_FREE_SHIFT);
1055 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1056 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1057 IXGBE_FDIRLEN_MAXHASH_SHIFT);
1058 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1059 IXGBE_FDIRLEN_MAXLEN_SHIFT);
1061 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1062 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1063 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1064 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1065 IXGBE_FDIRUSTAT_ADD_SHIFT;
1067 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1068 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1069 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1070 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1071 IXGBE_FDIRFSTAT_FADD_SHIFT;
1073 /* Copy the new information in the fdir parameter */
1074 fdir_stats->collision = info->collision;
1075 fdir_stats->free = info->free;
1076 fdir_stats->maxhash = info->maxhash;
1077 fdir_stats->maxlen = info->maxlen;
1078 fdir_stats->remove = info->remove;
1079 fdir_stats->add = info->add;
1080 fdir_stats->f_remove = info->f_remove;
1081 fdir_stats->f_add = info->f_add;
1083 reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1084 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1085 (reg & FDIRCTRL_PBALLOC_MASK)));
1086 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1087 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1088 else if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)
1089 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1094 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1095 * @dev: pointer to the structure rte_eth_dev
1096 * @filter_op:operation will be taken
1097 * @arg: a pointer to specific structure corresponding to the filter_op
1100 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1101 enum rte_filter_op filter_op, void *arg)
1103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1106 if (hw->mac.type != ixgbe_mac_82599EB &&
1107 hw->mac.type != ixgbe_mac_X540 &&
1108 hw->mac.type != ixgbe_mac_X550 &&
1109 hw->mac.type != ixgbe_mac_X550EM_x)
1112 if (filter_op == RTE_ETH_FILTER_NOP)
1115 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1118 switch (filter_op) {
1119 case RTE_ETH_FILTER_ADD:
1120 ret = ixgbe_add_del_fdir_filter(dev,
1121 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1123 case RTE_ETH_FILTER_UPDATE:
1124 ret = ixgbe_add_del_fdir_filter(dev,
1125 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1127 case RTE_ETH_FILTER_DELETE:
1128 ret = ixgbe_add_del_fdir_filter(dev,
1129 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1131 case RTE_ETH_FILTER_FLUSH:
1132 ret = ixgbe_fdir_flush(dev);
1134 case RTE_ETH_FILTER_INFO:
1135 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1137 case RTE_ETH_FILTER_STATS:
1138 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1141 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);