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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "ixgbe/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
55 #define IXGBE_MAX_VFTA (128)
56 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
57 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
59 static inline uint16_t
60 dev_num_vf(struct rte_eth_dev *eth_dev)
62 return eth_dev->pci_dev->max_vfs;
66 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
68 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
69 struct ixgbe_vf_info *vfinfo =
70 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
73 for (vfn = 0; vfn < vf_num; vfn++) {
74 eth_random_addr(vf_mac_addr);
75 /* keep the random address as default */
76 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
84 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
86 struct ixgbe_interrupt *intr =
87 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
89 intr->mask |= IXGBE_EICR_MAILBOX;
94 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
96 struct ixgbe_vf_info **vfinfo =
97 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
98 struct ixgbe_mirror_info *mirror_info =
99 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
100 struct ixgbe_uta_info *uta_info =
101 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
102 struct ixgbe_hw *hw =
103 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
107 PMD_INIT_FUNC_TRACE();
109 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
110 if (0 == (vf_num = dev_num_vf(eth_dev)))
113 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
115 rte_panic("Cannot allocate memory for private VF data\n");
117 memset(mirror_info,0,sizeof(struct ixgbe_mirror_info));
118 memset(uta_info,0,sizeof(struct ixgbe_uta_info));
119 hw->mac.mc_filter_type = 0;
121 if (vf_num >= ETH_32_POOLS) {
123 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
124 } else if (vf_num >= ETH_16_POOLS) {
126 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
129 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
132 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
133 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
134 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
136 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
138 /* init_mailbox_params */
139 hw->mbx.ops.init_params(hw);
141 /* set mb interrupt mask */
142 ixgbe_mb_intr_setup(eth_dev);
147 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
149 uint32_t vtctl, fcrth;
150 uint32_t vfre_slot, vfre_offset;
152 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
153 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
154 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
155 uint32_t gpie, gcr_ext;
159 if (0 == (vf_num = dev_num_vf(eth_dev)))
162 /* enable VMDq and set the default pool for PF */
163 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
165 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
167 << IXGBE_VT_CTL_POOL_SHIFT;
168 vtctl |= IXGBE_VT_CTL_REPLEN;
169 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
171 vfre_offset = vf_num & VFRE_MASK;
172 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
174 /* Enable pools reserved to PF only */
175 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
176 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
177 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
178 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
180 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
181 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
183 /* clear VMDq map to perment rar 0 */
184 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
186 /* clear VMDq map to scan rar 127 */
187 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
188 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
190 /* set VMDq map to default PF pool */
191 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
194 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
196 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
197 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
199 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
200 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
201 gpie |= IXGBE_GPIE_MSIX_MODE;
203 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
205 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
206 gpie |= IXGBE_GPIE_VTMODE_64;
209 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
210 gpie |= IXGBE_GPIE_VTMODE_32;
213 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
214 gpie |= IXGBE_GPIE_VTMODE_16;
218 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
219 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
222 * enable vlan filtering and allow all vlan tags through
224 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
225 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
228 /* VFTA - enable all vlan filters */
229 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
230 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
233 /* Enable MAC Anti-Spoofing */
234 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
236 /* set flow control threshold to max to avoid tx switch hang */
237 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
238 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
239 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
240 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
247 set_rx_mode(struct rte_eth_dev *dev)
249 struct rte_eth_dev_data *dev_data =
250 (struct rte_eth_dev_data*)dev->data->dev_private;
251 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
252 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
253 uint16_t vfn = dev_num_vf(dev);
255 /* Check for Promiscuous and All Multicast modes */
256 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
258 /* set all bits that we expect to always be set */
259 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
260 fctrl |= IXGBE_FCTRL_BAM;
262 /* clear the bits we are changing the status of */
263 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
265 if (dev_data->promiscuous) {
266 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
267 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
269 if (dev_data->all_multicast) {
270 fctrl |= IXGBE_FCTRL_MPE;
271 vmolr |= IXGBE_VMOLR_MPE;
273 vmolr |= IXGBE_VMOLR_ROMPE;
277 if (hw->mac.type != ixgbe_mac_82598EB) {
278 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
279 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
281 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
284 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
286 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
287 ixgbe_vlan_hw_strip_enable_all(dev);
289 ixgbe_vlan_hw_strip_disable_all(dev);
293 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
295 struct ixgbe_hw *hw =
296 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
297 struct ixgbe_vf_info *vfinfo =
298 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
299 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
300 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
302 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
303 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
304 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
306 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
308 /* reset multicast table array for vf */
309 vfinfo[vf].num_vf_mc_hashes = 0;
314 hw->mac.ops.clear_rar(hw, rar_entry);
318 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
320 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
322 uint32_t reg_offset, vf_shift;
323 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
324 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
326 vf_shift = vf & VFRE_MASK;
327 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
329 /* enable transmit and receive for vf */
330 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
331 reg |= (reg | (1 << vf_shift));
332 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
334 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
335 reg |= (reg | (1 << vf_shift));
336 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
338 /* Enable counting of spoofed packets in the SSVPC register */
339 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
340 reg |= (1 << vf_shift);
341 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
343 ixgbe_vf_reset_event(dev, vf);
347 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
349 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
350 struct ixgbe_vf_info *vfinfo =
351 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
352 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
353 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
354 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
356 ixgbe_vf_reset_msg(dev, vf);
358 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
360 /* reply to reset with ack and vf mac address */
361 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
362 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
364 * Piggyback the multicast filter type so VF can compute the
367 msgbuf[3] = hw->mac.mc_filter_type;
368 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
374 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
377 struct ixgbe_vf_info *vfinfo =
378 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
379 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
380 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
382 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
383 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
384 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
390 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
392 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
393 struct ixgbe_vf_info *vfinfo =
394 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
395 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
396 IXGBE_VT_MSGINFO_SHIFT;
397 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
400 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
401 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
402 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
406 /* only so many hash values supported */
407 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
409 /* store the mc entries */
410 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
411 for (i = 0; i < nb_entries; i++) {
412 vfinfo->vf_mc_hashes[i] = hash_list[i];
415 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
416 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
417 & IXGBE_MTA_INDEX_MASK;
418 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
419 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
420 reg_val |= (1 << mta_shift);
421 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
428 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
432 struct ixgbe_vf_info *vfinfo =
433 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
435 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
436 >> IXGBE_VT_MSGINFO_SHIFT;
437 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
440 vfinfo[vf].vlan_count++;
441 else if (vfinfo[vf].vlan_count)
442 vfinfo[vf].vlan_count--;
443 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
447 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
449 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
450 uint32_t new_mtu = msgbuf[1];
452 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
454 /* X540 and X550 support jumbo frames in IOV mode */
455 if (hw->mac.type != ixgbe_mac_X540 &&
456 hw->mac.type != ixgbe_mac_X550 &&
457 hw->mac.type != ixgbe_mac_X550EM_x)
460 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
463 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
464 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
465 if (max_frs < new_mtu) {
466 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
467 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
474 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
476 uint32_t api_version = msgbuf[1];
477 struct ixgbe_vf_info *vfinfo =
478 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
480 switch (api_version) {
481 case ixgbe_mbox_api_10:
482 case ixgbe_mbox_api_11:
483 vfinfo[vf].api_version = (uint8_t)api_version;
489 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
496 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
498 struct ixgbe_vf_info *vfinfo =
499 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
500 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
502 /* Verify if the PF supports the mbox APIs version or not */
503 switch (vfinfo[vf].api_version) {
504 case ixgbe_mbox_api_20:
505 case ixgbe_mbox_api_11:
511 /* Notify VF of Rx and Tx queue number */
512 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
513 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
515 /* Notify VF of default queue */
516 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
519 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
520 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
527 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
529 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
530 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
531 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
534 struct ixgbe_vf_info *vfinfo =
535 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
537 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
539 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
543 /* do nothing with the message already been processed */
544 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
547 /* flush the ack before we write any messages back */
548 IXGBE_WRITE_FLUSH(hw);
550 /* perform VF reset */
551 if (msgbuf[0] == IXGBE_VF_RESET) {
552 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
553 vfinfo[vf].clear_to_send = true;
557 /* check & process VF to PF mailbox message */
558 switch ((msgbuf[0] & 0xFFFF)) {
559 case IXGBE_VF_SET_MAC_ADDR:
560 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
562 case IXGBE_VF_SET_MULTICAST:
563 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
565 case IXGBE_VF_SET_LPE:
566 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
568 case IXGBE_VF_SET_VLAN:
569 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
571 case IXGBE_VF_API_NEGOTIATE:
572 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
574 case IXGBE_VF_GET_QUEUES:
575 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
576 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
579 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
580 retval = IXGBE_ERR_MBX;
584 /* response the VF according to the message process result */
586 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
588 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
590 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
592 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
598 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
600 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
601 struct ixgbe_hw *hw =
602 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
603 struct ixgbe_vf_info *vfinfo =
604 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
606 if (!vfinfo[vf].clear_to_send)
607 ixgbe_write_mbx(hw, &msg, 1, vf);
610 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
613 struct ixgbe_hw *hw =
614 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
616 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
617 /* check & process vf function level reset */
618 if (!ixgbe_check_for_rst(hw, vf))
619 ixgbe_vf_reset_event(eth_dev, vf);
621 /* check & process vf mailbox messages */
622 if (!ixgbe_check_for_msg(hw, vf))
623 ixgbe_rcv_msg_from_vf(eth_dev, vf);
625 /* check & process acks from vf */
626 if (!ixgbe_check_for_ack(hw, vf))
627 ixgbe_rcv_ack_from_vf(eth_dev, vf);