1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*******************************************************************************
4 Intel(R) Gigabit Ethernet Linux driver
5 Copyright(c) 2007-2013 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
16 #include "e1000_osdep.h"
17 #include "e1000_regs.h"
18 #include "e1000_defines.h"
22 #define E1000_DEV_ID_82576 0x10C9
23 #define E1000_DEV_ID_82576_FIBER 0x10E6
24 #define E1000_DEV_ID_82576_SERDES 0x10E7
25 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
26 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
27 #define E1000_DEV_ID_82576_NS 0x150A
28 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
29 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
30 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
31 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
32 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
33 #define E1000_DEV_ID_82580_COPPER 0x150E
34 #define E1000_DEV_ID_82580_FIBER 0x150F
35 #define E1000_DEV_ID_82580_SERDES 0x1510
36 #define E1000_DEV_ID_82580_SGMII 0x1511
37 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
38 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
39 #define E1000_DEV_ID_I350_COPPER 0x1521
40 #define E1000_DEV_ID_I350_FIBER 0x1522
41 #define E1000_DEV_ID_I350_SERDES 0x1523
42 #define E1000_DEV_ID_I350_SGMII 0x1524
43 #define E1000_DEV_ID_I350_DA4 0x1546
44 #define E1000_DEV_ID_I210_COPPER 0x1533
45 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
46 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
47 #define E1000_DEV_ID_I210_FIBER 0x1536
48 #define E1000_DEV_ID_I210_SERDES 0x1537
49 #define E1000_DEV_ID_I210_SGMII 0x1538
50 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
51 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
52 #define E1000_DEV_ID_I211_COPPER 0x1539
53 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
54 #define E1000_DEV_ID_I354_SGMII 0x1F41
55 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
56 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
57 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
58 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
59 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
61 #define E1000_REVISION_0 0
62 #define E1000_REVISION_1 1
63 #define E1000_REVISION_2 2
64 #define E1000_REVISION_3 3
65 #define E1000_REVISION_4 4
67 #define E1000_FUNC_0 0
68 #define E1000_FUNC_1 1
69 #define E1000_FUNC_2 2
70 #define E1000_FUNC_3 3
72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
73 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
86 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
89 enum e1000_media_type {
90 e1000_media_type_unknown = 0,
91 e1000_media_type_copper = 1,
92 e1000_media_type_fiber = 2,
93 e1000_media_type_internal_serdes = 3,
98 e1000_nvm_unknown = 0,
100 e1000_nvm_eeprom_spi,
106 enum e1000_nvm_override {
107 e1000_nvm_override_none = 0,
108 e1000_nvm_override_spi_small,
109 e1000_nvm_override_spi_large,
112 enum e1000_phy_type {
113 e1000_phy_unknown = 0,
126 enum e1000_bus_type {
127 e1000_bus_type_unknown = 0,
130 e1000_bus_type_pci_express,
131 e1000_bus_type_reserved
134 enum e1000_bus_speed {
135 e1000_bus_speed_unknown = 0,
141 e1000_bus_speed_2500,
142 e1000_bus_speed_5000,
143 e1000_bus_speed_reserved
146 enum e1000_bus_width {
147 e1000_bus_width_unknown = 0,
148 e1000_bus_width_pcie_x1,
149 e1000_bus_width_pcie_x2,
150 e1000_bus_width_pcie_x4 = 4,
151 e1000_bus_width_pcie_x8 = 8,
154 e1000_bus_width_reserved
157 enum e1000_1000t_rx_status {
158 e1000_1000t_rx_status_not_ok = 0,
159 e1000_1000t_rx_status_ok,
160 e1000_1000t_rx_status_undefined = 0xFF
163 enum e1000_rev_polarity {
164 e1000_rev_polarity_normal = 0,
165 e1000_rev_polarity_reversed,
166 e1000_rev_polarity_undefined = 0xFF
174 e1000_fc_default = 0xFF
178 e1000_ms_hw_default = 0,
179 e1000_ms_force_master,
180 e1000_ms_force_slave,
184 enum e1000_smart_speed {
185 e1000_smart_speed_default = 0,
186 e1000_smart_speed_on,
187 e1000_smart_speed_off
190 enum e1000_serdes_link_state {
191 e1000_serdes_link_down = 0,
192 e1000_serdes_link_autoneg_progress,
193 e1000_serdes_link_autoneg_complete,
194 e1000_serdes_link_forced_up
206 /* Receive Descriptor */
207 struct e1000_rx_desc {
208 __le64 buffer_addr; /* Address of the descriptor's data buffer */
209 __le16 length; /* Length of data DMAed into data buffer */
210 __le16 csum; /* Packet checksum */
211 u8 status; /* Descriptor status */
212 u8 errors; /* Descriptor Errors */
216 /* Receive Descriptor - Extended */
217 union e1000_rx_desc_extended {
224 __le32 mrq; /* Multiple Rx Queues */
226 __le32 rss; /* RSS Hash */
228 __le16 ip_id; /* IP id */
229 __le16 csum; /* Packet Checksum */
234 __le32 status_error; /* ext status/error */
236 __le16 vlan; /* VLAN tag */
238 } wb; /* writeback */
241 #define MAX_PS_BUFFERS 4
243 /* Number of packet split data buffers (not including the header buffer) */
244 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
246 /* Receive Descriptor - Packet Split */
247 union e1000_rx_desc_packet_split {
249 /* one buffer for protocol header(s), three data buffers */
250 __le64 buffer_addr[MAX_PS_BUFFERS];
254 __le32 mrq; /* Multiple Rx Queues */
256 __le32 rss; /* RSS Hash */
258 __le16 ip_id; /* IP id */
259 __le16 csum; /* Packet Checksum */
264 __le32 status_error; /* ext status/error */
265 __le16 length0; /* length of buffer 0 */
266 __le16 vlan; /* VLAN tag */
269 __le16 header_status;
270 /* length of buffers 1-3 */
271 __le16 length[PS_PAGE_BUFFERS];
274 } wb; /* writeback */
277 /* Transmit Descriptor */
278 struct e1000_tx_desc {
279 __le64 buffer_addr; /* Address of the descriptor's data buffer */
283 __le16 length; /* Data buffer length */
284 u8 cso; /* Checksum offset */
285 u8 cmd; /* Descriptor control */
291 u8 status; /* Descriptor status */
292 u8 css; /* Checksum start */
298 /* Offload Context Descriptor */
299 struct e1000_context_desc {
303 u8 ipcss; /* IP checksum start */
304 u8 ipcso; /* IP checksum offset */
305 __le16 ipcse; /* IP checksum end */
311 u8 tucss; /* TCP checksum start */
312 u8 tucso; /* TCP checksum offset */
313 __le16 tucse; /* TCP checksum end */
316 __le32 cmd_and_length;
320 u8 status; /* Descriptor status */
321 u8 hdr_len; /* Header length */
322 __le16 mss; /* Maximum segment size */
327 /* Offload data descriptor */
328 struct e1000_data_desc {
329 __le64 buffer_addr; /* Address of the descriptor's buffer address */
333 __le16 length; /* Data buffer length */
341 u8 status; /* Descriptor status */
342 u8 popts; /* Packet Options */
348 /* Statistics counters collected by the MAC */
349 struct e1000_hw_stats {
433 struct e1000_phy_stats {
438 struct e1000_host_mng_dhcp_cookie {
449 /* Host Interface "Rev 1" */
450 struct e1000_host_command_header {
457 #define E1000_HI_MAX_DATA_LENGTH 252
458 struct e1000_host_command_info {
459 struct e1000_host_command_header command_header;
460 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
463 /* Host Interface "Rev 2" */
464 struct e1000_host_mng_command_header {
472 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
473 struct e1000_host_mng_command_info {
474 struct e1000_host_mng_command_header command_header;
475 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
478 #include "e1000_mac.h"
479 #include "e1000_phy.h"
480 #include "e1000_nvm.h"
481 #include "e1000_manage.h"
482 #include "e1000_mbx.h"
484 /* Function pointers for the MAC. */
485 struct e1000_mac_operations {
486 s32 (*init_params)(struct e1000_hw *);
487 s32 (*id_led_init)(struct e1000_hw *);
488 s32 (*blink_led)(struct e1000_hw *);
489 bool (*check_mng_mode)(struct e1000_hw *);
490 s32 (*check_for_link)(struct e1000_hw *);
491 s32 (*cleanup_led)(struct e1000_hw *);
492 void (*clear_hw_cntrs)(struct e1000_hw *);
493 void (*clear_vfta)(struct e1000_hw *);
494 s32 (*get_bus_info)(struct e1000_hw *);
495 void (*set_lan_id)(struct e1000_hw *);
496 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
497 s32 (*led_on)(struct e1000_hw *);
498 s32 (*led_off)(struct e1000_hw *);
499 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
500 s32 (*reset_hw)(struct e1000_hw *);
501 s32 (*init_hw)(struct e1000_hw *);
502 void (*shutdown_serdes)(struct e1000_hw *);
503 void (*power_up_serdes)(struct e1000_hw *);
504 s32 (*setup_link)(struct e1000_hw *);
505 s32 (*setup_physical_interface)(struct e1000_hw *);
506 s32 (*setup_led)(struct e1000_hw *);
507 void (*write_vfta)(struct e1000_hw *, u32, u32);
508 void (*config_collision_dist)(struct e1000_hw *);
509 void (*rar_set)(struct e1000_hw *, u8*, u32);
510 s32 (*read_mac_addr)(struct e1000_hw *);
511 s32 (*validate_mdi_setting)(struct e1000_hw *);
512 s32 (*get_thermal_sensor_data)(struct e1000_hw *);
513 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
514 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
515 void (*release_swfw_sync)(struct e1000_hw *, u16);
518 /* When to use various PHY register access functions:
521 * Function Does Does When to use
522 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
523 * X_reg L,P,A n/a for simple PHY reg accesses
524 * X_reg_locked P,A L for multiple accesses of different regs
526 * X_reg_page A L,P for multiple accesses of different regs
529 * Where X=[read|write], L=locking, P=sets page, A=register access
532 struct e1000_phy_operations {
533 s32 (*init_params)(struct e1000_hw *);
534 s32 (*acquire)(struct e1000_hw *);
535 s32 (*check_polarity)(struct e1000_hw *);
536 s32 (*check_reset_block)(struct e1000_hw *);
537 s32 (*commit)(struct e1000_hw *);
538 s32 (*force_speed_duplex)(struct e1000_hw *);
539 s32 (*get_cfg_done)(struct e1000_hw *hw);
540 s32 (*get_cable_length)(struct e1000_hw *);
541 s32 (*get_info)(struct e1000_hw *);
542 s32 (*set_page)(struct e1000_hw *, u16);
543 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
544 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
545 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
546 void (*release)(struct e1000_hw *);
547 s32 (*reset)(struct e1000_hw *);
548 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
549 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
550 s32 (*write_reg)(struct e1000_hw *, u32, u16);
551 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
552 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
553 void (*power_up)(struct e1000_hw *);
554 void (*power_down)(struct e1000_hw *);
555 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
556 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
559 /* Function pointers for the NVM. */
560 struct e1000_nvm_operations {
561 s32 (*init_params)(struct e1000_hw *);
562 s32 (*acquire)(struct e1000_hw *);
563 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
564 void (*release)(struct e1000_hw *);
565 void (*reload)(struct e1000_hw *);
566 s32 (*update)(struct e1000_hw *);
567 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
568 s32 (*validate)(struct e1000_hw *);
569 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
572 #define E1000_MAX_SENSORS 3
574 struct e1000_thermal_diode_data {
581 struct e1000_thermal_sensor_data {
582 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
585 struct e1000_mac_info {
586 struct e1000_mac_operations ops;
587 u8 addr[ETH_ADDR_LEN];
588 u8 perm_addr[ETH_ADDR_LEN];
590 enum e1000_mac_type type;
608 /* Maximum size of the MTA register table in all supported adapters */
609 #define MAX_MTA_REG 128
610 u32 mta_shadow[MAX_MTA_REG];
613 u8 forced_speed_duplex;
617 bool arc_subsystem_valid;
618 bool asf_firmware_present;
621 bool get_link_status;
623 enum e1000_serdes_link_state serdes_link_state;
624 bool serdes_has_link;
625 bool tx_pkt_filtering;
626 struct e1000_thermal_sensor_data thermal_sensor_data;
629 struct e1000_phy_info {
630 struct e1000_phy_operations ops;
631 enum e1000_phy_type type;
633 enum e1000_1000t_rx_status local_rx;
634 enum e1000_1000t_rx_status remote_rx;
635 enum e1000_ms_type ms_type;
636 enum e1000_ms_type original_ms_type;
637 enum e1000_rev_polarity cable_polarity;
638 enum e1000_smart_speed smart_speed;
642 u32 reset_delay_us; /* in usec */
645 enum e1000_media_type media_type;
647 u16 autoneg_advertised;
650 u16 max_cable_length;
651 u16 min_cable_length;
655 bool disable_polarity_correction;
657 bool polarity_correction;
659 bool speed_downgraded;
660 bool autoneg_wait_to_complete;
663 struct e1000_nvm_info {
664 struct e1000_nvm_operations ops;
665 enum e1000_nvm_type type;
666 enum e1000_nvm_override override;
678 struct e1000_bus_info {
679 enum e1000_bus_type type;
680 enum e1000_bus_speed speed;
681 enum e1000_bus_width width;
687 struct e1000_fc_info {
688 u32 high_water; /* Flow control high-water mark */
689 u32 low_water; /* Flow control low-water mark */
690 u16 pause_time; /* Flow control pause timer */
691 u16 refresh_time; /* Flow control refresh timer */
692 bool send_xon; /* Flow control send XON */
693 bool strict_ieee; /* Strict IEEE mode */
694 enum e1000_fc_mode current_mode; /* FC mode in effect */
695 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
698 struct e1000_mbx_operations {
699 s32 (*init_params)(struct e1000_hw *hw);
700 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
701 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
702 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
703 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
704 s32 (*check_for_msg)(struct e1000_hw *, u16);
705 s32 (*check_for_ack)(struct e1000_hw *, u16);
706 s32 (*check_for_rst)(struct e1000_hw *, u16);
709 struct e1000_mbx_stats {
718 struct e1000_mbx_info {
719 struct e1000_mbx_operations ops;
720 struct e1000_mbx_stats stats;
726 struct e1000_dev_spec_82575 {
728 bool global_device_reset;
731 bool clear_semaphore_once;
733 struct sfp_e1000_flags eth_flags;
738 struct e1000_dev_spec_vf {
747 u8 __iomem *flash_address;
748 unsigned long io_base;
750 struct e1000_mac_info mac;
751 struct e1000_fc_info fc;
752 struct e1000_phy_info phy;
753 struct e1000_nvm_info nvm;
754 struct e1000_bus_info bus;
755 struct e1000_mbx_info mbx;
756 struct e1000_host_mng_dhcp_cookie mng_cookie;
759 struct e1000_dev_spec_82575 _82575;
760 struct e1000_dev_spec_vf vf;
764 u16 subsystem_vendor_id;
765 u16 subsystem_device_id;
771 #include "e1000_82575.h"
772 #include "e1000_i210.h"
774 /* These functions must be implemented by drivers */
775 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
776 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);