1 // SPDX-License-Identifier: GPL-2.0
2 /*******************************************************************************
4 Intel 10 Gigabit PCI Express Linux driver
5 Copyright(c) 1999 - 2012 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
13 #include "ixgbe_common.h"
14 #include "ixgbe_phy.h"
15 #include "ixgbe_api.h"
17 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
18 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
19 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
20 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
21 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
22 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
24 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
25 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
26 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
27 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
29 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
30 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
32 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
33 u16 words, u16 *data);
34 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
35 u16 words, u16 *data);
36 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
40 * ixgbe_init_ops_generic - Inits function ptrs
41 * @hw: pointer to the hardware structure
43 * Initialize the function pointers.
45 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
47 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
48 struct ixgbe_mac_info *mac = &hw->mac;
49 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
52 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
53 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
54 if (eec & IXGBE_EEC_PRES) {
55 eeprom->ops.read = &ixgbe_read_eerd_generic;
56 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
58 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
59 eeprom->ops.read_buffer =
60 &ixgbe_read_eeprom_buffer_bit_bang_generic;
62 eeprom->ops.write = &ixgbe_write_eeprom_generic;
63 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
64 eeprom->ops.validate_checksum =
65 &ixgbe_validate_eeprom_checksum_generic;
66 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
67 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
70 mac->ops.init_hw = &ixgbe_init_hw_generic;
71 mac->ops.reset_hw = NULL;
72 mac->ops.start_hw = &ixgbe_start_hw_generic;
73 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
74 mac->ops.get_media_type = NULL;
75 mac->ops.get_supported_physical_layer = NULL;
76 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
77 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
78 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
79 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
80 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
81 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
82 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
85 mac->ops.led_on = &ixgbe_led_on_generic;
86 mac->ops.led_off = &ixgbe_led_off_generic;
87 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
88 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
90 /* RAR, Multicast, VLAN */
91 mac->ops.set_rar = &ixgbe_set_rar_generic;
92 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
93 mac->ops.insert_mac_addr = NULL;
94 mac->ops.set_vmdq = NULL;
95 mac->ops.clear_vmdq = NULL;
96 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
97 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
98 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
99 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
100 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
101 mac->ops.clear_vfta = NULL;
102 mac->ops.set_vfta = NULL;
103 mac->ops.set_vlvf = NULL;
104 mac->ops.init_uta_tables = NULL;
107 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
110 mac->ops.get_link_capabilities = NULL;
111 mac->ops.setup_link = NULL;
112 mac->ops.check_link = NULL;
118 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
120 * @hw: pointer to hardware structure
122 * There are several phys that do not support autoneg flow control. This
123 * function check the device id to see if the associated phy supports
124 * autoneg flow control.
126 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
129 switch (hw->device_id) {
130 case IXGBE_DEV_ID_X540T:
132 case IXGBE_DEV_ID_82599_T3_LOM:
135 return IXGBE_ERR_FC_NOT_SUPPORTED;
140 * ixgbe_setup_fc - Set up flow control
141 * @hw: pointer to hardware structure
143 * Called at init time to set up flow control.
145 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
148 u32 reg = 0, reg_bp = 0;
152 * Validate the requested mode. Strict IEEE mode does not allow
153 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
155 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
156 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
157 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
162 * 10gig parts do not have a word in the EEPROM to determine the
163 * default flow control setting, so we explicitly set it to full.
165 if (hw->fc.requested_mode == ixgbe_fc_default)
166 hw->fc.requested_mode = ixgbe_fc_full;
169 * Set up the 1G and 10G flow control advertisement registers so the
170 * HW will be able to do fc autoneg once the cable is plugged in. If
171 * we link at 10G, the 1G advertisement is harmless and vice versa.
173 switch (hw->phy.media_type) {
174 case ixgbe_media_type_fiber:
175 case ixgbe_media_type_backplane:
176 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
177 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
179 case ixgbe_media_type_copper:
180 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
181 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
188 * The possible values of fc.requested_mode are:
189 * 0: Flow control is completely disabled
190 * 1: Rx flow control is enabled (we can receive pause frames,
191 * but not send pause frames).
192 * 2: Tx flow control is enabled (we can send pause frames but
193 * we do not support receiving pause frames).
194 * 3: Both Rx and Tx flow control (symmetric) are enabled.
197 switch (hw->fc.requested_mode) {
199 /* Flow control completely disabled by software override. */
200 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
201 if (hw->phy.media_type == ixgbe_media_type_backplane)
202 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
203 IXGBE_AUTOC_ASM_PAUSE);
204 else if (hw->phy.media_type == ixgbe_media_type_copper)
205 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
207 case ixgbe_fc_tx_pause:
209 * Tx Flow control is enabled, and Rx Flow control is
210 * disabled by software override.
212 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
213 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
214 if (hw->phy.media_type == ixgbe_media_type_backplane) {
215 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
216 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
217 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
218 reg_cu |= IXGBE_TAF_ASM_PAUSE;
219 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
222 case ixgbe_fc_rx_pause:
224 * Rx Flow control is enabled and Tx Flow control is
225 * disabled by software override. Since there really
226 * isn't a way to advertise that we are capable of RX
227 * Pause ONLY, we will advertise that we support both
228 * symmetric and asymmetric Rx PAUSE, as such we fall
229 * through to the fc_full statement. Later, we will
230 * disable the adapter's ability to send PAUSE frames.
233 /* Flow control (both Rx and Tx) is enabled by SW override. */
234 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
235 if (hw->phy.media_type == ixgbe_media_type_backplane)
236 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
237 IXGBE_AUTOC_ASM_PAUSE;
238 else if (hw->phy.media_type == ixgbe_media_type_copper)
239 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
242 hw_dbg(hw, "Flow control param set incorrectly\n");
243 ret_val = IXGBE_ERR_CONFIG;
248 if (hw->mac.type != ixgbe_mac_X540) {
250 * Enable auto-negotiation between the MAC & PHY;
251 * the MAC will advertise clause 37 flow control.
253 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
254 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
256 /* Disable AN timeout */
257 if (hw->fc.strict_ieee)
258 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
260 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
261 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
265 * AUTOC restart handles negotiation of 1G and 10G on backplane
266 * and copper. There is no need to set the PCS1GCTL register.
269 if (hw->phy.media_type == ixgbe_media_type_backplane) {
270 reg_bp |= IXGBE_AUTOC_AN_RESTART;
271 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
272 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
273 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
274 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
275 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
278 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
284 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
285 * @hw: pointer to hardware structure
287 * Starts the hardware by filling the bus info structure and media type, clears
288 * all on chip counters, initializes receive address registers, multicast
289 * table, VLAN filter table, calls routine to set up link and flow control
290 * settings, and leaves transmit and receive units disabled and uninitialized
292 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
297 /* Set the media type */
298 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
300 /* PHY ops initialization must be done in reset_hw() */
302 /* Clear the VLAN filter table */
303 hw->mac.ops.clear_vfta(hw);
305 /* Clear statistics registers */
306 hw->mac.ops.clear_hw_cntrs(hw);
308 /* Set No Snoop Disable */
309 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
310 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
311 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
312 IXGBE_WRITE_FLUSH(hw);
314 /* Setup flow control */
315 ret_val = ixgbe_setup_fc(hw);
319 /* Clear adapter stopped flag */
320 hw->adapter_stopped = false;
327 * ixgbe_start_hw_gen2 - Init sequence for common device family
328 * @hw: pointer to hw structure
330 * Performs the init sequence common to the second generation
332 * Devices in the second generation:
336 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
341 /* Clear the rate limiters */
342 for (i = 0; i < hw->mac.max_tx_queues; i++) {
343 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
344 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
346 IXGBE_WRITE_FLUSH(hw);
348 /* Disable relaxed ordering */
349 for (i = 0; i < hw->mac.max_tx_queues; i++) {
350 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
351 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
352 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
355 for (i = 0; i < hw->mac.max_rx_queues; i++) {
356 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
357 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
358 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
359 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
366 * ixgbe_init_hw_generic - Generic hardware initialization
367 * @hw: pointer to hardware structure
369 * Initialize the hardware by resetting the hardware, filling the bus info
370 * structure and media type, clears all on chip counters, initializes receive
371 * address registers, multicast table, VLAN filter table, calls routine to set
372 * up link and flow control settings, and leaves transmit and receive units
373 * disabled and uninitialized
375 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
379 /* Reset the hardware */
380 status = hw->mac.ops.reset_hw(hw);
384 status = hw->mac.ops.start_hw(hw);
391 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
392 * @hw: pointer to hardware structure
394 * Clears all hardware statistics counters by reading them from the hardware
395 * Statistics counters are clear on read.
397 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
401 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
402 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
403 IXGBE_READ_REG(hw, IXGBE_ERRBC);
404 IXGBE_READ_REG(hw, IXGBE_MSPDC);
405 for (i = 0; i < 8; i++)
406 IXGBE_READ_REG(hw, IXGBE_MPC(i));
408 IXGBE_READ_REG(hw, IXGBE_MLFC);
409 IXGBE_READ_REG(hw, IXGBE_MRFC);
410 IXGBE_READ_REG(hw, IXGBE_RLEC);
411 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
412 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
413 if (hw->mac.type >= ixgbe_mac_82599EB) {
414 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
415 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
417 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
418 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
421 for (i = 0; i < 8; i++) {
422 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
423 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
424 if (hw->mac.type >= ixgbe_mac_82599EB) {
425 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
426 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
428 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
429 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
432 if (hw->mac.type >= ixgbe_mac_82599EB)
433 for (i = 0; i < 8; i++)
434 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
435 IXGBE_READ_REG(hw, IXGBE_PRC64);
436 IXGBE_READ_REG(hw, IXGBE_PRC127);
437 IXGBE_READ_REG(hw, IXGBE_PRC255);
438 IXGBE_READ_REG(hw, IXGBE_PRC511);
439 IXGBE_READ_REG(hw, IXGBE_PRC1023);
440 IXGBE_READ_REG(hw, IXGBE_PRC1522);
441 IXGBE_READ_REG(hw, IXGBE_GPRC);
442 IXGBE_READ_REG(hw, IXGBE_BPRC);
443 IXGBE_READ_REG(hw, IXGBE_MPRC);
444 IXGBE_READ_REG(hw, IXGBE_GPTC);
445 IXGBE_READ_REG(hw, IXGBE_GORCL);
446 IXGBE_READ_REG(hw, IXGBE_GORCH);
447 IXGBE_READ_REG(hw, IXGBE_GOTCL);
448 IXGBE_READ_REG(hw, IXGBE_GOTCH);
449 if (hw->mac.type == ixgbe_mac_82598EB)
450 for (i = 0; i < 8; i++)
451 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
452 IXGBE_READ_REG(hw, IXGBE_RUC);
453 IXGBE_READ_REG(hw, IXGBE_RFC);
454 IXGBE_READ_REG(hw, IXGBE_ROC);
455 IXGBE_READ_REG(hw, IXGBE_RJC);
456 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
457 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
458 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
459 IXGBE_READ_REG(hw, IXGBE_TORL);
460 IXGBE_READ_REG(hw, IXGBE_TORH);
461 IXGBE_READ_REG(hw, IXGBE_TPR);
462 IXGBE_READ_REG(hw, IXGBE_TPT);
463 IXGBE_READ_REG(hw, IXGBE_PTC64);
464 IXGBE_READ_REG(hw, IXGBE_PTC127);
465 IXGBE_READ_REG(hw, IXGBE_PTC255);
466 IXGBE_READ_REG(hw, IXGBE_PTC511);
467 IXGBE_READ_REG(hw, IXGBE_PTC1023);
468 IXGBE_READ_REG(hw, IXGBE_PTC1522);
469 IXGBE_READ_REG(hw, IXGBE_MPTC);
470 IXGBE_READ_REG(hw, IXGBE_BPTC);
471 for (i = 0; i < 16; i++) {
472 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
473 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
474 if (hw->mac.type >= ixgbe_mac_82599EB) {
475 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
476 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
477 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
478 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
479 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
481 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
482 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
486 if (hw->mac.type == ixgbe_mac_X540) {
488 ixgbe_identify_phy(hw);
489 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
490 IXGBE_MDIO_PCS_DEV_TYPE, &i);
491 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
492 IXGBE_MDIO_PCS_DEV_TYPE, &i);
493 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
494 IXGBE_MDIO_PCS_DEV_TYPE, &i);
495 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
496 IXGBE_MDIO_PCS_DEV_TYPE, &i);
503 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
504 * @hw: pointer to hardware structure
505 * @pba_num: stores the part number string from the EEPROM
506 * @pba_num_size: part number string buffer length
508 * Reads the part number string from the EEPROM.
510 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
519 if (pba_num == NULL) {
520 hw_dbg(hw, "PBA string buffer was null\n");
521 return IXGBE_ERR_INVALID_ARGUMENT;
524 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
526 hw_dbg(hw, "NVM Read Error\n");
530 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
532 hw_dbg(hw, "NVM Read Error\n");
537 * if data is not ptr guard the PBA must be in legacy format which
538 * means pba_ptr is actually our second data word for the PBA number
539 * and we can decode it into an ascii string
541 if (data != IXGBE_PBANUM_PTR_GUARD) {
542 hw_dbg(hw, "NVM PBA number is not stored as string\n");
544 /* we will need 11 characters to store the PBA */
545 if (pba_num_size < 11) {
546 hw_dbg(hw, "PBA string buffer too small\n");
547 return IXGBE_ERR_NO_SPACE;
550 /* extract hex string from data and pba_ptr */
551 pba_num[0] = (data >> 12) & 0xF;
552 pba_num[1] = (data >> 8) & 0xF;
553 pba_num[2] = (data >> 4) & 0xF;
554 pba_num[3] = data & 0xF;
555 pba_num[4] = (pba_ptr >> 12) & 0xF;
556 pba_num[5] = (pba_ptr >> 8) & 0xF;
559 pba_num[8] = (pba_ptr >> 4) & 0xF;
560 pba_num[9] = pba_ptr & 0xF;
562 /* put a null character on the end of our string */
565 /* switch all the data but the '-' to hex char */
566 for (offset = 0; offset < 10; offset++) {
567 if (pba_num[offset] < 0xA)
568 pba_num[offset] += '0';
569 else if (pba_num[offset] < 0x10)
570 pba_num[offset] += 'A' - 0xA;
576 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
578 hw_dbg(hw, "NVM Read Error\n");
582 if (length == 0xFFFF || length == 0) {
583 hw_dbg(hw, "NVM PBA number section invalid length\n");
584 return IXGBE_ERR_PBA_SECTION;
587 /* check if pba_num buffer is big enough */
588 if (pba_num_size < (((u32)length * 2) - 1)) {
589 hw_dbg(hw, "PBA string buffer too small\n");
590 return IXGBE_ERR_NO_SPACE;
593 /* trim pba length from start of string */
597 for (offset = 0; offset < length; offset++) {
598 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
600 hw_dbg(hw, "NVM Read Error\n");
603 pba_num[offset * 2] = (u8)(data >> 8);
604 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
606 pba_num[offset * 2] = '\0';
612 * ixgbe_get_mac_addr_generic - Generic get MAC address
613 * @hw: pointer to hardware structure
614 * @mac_addr: Adapter MAC address
616 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
617 * A reset of the adapter must be performed prior to calling this function
618 * in order for the MAC address to have been loaded from the EEPROM into RAR0
620 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
626 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
627 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
629 for (i = 0; i < 4; i++)
630 mac_addr[i] = (u8)(rar_low >> (i*8));
632 for (i = 0; i < 2; i++)
633 mac_addr[i+4] = (u8)(rar_high >> (i*8));
639 * ixgbe_get_bus_info_generic - Generic set PCI bus info
640 * @hw: pointer to hardware structure
642 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
644 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
646 struct ixgbe_mac_info *mac = &hw->mac;
649 hw->bus.type = ixgbe_bus_type_pci_express;
651 /* Get the negotiated link width and speed from PCI config space */
652 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
654 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
655 case IXGBE_PCI_LINK_WIDTH_1:
656 hw->bus.width = ixgbe_bus_width_pcie_x1;
658 case IXGBE_PCI_LINK_WIDTH_2:
659 hw->bus.width = ixgbe_bus_width_pcie_x2;
661 case IXGBE_PCI_LINK_WIDTH_4:
662 hw->bus.width = ixgbe_bus_width_pcie_x4;
664 case IXGBE_PCI_LINK_WIDTH_8:
665 hw->bus.width = ixgbe_bus_width_pcie_x8;
668 hw->bus.width = ixgbe_bus_width_unknown;
672 switch (link_status & IXGBE_PCI_LINK_SPEED) {
673 case IXGBE_PCI_LINK_SPEED_2500:
674 hw->bus.speed = ixgbe_bus_speed_2500;
676 case IXGBE_PCI_LINK_SPEED_5000:
677 hw->bus.speed = ixgbe_bus_speed_5000;
679 case IXGBE_PCI_LINK_SPEED_8000:
680 hw->bus.speed = ixgbe_bus_speed_8000;
683 hw->bus.speed = ixgbe_bus_speed_unknown;
687 mac->ops.set_lan_id(hw);
693 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
694 * @hw: pointer to the HW structure
696 * Determines the LAN function id by reading memory-mapped registers
697 * and swaps the port value if requested.
699 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
701 struct ixgbe_bus_info *bus = &hw->bus;
704 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
705 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
706 bus->lan_id = bus->func;
708 /* check for a port swap */
709 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
710 if (reg & IXGBE_FACTPS_LFS)
715 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
716 * @hw: pointer to hardware structure
718 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
719 * disables transmit and receive units. The adapter_stopped flag is used by
720 * the shared code and drivers to determine if the adapter is in a stopped
721 * state and should not touch the hardware.
723 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
729 * Set the adapter_stopped flag so other driver functions stop touching
732 hw->adapter_stopped = true;
734 /* Disable the receive unit */
735 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
737 /* Clear interrupt mask to stop interrupts from being generated */
738 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
740 /* Clear any pending interrupts, flush previous writes */
741 IXGBE_READ_REG(hw, IXGBE_EICR);
743 /* Disable the transmit unit. Each queue must be disabled. */
744 for (i = 0; i < hw->mac.max_tx_queues; i++)
745 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
747 /* Disable the receive unit by stopping each queue */
748 for (i = 0; i < hw->mac.max_rx_queues; i++) {
749 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
750 reg_val &= ~IXGBE_RXDCTL_ENABLE;
751 reg_val |= IXGBE_RXDCTL_SWFLSH;
752 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
755 /* flush all queues disables */
756 IXGBE_WRITE_FLUSH(hw);
760 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
761 * access and verify no pending requests
763 return ixgbe_disable_pcie_master(hw);
767 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
768 * @hw: pointer to hardware structure
769 * @index: led number to turn on
771 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
773 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
775 /* To turn on the LED, set mode to ON. */
776 led_reg &= ~IXGBE_LED_MODE_MASK(index);
777 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
778 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
779 IXGBE_WRITE_FLUSH(hw);
785 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
786 * @hw: pointer to hardware structure
787 * @index: led number to turn off
789 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
791 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
793 /* To turn off the LED, set mode to OFF. */
794 led_reg &= ~IXGBE_LED_MODE_MASK(index);
795 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
796 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
797 IXGBE_WRITE_FLUSH(hw);
803 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
804 * @hw: pointer to hardware structure
806 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
807 * ixgbe_hw struct in order to set up EEPROM access.
809 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
811 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
815 if (eeprom->type == ixgbe_eeprom_uninitialized) {
816 eeprom->type = ixgbe_eeprom_none;
817 /* Set default semaphore delay to 10ms which is a well
819 eeprom->semaphore_delay = 10;
820 /* Clear EEPROM page size, it will be initialized as needed */
821 eeprom->word_page_size = 0;
824 * Check for EEPROM present first.
825 * If not present leave as none
827 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
828 if (eec & IXGBE_EEC_PRES) {
829 eeprom->type = ixgbe_eeprom_spi;
832 * SPI EEPROM is assumed here. This code would need to
833 * change if a future EEPROM is not SPI.
835 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
836 IXGBE_EEC_SIZE_SHIFT);
837 eeprom->word_size = 1 << (eeprom_size +
838 IXGBE_EEPROM_WORD_SIZE_SHIFT);
841 if (eec & IXGBE_EEC_ADDR_SIZE)
842 eeprom->address_bits = 16;
844 eeprom->address_bits = 8;
845 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
846 "%d\n", eeprom->type, eeprom->word_size,
847 eeprom->address_bits);
854 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
855 * @hw: pointer to hardware structure
856 * @offset: offset within the EEPROM to write
857 * @words: number of word(s)
858 * @data: 16 bit word(s) to write to EEPROM
860 * Reads 16 bit word(s) from EEPROM through bit-bang method
862 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
863 u16 words, u16 *data)
868 hw->eeprom.ops.init_params(hw);
871 status = IXGBE_ERR_INVALID_ARGUMENT;
875 if (offset + words > hw->eeprom.word_size) {
876 status = IXGBE_ERR_EEPROM;
881 * The EEPROM page size cannot be queried from the chip. We do lazy
882 * initialization. It is worth to do that when we write large buffer.
884 if ((hw->eeprom.word_page_size == 0) &&
885 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
886 ixgbe_detect_eeprom_page_size_generic(hw, offset);
889 * We cannot hold synchronization semaphores for too long
890 * to avoid other entity starvation. However it is more efficient
891 * to read in bursts than synchronizing access for each word.
893 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
894 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
895 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
896 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
908 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
909 * @hw: pointer to hardware structure
910 * @offset: offset within the EEPROM to be written to
911 * @words: number of word(s)
912 * @data: 16 bit word(s) to be written to the EEPROM
914 * If ixgbe_eeprom_update_checksum is not called after this function, the
915 * EEPROM will most likely contain an invalid checksum.
917 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
918 u16 words, u16 *data)
924 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
926 /* Prepare the EEPROM for writing */
927 status = ixgbe_acquire_eeprom(hw);
930 if (ixgbe_ready_eeprom(hw) != 0) {
931 ixgbe_release_eeprom(hw);
932 status = IXGBE_ERR_EEPROM;
937 for (i = 0; i < words; i++) {
938 ixgbe_standby_eeprom(hw);
940 /* Send the WRITE ENABLE command (8 bit opcode ) */
941 ixgbe_shift_out_eeprom_bits(hw,
942 IXGBE_EEPROM_WREN_OPCODE_SPI,
943 IXGBE_EEPROM_OPCODE_BITS);
945 ixgbe_standby_eeprom(hw);
948 * Some SPI eeproms use the 8th address bit embedded
951 if ((hw->eeprom.address_bits == 8) &&
952 ((offset + i) >= 128))
953 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
955 /* Send the Write command (8-bit opcode + addr) */
956 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
957 IXGBE_EEPROM_OPCODE_BITS);
958 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
959 hw->eeprom.address_bits);
961 page_size = hw->eeprom.word_page_size;
963 /* Send the data in burst via SPI*/
966 word = (word >> 8) | (word << 8);
967 ixgbe_shift_out_eeprom_bits(hw, word, 16);
972 /* do not wrap around page */
973 if (((offset + i) & (page_size - 1)) ==
976 } while (++i < words);
978 ixgbe_standby_eeprom(hw);
981 /* Done with writing - release the EEPROM */
982 ixgbe_release_eeprom(hw);
989 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
990 * @hw: pointer to hardware structure
991 * @offset: offset within the EEPROM to be written to
992 * @data: 16 bit word to be written to the EEPROM
994 * If ixgbe_eeprom_update_checksum is not called after this function, the
995 * EEPROM will most likely contain an invalid checksum.
997 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1001 hw->eeprom.ops.init_params(hw);
1003 if (offset >= hw->eeprom.word_size) {
1004 status = IXGBE_ERR_EEPROM;
1008 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1015 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1016 * @hw: pointer to hardware structure
1017 * @offset: offset within the EEPROM to be read
1018 * @data: read 16 bit words(s) from EEPROM
1019 * @words: number of word(s)
1021 * Reads 16 bit word(s) from EEPROM through bit-bang method
1023 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1024 u16 words, u16 *data)
1029 hw->eeprom.ops.init_params(hw);
1032 status = IXGBE_ERR_INVALID_ARGUMENT;
1036 if (offset + words > hw->eeprom.word_size) {
1037 status = IXGBE_ERR_EEPROM;
1042 * We cannot hold synchronization semaphores for too long
1043 * to avoid other entity starvation. However it is more efficient
1044 * to read in bursts than synchronizing access for each word.
1046 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1047 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1048 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1050 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1062 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1063 * @hw: pointer to hardware structure
1064 * @offset: offset within the EEPROM to be read
1065 * @words: number of word(s)
1066 * @data: read 16 bit word(s) from EEPROM
1068 * Reads 16 bit word(s) from EEPROM through bit-bang method
1070 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1071 u16 words, u16 *data)
1075 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1078 /* Prepare the EEPROM for reading */
1079 status = ixgbe_acquire_eeprom(hw);
1082 if (ixgbe_ready_eeprom(hw) != 0) {
1083 ixgbe_release_eeprom(hw);
1084 status = IXGBE_ERR_EEPROM;
1089 for (i = 0; i < words; i++) {
1090 ixgbe_standby_eeprom(hw);
1092 * Some SPI eeproms use the 8th address bit embedded
1095 if ((hw->eeprom.address_bits == 8) &&
1096 ((offset + i) >= 128))
1097 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1099 /* Send the READ command (opcode + addr) */
1100 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1101 IXGBE_EEPROM_OPCODE_BITS);
1102 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1103 hw->eeprom.address_bits);
1105 /* Read the data. */
1106 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1107 data[i] = (word_in >> 8) | (word_in << 8);
1110 /* End this read operation */
1111 ixgbe_release_eeprom(hw);
1118 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1119 * @hw: pointer to hardware structure
1120 * @offset: offset within the EEPROM to be read
1121 * @data: read 16 bit value from EEPROM
1123 * Reads 16 bit value from EEPROM through bit-bang method
1125 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1130 hw->eeprom.ops.init_params(hw);
1132 if (offset >= hw->eeprom.word_size) {
1133 status = IXGBE_ERR_EEPROM;
1137 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1144 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1145 * @hw: pointer to hardware structure
1146 * @offset: offset of word in the EEPROM to read
1147 * @words: number of word(s)
1148 * @data: 16 bit word(s) from the EEPROM
1150 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1152 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1153 u16 words, u16 *data)
1159 hw->eeprom.ops.init_params(hw);
1162 status = IXGBE_ERR_INVALID_ARGUMENT;
1166 if (offset >= hw->eeprom.word_size) {
1167 status = IXGBE_ERR_EEPROM;
1171 for (i = 0; i < words; i++) {
1172 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1173 IXGBE_EEPROM_RW_REG_START;
1175 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1176 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1179 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1180 IXGBE_EEPROM_RW_REG_DATA);
1182 hw_dbg(hw, "Eeprom read timed out\n");
1191 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1192 * @hw: pointer to hardware structure
1193 * @offset: offset within the EEPROM to be used as a scratch pad
1195 * Discover EEPROM page size by writing marching data at given offset.
1196 * This function is called only when we are writing a new large buffer
1197 * at given offset so the data would be overwritten anyway.
1199 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1202 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1206 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1209 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1210 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1211 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1212 hw->eeprom.word_page_size = 0;
1216 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1221 * When writing in burst more than the actual page size
1222 * EEPROM address wraps around current page.
1224 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1226 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1227 hw->eeprom.word_page_size);
1233 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1234 * @hw: pointer to hardware structure
1235 * @offset: offset of word in the EEPROM to read
1236 * @data: word read from the EEPROM
1238 * Reads a 16 bit word from the EEPROM using the EERD register.
1240 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1242 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1246 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1247 * @hw: pointer to hardware structure
1248 * @offset: offset of word in the EEPROM to write
1249 * @words: number of word(s)
1250 * @data: word(s) write to the EEPROM
1252 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1254 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1255 u16 words, u16 *data)
1261 hw->eeprom.ops.init_params(hw);
1264 status = IXGBE_ERR_INVALID_ARGUMENT;
1268 if (offset >= hw->eeprom.word_size) {
1269 status = IXGBE_ERR_EEPROM;
1273 for (i = 0; i < words; i++) {
1274 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1275 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1276 IXGBE_EEPROM_RW_REG_START;
1278 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1280 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1284 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1286 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1288 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1298 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1299 * @hw: pointer to hardware structure
1300 * @offset: offset of word in the EEPROM to write
1301 * @data: word write to the EEPROM
1303 * Write a 16 bit word to the EEPROM using the EEWR register.
1305 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1307 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1311 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1312 * @hw: pointer to hardware structure
1313 * @ee_reg: EEPROM flag for polling
1315 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1316 * read or write is done respectively.
1318 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1322 s32 status = IXGBE_ERR_EEPROM;
1324 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1325 if (ee_reg == IXGBE_NVM_POLL_READ)
1326 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1328 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1330 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1340 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1341 * @hw: pointer to hardware structure
1343 * Prepares EEPROM for access using bit-bang method. This function should
1344 * be called before issuing a command to the EEPROM.
1346 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1352 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1354 status = IXGBE_ERR_SWFW_SYNC;
1357 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1359 /* Request EEPROM Access */
1360 eec |= IXGBE_EEC_REQ;
1361 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1363 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1364 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1365 if (eec & IXGBE_EEC_GNT)
1370 /* Release if grant not acquired */
1371 if (!(eec & IXGBE_EEC_GNT)) {
1372 eec &= ~IXGBE_EEC_REQ;
1373 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1374 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1376 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1377 status = IXGBE_ERR_EEPROM;
1380 /* Setup EEPROM for Read/Write */
1382 /* Clear CS and SK */
1383 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1384 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1385 IXGBE_WRITE_FLUSH(hw);
1393 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1394 * @hw: pointer to hardware structure
1396 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1398 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1400 s32 status = IXGBE_ERR_EEPROM;
1405 /* Get SMBI software semaphore between device drivers first */
1406 for (i = 0; i < timeout; i++) {
1408 * If the SMBI bit is 0 when we read it, then the bit will be
1409 * set and we have the semaphore
1411 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1412 if (!(swsm & IXGBE_SWSM_SMBI)) {
1420 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1423 * this release is particularly important because our attempts
1424 * above to get the semaphore may have succeeded, and if there
1425 * was a timeout, we should unconditionally clear the semaphore
1426 * bits to free the driver to make progress
1428 ixgbe_release_eeprom_semaphore(hw);
1433 * If the SMBI bit is 0 when we read it, then the bit will be
1434 * set and we have the semaphore
1436 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1437 if (!(swsm & IXGBE_SWSM_SMBI))
1441 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1443 for (i = 0; i < timeout; i++) {
1444 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1446 /* Set the SW EEPROM semaphore bit to request access */
1447 swsm |= IXGBE_SWSM_SWESMBI;
1448 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1451 * If we set the bit successfully then we got the
1454 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1455 if (swsm & IXGBE_SWSM_SWESMBI)
1462 * Release semaphores and return error if SW EEPROM semaphore
1463 * was not granted because we don't have access to the EEPROM
1466 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1468 ixgbe_release_eeprom_semaphore(hw);
1469 status = IXGBE_ERR_EEPROM;
1472 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1480 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1481 * @hw: pointer to hardware structure
1483 * This function clears hardware semaphore bits.
1485 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1489 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1491 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1492 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1493 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1494 IXGBE_WRITE_FLUSH(hw);
1498 * ixgbe_ready_eeprom - Polls for EEPROM ready
1499 * @hw: pointer to hardware structure
1501 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1508 * Read "Status Register" repeatedly until the LSB is cleared. The
1509 * EEPROM will signal that the command has been completed by clearing
1510 * bit 0 of the internal status register. If it's not cleared within
1511 * 5 milliseconds, then error out.
1513 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1514 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1515 IXGBE_EEPROM_OPCODE_BITS);
1516 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1517 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1521 ixgbe_standby_eeprom(hw);
1525 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1526 * devices (and only 0-5mSec on 5V devices)
1528 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1529 hw_dbg(hw, "SPI EEPROM Status error\n");
1530 status = IXGBE_ERR_EEPROM;
1537 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1538 * @hw: pointer to hardware structure
1540 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1544 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1546 /* Toggle CS to flush commands */
1547 eec |= IXGBE_EEC_CS;
1548 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1549 IXGBE_WRITE_FLUSH(hw);
1551 eec &= ~IXGBE_EEC_CS;
1552 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1553 IXGBE_WRITE_FLUSH(hw);
1558 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1559 * @hw: pointer to hardware structure
1560 * @data: data to send to the EEPROM
1561 * @count: number of bits to shift out
1563 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1570 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1573 * Mask is used to shift "count" bits of "data" out to the EEPROM
1574 * one bit at a time. Determine the starting bit based on count
1576 mask = 0x01 << (count - 1);
1578 for (i = 0; i < count; i++) {
1580 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1581 * "1", and then raising and then lowering the clock (the SK
1582 * bit controls the clock input to the EEPROM). A "0" is
1583 * shifted out to the EEPROM by setting "DI" to "0" and then
1584 * raising and then lowering the clock.
1587 eec |= IXGBE_EEC_DI;
1589 eec &= ~IXGBE_EEC_DI;
1591 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1592 IXGBE_WRITE_FLUSH(hw);
1596 ixgbe_raise_eeprom_clk(hw, &eec);
1597 ixgbe_lower_eeprom_clk(hw, &eec);
1600 * Shift mask to signify next bit of data to shift in to the
1606 /* We leave the "DI" bit set to "0" when we leave this routine. */
1607 eec &= ~IXGBE_EEC_DI;
1608 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1609 IXGBE_WRITE_FLUSH(hw);
1613 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1614 * @hw: pointer to hardware structure
1616 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1623 * In order to read a register from the EEPROM, we need to shift
1624 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1625 * the clock input to the EEPROM (setting the SK bit), and then reading
1626 * the value of the "DO" bit. During this "shifting in" process the
1627 * "DI" bit should always be clear.
1629 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1631 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1633 for (i = 0; i < count; i++) {
1635 ixgbe_raise_eeprom_clk(hw, &eec);
1637 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1639 eec &= ~(IXGBE_EEC_DI);
1640 if (eec & IXGBE_EEC_DO)
1643 ixgbe_lower_eeprom_clk(hw, &eec);
1650 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1651 * @hw: pointer to hardware structure
1652 * @eec: EEC register's current value
1654 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1657 * Raise the clock input to the EEPROM
1658 * (setting the SK bit), then delay
1660 *eec = *eec | IXGBE_EEC_SK;
1661 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1662 IXGBE_WRITE_FLUSH(hw);
1667 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1668 * @hw: pointer to hardware structure
1669 * @eecd: EECD's current value
1671 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1674 * Lower the clock input to the EEPROM (clearing the SK bit), then
1677 *eec = *eec & ~IXGBE_EEC_SK;
1678 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1679 IXGBE_WRITE_FLUSH(hw);
1684 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1685 * @hw: pointer to hardware structure
1687 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1691 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1693 eec |= IXGBE_EEC_CS; /* Pull CS high */
1694 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1696 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1697 IXGBE_WRITE_FLUSH(hw);
1701 /* Stop requesting EEPROM access */
1702 eec &= ~IXGBE_EEC_REQ;
1703 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1705 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1707 /* Delay before attempt to obtain semaphore again to allow FW access */
1708 msleep(hw->eeprom.semaphore_delay);
1712 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1713 * @hw: pointer to hardware structure
1715 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1724 /* Include 0x0-0x3F in the checksum */
1725 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1726 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1727 hw_dbg(hw, "EEPROM read failed\n");
1733 /* Include all data from pointers except for the fw pointer */
1734 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1735 hw->eeprom.ops.read(hw, i, &pointer);
1737 /* Make sure the pointer seems valid */
1738 if (pointer != 0xFFFF && pointer != 0) {
1739 hw->eeprom.ops.read(hw, pointer, &length);
1741 if (length != 0xFFFF && length != 0) {
1742 for (j = pointer+1; j <= pointer+length; j++) {
1743 hw->eeprom.ops.read(hw, j, &word);
1750 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1756 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1757 * @hw: pointer to hardware structure
1758 * @checksum_val: calculated checksum
1760 * Performs checksum calculation and validates the EEPROM checksum. If the
1761 * caller does not need checksum_val, the value can be NULL.
1763 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1768 u16 read_checksum = 0;
1771 * Read the first word from the EEPROM. If this times out or fails, do
1772 * not continue or we could be in for a very long wait while every
1775 status = hw->eeprom.ops.read(hw, 0, &checksum);
1778 checksum = hw->eeprom.ops.calc_checksum(hw);
1780 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1783 * Verify read checksum from EEPROM is the same as
1784 * calculated checksum
1786 if (read_checksum != checksum)
1787 status = IXGBE_ERR_EEPROM_CHECKSUM;
1789 /* If the user cares, return the calculated checksum */
1791 *checksum_val = checksum;
1793 hw_dbg(hw, "EEPROM read failed\n");
1800 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1801 * @hw: pointer to hardware structure
1803 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1809 * Read the first word from the EEPROM. If this times out or fails, do
1810 * not continue or we could be in for a very long wait while every
1813 status = hw->eeprom.ops.read(hw, 0, &checksum);
1816 checksum = hw->eeprom.ops.calc_checksum(hw);
1817 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1820 hw_dbg(hw, "EEPROM read failed\n");
1827 * ixgbe_validate_mac_addr - Validate MAC address
1828 * @mac_addr: pointer to MAC address.
1830 * Tests a MAC address to ensure it is a valid Individual Address
1832 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1836 /* Make sure it is not a multicast address */
1837 if (IXGBE_IS_MULTICAST(mac_addr)) {
1838 hw_dbg(hw, "MAC address is multicast\n");
1839 status = IXGBE_ERR_INVALID_MAC_ADDR;
1840 /* Not a broadcast address */
1841 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1842 hw_dbg(hw, "MAC address is broadcast\n");
1843 status = IXGBE_ERR_INVALID_MAC_ADDR;
1844 /* Reject the zero address */
1845 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1846 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1847 hw_dbg(hw, "MAC address is all zeros\n");
1848 status = IXGBE_ERR_INVALID_MAC_ADDR;
1854 * ixgbe_set_rar_generic - Set Rx address register
1855 * @hw: pointer to hardware structure
1856 * @index: Receive address register to write
1857 * @addr: Address to put into receive address register
1858 * @vmdq: VMDq "set" or "pool" index
1859 * @enable_addr: set flag that address is active
1861 * Puts an ethernet address into a receive address register.
1863 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1866 u32 rar_low, rar_high;
1867 u32 rar_entries = hw->mac.num_rar_entries;
1869 /* Make sure we are using a valid rar index range */
1870 if (index >= rar_entries) {
1871 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1872 return IXGBE_ERR_INVALID_ARGUMENT;
1875 /* setup VMDq pool selection before this RAR gets enabled */
1876 hw->mac.ops.set_vmdq(hw, index, vmdq);
1879 * HW expects these in little endian so we reverse the byte
1880 * order from network order (big endian) to little endian
1882 rar_low = ((u32)addr[0] |
1883 ((u32)addr[1] << 8) |
1884 ((u32)addr[2] << 16) |
1885 ((u32)addr[3] << 24));
1887 * Some parts put the VMDq setting in the extra RAH bits,
1888 * so save everything except the lower 16 bits that hold part
1889 * of the address and the address valid bit.
1891 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1892 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1893 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1895 if (enable_addr != 0)
1896 rar_high |= IXGBE_RAH_AV;
1898 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1899 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1905 * ixgbe_clear_rar_generic - Remove Rx address register
1906 * @hw: pointer to hardware structure
1907 * @index: Receive address register to write
1909 * Clears an ethernet address from a receive address register.
1911 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1914 u32 rar_entries = hw->mac.num_rar_entries;
1916 /* Make sure we are using a valid rar index range */
1917 if (index >= rar_entries) {
1918 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1919 return IXGBE_ERR_INVALID_ARGUMENT;
1923 * Some parts put the VMDq setting in the extra RAH bits,
1924 * so save everything except the lower 16 bits that hold part
1925 * of the address and the address valid bit.
1927 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1928 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1930 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1931 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1933 /* clear VMDq pool/queue selection for this RAR */
1934 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1940 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1941 * @hw: pointer to hardware structure
1943 * Places the MAC address in receive address register 0 and clears the rest
1944 * of the receive address registers. Clears the multicast table. Assumes
1945 * the receiver is in reset when the routine is called.
1947 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1950 u32 rar_entries = hw->mac.num_rar_entries;
1953 * If the current mac address is valid, assume it is a software override
1954 * to the permanent address.
1955 * Otherwise, use the permanent address from the eeprom.
1957 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1958 IXGBE_ERR_INVALID_MAC_ADDR) {
1959 /* Get the MAC address from the RAR0 for later reference */
1960 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1962 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1963 hw->mac.addr[0], hw->mac.addr[1],
1965 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1966 hw->mac.addr[4], hw->mac.addr[5]);
1968 /* Setup the receive address. */
1969 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1970 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1971 hw->mac.addr[0], hw->mac.addr[1],
1973 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1974 hw->mac.addr[4], hw->mac.addr[5]);
1976 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1978 /* clear VMDq pool/queue selection for RAR 0 */
1979 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1981 hw->addr_ctrl.overflow_promisc = 0;
1983 hw->addr_ctrl.rar_used_count = 1;
1985 /* Zero out the other receive addresses. */
1986 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1987 for (i = 1; i < rar_entries; i++) {
1988 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1989 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1993 hw->addr_ctrl.mta_in_use = 0;
1994 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1996 hw_dbg(hw, " Clearing MTA\n");
1997 for (i = 0; i < hw->mac.mcft_size; i++)
1998 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2000 ixgbe_init_uta_tables(hw);
2006 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2007 * @hw: pointer to hardware structure
2008 * @addr: new address
2010 * Adds it to unused receive address register or goes into promiscuous mode.
2012 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2014 u32 rar_entries = hw->mac.num_rar_entries;
2017 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2018 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2021 * Place this address in the RAR if there is room,
2022 * else put the controller into promiscuous mode
2024 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2025 rar = hw->addr_ctrl.rar_used_count;
2026 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2027 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
2028 hw->addr_ctrl.rar_used_count++;
2030 hw->addr_ctrl.overflow_promisc++;
2033 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
2037 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2038 * @hw: pointer to hardware structure
2039 * @addr_list: the list of new addresses
2040 * @addr_count: number of addresses
2041 * @next: iterator function to walk the address list
2043 * The given list replaces any existing list. Clears the secondary addrs from
2044 * receive address registers. Uses unused receive address registers for the
2045 * first secondary addresses, and falls back to promiscuous mode as needed.
2047 * Drivers using secondary unicast addresses must set user_set_promisc when
2048 * manually putting the device into promiscuous mode.
2050 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2051 u32 addr_count, ixgbe_mc_addr_itr next)
2055 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2061 * Clear accounting of old secondary address list,
2062 * don't count RAR[0]
2064 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2065 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2066 hw->addr_ctrl.overflow_promisc = 0;
2068 /* Zero out the other receive addresses */
2069 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2070 for (i = 0; i < uc_addr_in_use; i++) {
2071 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2072 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2075 /* Add the new addresses */
2076 for (i = 0; i < addr_count; i++) {
2077 hw_dbg(hw, " Adding the secondary addresses:\n");
2078 addr = next(hw, &addr_list, &vmdq);
2079 ixgbe_add_uc_addr(hw, addr, vmdq);
2082 if (hw->addr_ctrl.overflow_promisc) {
2083 /* enable promisc if not already in overflow or set by user */
2084 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2085 hw_dbg(hw, " Entering address overflow promisc mode\n");
2086 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2087 fctrl |= IXGBE_FCTRL_UPE;
2088 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2091 /* only disable if set by overflow, not by user */
2092 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2093 hw_dbg(hw, " Leaving address overflow promisc mode\n");
2094 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2095 fctrl &= ~IXGBE_FCTRL_UPE;
2096 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2100 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2105 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2106 * @hw: pointer to hardware structure
2107 * @mc_addr: the multicast address
2109 * Extracts the 12 bits, from a multicast address, to determine which
2110 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2111 * incoming rx multicast addresses, to determine the bit-vector to check in
2112 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2113 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2114 * to mc_filter_type.
2116 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2120 switch (hw->mac.mc_filter_type) {
2121 case 0: /* use bits [47:36] of the address */
2122 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2124 case 1: /* use bits [46:35] of the address */
2125 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2127 case 2: /* use bits [45:34] of the address */
2128 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2130 case 3: /* use bits [43:32] of the address */
2131 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2133 default: /* Invalid mc_filter_type */
2134 hw_dbg(hw, "MC filter type param set incorrectly\n");
2138 /* vector can only be 12-bits or boundary will be exceeded */
2144 * ixgbe_set_mta - Set bit-vector in multicast table
2145 * @hw: pointer to hardware structure
2146 * @hash_value: Multicast address hash value
2148 * Sets the bit-vector in the multicast table.
2150 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2156 hw->addr_ctrl.mta_in_use++;
2158 vector = ixgbe_mta_vector(hw, mc_addr);
2159 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2162 * The MTA is a register array of 128 32-bit registers. It is treated
2163 * like an array of 4096 bits. We want to set bit
2164 * BitArray[vector_value]. So we figure out what register the bit is
2165 * in, read it, OR in the new bit, then write back the new value. The
2166 * register is determined by the upper 7 bits of the vector value and
2167 * the bit within that register are determined by the lower 5 bits of
2170 vector_reg = (vector >> 5) & 0x7F;
2171 vector_bit = vector & 0x1F;
2172 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2176 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2177 * @hw: pointer to hardware structure
2178 * @mc_addr_list: the list of new multicast addresses
2179 * @mc_addr_count: number of addresses
2180 * @next: iterator function to walk the multicast address list
2181 * @clear: flag, when set clears the table beforehand
2183 * When the clear flag is set, the given list replaces any existing list.
2184 * Hashes the given addresses into the multicast table.
2186 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2187 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2194 * Set the new number of MC addresses that we are being requested to
2197 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2198 hw->addr_ctrl.mta_in_use = 0;
2200 /* Clear mta_shadow */
2202 hw_dbg(hw, " Clearing MTA\n");
2203 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2206 /* Update mta_shadow */
2207 for (i = 0; i < mc_addr_count; i++) {
2208 hw_dbg(hw, " Adding the multicast addresses:\n");
2209 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2213 for (i = 0; i < hw->mac.mcft_size; i++)
2214 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2215 hw->mac.mta_shadow[i]);
2217 if (hw->addr_ctrl.mta_in_use > 0)
2218 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2219 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2221 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2226 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2227 * @hw: pointer to hardware structure
2229 * Enables multicast address in RAR and the use of the multicast hash table.
2231 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2233 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2235 if (a->mta_in_use > 0)
2236 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2237 hw->mac.mc_filter_type);
2243 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2244 * @hw: pointer to hardware structure
2246 * Disables multicast address in RAR and the use of the multicast hash table.
2248 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2250 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2252 if (a->mta_in_use > 0)
2253 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2259 * ixgbe_fc_enable_generic - Enable flow control
2260 * @hw: pointer to hardware structure
2262 * Enable flow control according to the current settings.
2264 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2267 u32 mflcn_reg, fccfg_reg;
2272 /* Validate the water mark configuration */
2273 if (!hw->fc.pause_time) {
2274 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2278 /* Low water mark of zero causes XOFF floods */
2279 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2280 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2281 hw->fc.high_water[i]) {
2282 if (!hw->fc.low_water[i] ||
2283 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2284 hw_dbg(hw, "Invalid water mark configuration\n");
2285 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2291 /* Negotiate the fc mode to use */
2292 ixgbe_fc_autoneg(hw);
2294 /* Disable any previous flow control settings */
2295 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2296 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2298 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2299 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2302 * The possible values of fc.current_mode are:
2303 * 0: Flow control is completely disabled
2304 * 1: Rx flow control is enabled (we can receive pause frames,
2305 * but not send pause frames).
2306 * 2: Tx flow control is enabled (we can send pause frames but
2307 * we do not support receiving pause frames).
2308 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2311 switch (hw->fc.current_mode) {
2314 * Flow control is disabled by software override or autoneg.
2315 * The code below will actually disable it in the HW.
2318 case ixgbe_fc_rx_pause:
2320 * Rx Flow control is enabled and Tx Flow control is
2321 * disabled by software override. Since there really
2322 * isn't a way to advertise that we are capable of RX
2323 * Pause ONLY, we will advertise that we support both
2324 * symmetric and asymmetric Rx PAUSE. Later, we will
2325 * disable the adapter's ability to send PAUSE frames.
2327 mflcn_reg |= IXGBE_MFLCN_RFCE;
2329 case ixgbe_fc_tx_pause:
2331 * Tx Flow control is enabled, and Rx Flow control is
2332 * disabled by software override.
2334 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2337 /* Flow control (both Rx and Tx) is enabled by SW override. */
2338 mflcn_reg |= IXGBE_MFLCN_RFCE;
2339 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2342 hw_dbg(hw, "Flow control param set incorrectly\n");
2343 ret_val = IXGBE_ERR_CONFIG;
2348 /* Set 802.3x based flow control settings. */
2349 mflcn_reg |= IXGBE_MFLCN_DPF;
2350 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2351 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2354 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2355 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2356 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2357 hw->fc.high_water[i]) {
2358 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2359 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2360 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2362 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2364 * In order to prevent Tx hangs when the internal Tx
2365 * switch is enabled we must set the high water mark
2366 * to the maximum FCRTH value. This allows the Tx
2367 * switch to function even under heavy Rx workloads.
2369 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2372 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2375 /* Configure pause time (2 TCs per register) */
2376 reg = hw->fc.pause_time * 0x00010001;
2377 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2378 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2380 /* Configure flow control refresh threshold value */
2381 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2388 * ixgbe_negotiate_fc - Negotiate flow control
2389 * @hw: pointer to hardware structure
2390 * @adv_reg: flow control advertised settings
2391 * @lp_reg: link partner's flow control settings
2392 * @adv_sym: symmetric pause bit in advertisement
2393 * @adv_asm: asymmetric pause bit in advertisement
2394 * @lp_sym: symmetric pause bit in link partner advertisement
2395 * @lp_asm: asymmetric pause bit in link partner advertisement
2397 * Find the intersection between advertised settings and link partner's
2398 * advertised settings
2400 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2401 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2403 if (!adv_reg || !lp_reg)
2404 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2406 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2408 * Now we need to check if the user selected Rx ONLY
2409 * of pause frames. In this case, we had to advertise
2410 * FULL flow control because we could not advertise RX
2411 * ONLY. Hence, we must now check to see if we need to
2412 * turn OFF the TRANSMISSION of PAUSE frames.
2414 if (hw->fc.requested_mode == ixgbe_fc_full) {
2415 hw->fc.current_mode = ixgbe_fc_full;
2416 hw_dbg(hw, "Flow Control = FULL.\n");
2418 hw->fc.current_mode = ixgbe_fc_rx_pause;
2419 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2421 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2422 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2423 hw->fc.current_mode = ixgbe_fc_tx_pause;
2424 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2425 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2426 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2427 hw->fc.current_mode = ixgbe_fc_rx_pause;
2428 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2430 hw->fc.current_mode = ixgbe_fc_none;
2431 hw_dbg(hw, "Flow Control = NONE.\n");
2437 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2438 * @hw: pointer to hardware structure
2440 * Enable flow control according on 1 gig fiber.
2442 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2444 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2445 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2448 * On multispeed fiber at 1g, bail out if
2449 * - link is up but AN did not complete, or if
2450 * - link is up and AN completed but timed out
2453 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2454 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2455 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2458 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2459 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2461 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2462 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2463 IXGBE_PCS1GANA_ASM_PAUSE,
2464 IXGBE_PCS1GANA_SYM_PAUSE,
2465 IXGBE_PCS1GANA_ASM_PAUSE);
2472 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2473 * @hw: pointer to hardware structure
2475 * Enable flow control according to IEEE clause 37.
2477 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2479 u32 links2, anlp1_reg, autoc_reg, links;
2480 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2483 * On backplane, bail out if
2484 * - backplane autoneg was not completed, or if
2485 * - we are 82599 and link partner is not AN enabled
2487 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2488 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2491 if (hw->mac.type == ixgbe_mac_82599EB) {
2492 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2493 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2497 * Read the 10g AN autoc and LP ability registers and resolve
2498 * local flow control settings accordingly
2500 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2501 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2503 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2504 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2505 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2512 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2513 * @hw: pointer to hardware structure
2515 * Enable flow control according to IEEE clause 37.
2517 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2519 u16 technology_ability_reg = 0;
2520 u16 lp_technology_ability_reg = 0;
2522 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2523 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2524 &technology_ability_reg);
2525 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2526 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2527 &lp_technology_ability_reg);
2529 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2530 (u32)lp_technology_ability_reg,
2531 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2532 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2536 * ixgbe_fc_autoneg - Configure flow control
2537 * @hw: pointer to hardware structure
2539 * Compares our advertised flow control capabilities to those advertised by
2540 * our link partner, and determines the proper flow control mode to use.
2542 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2544 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2545 ixgbe_link_speed speed;
2549 * AN should have completed when the cable was plugged in.
2550 * Look for reasons to bail out. Bail out if:
2551 * - FC autoneg is disabled, or if
2554 if (hw->fc.disable_fc_autoneg)
2557 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2561 switch (hw->phy.media_type) {
2562 /* Autoneg flow control on fiber adapters */
2563 case ixgbe_media_type_fiber:
2564 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2565 ret_val = ixgbe_fc_autoneg_fiber(hw);
2568 /* Autoneg flow control on backplane adapters */
2569 case ixgbe_media_type_backplane:
2570 ret_val = ixgbe_fc_autoneg_backplane(hw);
2573 /* Autoneg flow control on copper adapters */
2574 case ixgbe_media_type_copper:
2575 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2576 ret_val = ixgbe_fc_autoneg_copper(hw);
2585 hw->fc.fc_was_autonegged = true;
2587 hw->fc.fc_was_autonegged = false;
2588 hw->fc.current_mode = hw->fc.requested_mode;
2593 * ixgbe_disable_pcie_master - Disable PCI-express master access
2594 * @hw: pointer to hardware structure
2596 * Disables PCI-Express master access and verifies there are no pending
2597 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2598 * bit hasn't caused the master requests to be disabled, else 0
2599 * is returned signifying master requests disabled.
2601 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2606 /* Always set this bit to ensure any future transactions are blocked */
2607 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2609 /* Exit if master requets are blocked */
2610 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2613 /* Poll for master request bit to clear */
2614 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2616 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2621 * Two consecutive resets are required via CTRL.RST per datasheet
2622 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2623 * of this need. The first reset prevents new master requests from
2624 * being issued by our device. We then must wait 1usec or more for any
2625 * remaining completions from the PCIe bus to trickle in, and then reset
2626 * again to clear out any effects they may have had on our device.
2628 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2629 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2632 * Before proceeding, make sure that the PCIe block does not have
2633 * transactions pending.
2635 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2637 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2638 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2642 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2643 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2650 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2651 * @hw: pointer to hardware structure
2652 * @mask: Mask to specify which semaphore to acquire
2654 * Acquires the SWFW semaphore through the GSSR register for the specified
2655 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2657 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2661 u32 fwmask = mask << 5;
2666 * SW EEPROM semaphore bit is used for access to all
2667 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2669 if (ixgbe_get_eeprom_semaphore(hw))
2670 return IXGBE_ERR_SWFW_SYNC;
2672 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2673 if (!(gssr & (fwmask | swmask)))
2677 * Firmware currently using resource (fwmask) or other software
2678 * thread currently using resource (swmask)
2680 ixgbe_release_eeprom_semaphore(hw);
2686 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2687 return IXGBE_ERR_SWFW_SYNC;
2691 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2693 ixgbe_release_eeprom_semaphore(hw);
2698 * ixgbe_release_swfw_sync - Release SWFW semaphore
2699 * @hw: pointer to hardware structure
2700 * @mask: Mask to specify which semaphore to release
2702 * Releases the SWFW semaphore through the GSSR register for the specified
2703 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2705 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2710 ixgbe_get_eeprom_semaphore(hw);
2712 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2714 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2716 ixgbe_release_eeprom_semaphore(hw);
2720 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2721 * @hw: pointer to hardware structure
2723 * Stops the receive data path and waits for the HW to internally empty
2724 * the Rx security block
2726 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2728 #define IXGBE_MAX_SECRX_POLL 40
2733 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2734 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2735 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2736 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2737 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2738 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2741 /* Use interrupt-safe sleep just in case */
2745 /* For informational purposes only */
2746 if (i >= IXGBE_MAX_SECRX_POLL)
2747 hw_dbg(hw, "Rx unit being enabled before security "
2748 "path fully disabled. Continuing with init.\n");
2754 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2755 * @hw: pointer to hardware structure
2757 * Enables the receive data path.
2759 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2763 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2764 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2765 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2766 IXGBE_WRITE_FLUSH(hw);
2772 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2773 * @hw: pointer to hardware structure
2774 * @regval: register value to write to RXCTRL
2776 * Enables the Rx DMA unit
2778 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2780 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2786 * ixgbe_blink_led_start_generic - Blink LED based on index.
2787 * @hw: pointer to hardware structure
2788 * @index: led number to blink
2790 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2792 ixgbe_link_speed speed = 0;
2794 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2795 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2798 * Link must be up to auto-blink the LEDs;
2799 * Force it if link is down.
2801 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2804 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2805 autoc_reg |= IXGBE_AUTOC_FLU;
2806 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2807 IXGBE_WRITE_FLUSH(hw);
2811 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2812 led_reg |= IXGBE_LED_BLINK(index);
2813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2814 IXGBE_WRITE_FLUSH(hw);
2820 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2821 * @hw: pointer to hardware structure
2822 * @index: led number to stop blinking
2824 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2826 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2827 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2829 autoc_reg &= ~IXGBE_AUTOC_FLU;
2830 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2831 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2833 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2834 led_reg &= ~IXGBE_LED_BLINK(index);
2835 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2836 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2837 IXGBE_WRITE_FLUSH(hw);
2843 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2844 * @hw: pointer to hardware structure
2845 * @san_mac_offset: SAN MAC address offset
2847 * This function will read the EEPROM location for the SAN MAC address
2848 * pointer, and returns the value at that location. This is used in both
2849 * get and set mac_addr routines.
2851 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2852 u16 *san_mac_offset)
2855 * First read the EEPROM pointer to see if the MAC addresses are
2858 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2864 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2865 * @hw: pointer to hardware structure
2866 * @san_mac_addr: SAN MAC address
2868 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2869 * per-port, so set_lan_id() must be called before reading the addresses.
2870 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2871 * upon for non-SFP connections, so we must call it here.
2873 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2875 u16 san_mac_data, san_mac_offset;
2879 * First read the EEPROM pointer to see if the MAC addresses are
2880 * available. If they're not, no point in calling set_lan_id() here.
2882 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2884 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2886 * No addresses available in this EEPROM. It's not an
2887 * error though, so just wipe the local address and return.
2889 for (i = 0; i < 6; i++)
2890 san_mac_addr[i] = 0xFF;
2892 goto san_mac_addr_out;
2895 /* make sure we know which port we need to program */
2896 hw->mac.ops.set_lan_id(hw);
2897 /* apply the port offset to the address offset */
2898 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2899 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2900 for (i = 0; i < 3; i++) {
2901 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2902 san_mac_addr[i * 2] = (u8)(san_mac_data);
2903 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2912 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2913 * @hw: pointer to hardware structure
2914 * @san_mac_addr: SAN MAC address
2916 * Write a SAN MAC address to the EEPROM.
2918 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2921 u16 san_mac_data, san_mac_offset;
2924 /* Look for SAN mac address pointer. If not defined, return */
2925 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2927 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2928 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2929 goto san_mac_addr_out;
2932 /* Make sure we know which port we need to write */
2933 hw->mac.ops.set_lan_id(hw);
2934 /* Apply the port offset to the address offset */
2935 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2936 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2938 for (i = 0; i < 3; i++) {
2939 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2940 san_mac_data |= (u16)(san_mac_addr[i * 2]);
2941 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2950 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2951 * @hw: pointer to hardware structure
2953 * Read PCIe configuration space, and get the MSI-X vector count from
2954 * the capabilities table.
2956 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2962 switch (hw->mac.type) {
2963 case ixgbe_mac_82598EB:
2964 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2965 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2967 case ixgbe_mac_82599EB:
2968 case ixgbe_mac_X540:
2969 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2970 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2976 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
2977 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2979 /* MSI-X count is zero-based in HW */
2982 if (msix_count > max_msix_count)
2983 msix_count = max_msix_count;
2989 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
2990 * @hw: pointer to hardware structure
2991 * @addr: Address to put into receive address register
2992 * @vmdq: VMDq pool to assign
2994 * Puts an ethernet address into a receive address register, or
2995 * finds the rar that it is already in; adds to the pool list
2997 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2999 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3000 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3002 u32 rar_low, rar_high;
3003 u32 addr_low, addr_high;
3005 /* swap bytes for HW little endian */
3006 addr_low = addr[0] | (addr[1] << 8)
3009 addr_high = addr[4] | (addr[5] << 8);
3012 * Either find the mac_id in rar or find the first empty space.
3013 * rar_highwater points to just after the highest currently used
3014 * rar in order to shorten the search. It grows when we add a new
3017 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3018 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3020 if (((IXGBE_RAH_AV & rar_high) == 0)
3021 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3022 first_empty_rar = rar;
3023 } else if ((rar_high & 0xFFFF) == addr_high) {
3024 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3025 if (rar_low == addr_low)
3026 break; /* found it already in the rars */
3030 if (rar < hw->mac.rar_highwater) {
3031 /* already there so just add to the pool bits */
3032 ixgbe_set_vmdq(hw, rar, vmdq);
3033 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3034 /* stick it into first empty RAR slot we found */
3035 rar = first_empty_rar;
3036 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3037 } else if (rar == hw->mac.rar_highwater) {
3038 /* add it to the top of the list and inc the highwater mark */
3039 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3040 hw->mac.rar_highwater++;
3041 } else if (rar >= hw->mac.num_rar_entries) {
3042 return IXGBE_ERR_INVALID_MAC_ADDR;
3046 * If we found rar[0], make sure the default pool bit (we use pool 0)
3047 * remains cleared to be sure default pool packets will get delivered
3050 ixgbe_clear_vmdq(hw, rar, 0);
3056 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3057 * @hw: pointer to hardware struct
3058 * @rar: receive address register index to disassociate
3059 * @vmdq: VMDq pool index to remove from the rar
3061 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3063 u32 mpsar_lo, mpsar_hi;
3064 u32 rar_entries = hw->mac.num_rar_entries;
3066 /* Make sure we are using a valid rar index range */
3067 if (rar >= rar_entries) {
3068 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3069 return IXGBE_ERR_INVALID_ARGUMENT;
3072 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3073 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3075 if (!mpsar_lo && !mpsar_hi)
3078 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3080 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3084 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3087 } else if (vmdq < 32) {
3088 mpsar_lo &= ~(1 << vmdq);
3089 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3091 mpsar_hi &= ~(1 << (vmdq - 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3095 /* was that the last pool using this rar? */
3096 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3097 hw->mac.ops.clear_rar(hw, rar);
3103 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3104 * @hw: pointer to hardware struct
3105 * @rar: receive address register index to associate with a VMDq index
3106 * @vmdq: VMDq pool index
3108 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3111 u32 rar_entries = hw->mac.num_rar_entries;
3113 /* Make sure we are using a valid rar index range */
3114 if (rar >= rar_entries) {
3115 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
3116 return IXGBE_ERR_INVALID_ARGUMENT;
3120 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3122 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3124 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3125 mpsar |= 1 << (vmdq - 32);
3126 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3132 * This function should only be involved in the IOV mode.
3133 * In IOV mode, Default pool is next pool after the number of
3134 * VFs advertized and not 0.
3135 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3137 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3138 * @hw: pointer to hardware struct
3139 * @vmdq: VMDq pool index
3141 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3144 u32 rar = hw->mac.san_mac_rar_index;
3147 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3149 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3151 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3152 mpsar |= 1 << (vmdq - 32);
3153 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3160 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3161 * @hw: pointer to hardware structure
3163 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3167 hw_dbg(hw, " Clearing UTA\n");
3169 for (i = 0; i < 128; i++)
3170 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3176 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3177 * @hw: pointer to hardware structure
3178 * @vlan: VLAN id to write to VLAN filter
3180 * return the VLVF index where this VLAN id should be placed
3183 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3186 u32 first_empty_slot = 0;
3189 /* short cut the special case */
3194 * Search for the vlan id in the VLVF entries. Save off the first empty
3195 * slot found along the way
3197 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3198 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3199 if (!bits && !(first_empty_slot))
3200 first_empty_slot = regindex;
3201 else if ((bits & 0x0FFF) == vlan)
3206 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3207 * in the VLVF. Else use the first empty VLVF register for this
3210 if (regindex >= IXGBE_VLVF_ENTRIES) {
3211 if (first_empty_slot)
3212 regindex = first_empty_slot;
3214 hw_dbg(hw, "No space in VLVF.\n");
3215 regindex = IXGBE_ERR_NO_SPACE;
3223 * ixgbe_set_vfta_generic - Set VLAN filter table
3224 * @hw: pointer to hardware structure
3225 * @vlan: VLAN id to write to VLAN filter
3226 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3227 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3229 * Turn on/off specified VLAN in the VLAN filter table.
3231 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3239 bool vfta_changed = false;
3242 return IXGBE_ERR_PARAM;
3245 * this is a 2 part operation - first the VFTA, then the
3246 * VLVF and VLVFB if VT Mode is set
3247 * We don't write the VFTA until we know the VLVF part succeeded.
3251 * The VFTA is a bitstring made up of 128 32-bit registers
3252 * that enable the particular VLAN id, much like the MTA:
3253 * bits[11-5]: which register
3254 * bits[4-0]: which bit in the register
3256 regindex = (vlan >> 5) & 0x7F;
3257 bitindex = vlan & 0x1F;
3258 targetbit = (1 << bitindex);
3259 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3262 if (!(vfta & targetbit)) {
3264 vfta_changed = true;
3267 if (vfta & targetbit) {
3269 vfta_changed = true;
3274 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3276 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3282 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3288 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3289 * @hw: pointer to hardware structure
3290 * @vlan: VLAN id to write to VLAN filter
3291 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3292 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3293 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3296 * Turn on/off specified bit in VLVF table.
3298 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3299 bool vlan_on, bool *vfta_changed)
3304 return IXGBE_ERR_PARAM;
3306 /* If VT Mode is set
3308 * make sure the vlan is in VLVF
3309 * set the vind bit in the matching VLVFB
3311 * clear the pool bit and possibly the vind
3313 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3314 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3318 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3323 /* set the pool bit */
3325 bits = IXGBE_READ_REG(hw,
3326 IXGBE_VLVFB(vlvf_index * 2));
3327 bits |= (1 << vind);
3329 IXGBE_VLVFB(vlvf_index * 2),
3332 bits = IXGBE_READ_REG(hw,
3333 IXGBE_VLVFB((vlvf_index * 2) + 1));
3334 bits |= (1 << (vind - 32));
3336 IXGBE_VLVFB((vlvf_index * 2) + 1),
3340 /* clear the pool bit */
3342 bits = IXGBE_READ_REG(hw,
3343 IXGBE_VLVFB(vlvf_index * 2));
3344 bits &= ~(1 << vind);
3346 IXGBE_VLVFB(vlvf_index * 2),
3348 bits |= IXGBE_READ_REG(hw,
3349 IXGBE_VLVFB((vlvf_index * 2) + 1));
3351 bits = IXGBE_READ_REG(hw,
3352 IXGBE_VLVFB((vlvf_index * 2) + 1));
3353 bits &= ~(1 << (vind - 32));
3355 IXGBE_VLVFB((vlvf_index * 2) + 1),
3357 bits |= IXGBE_READ_REG(hw,
3358 IXGBE_VLVFB(vlvf_index * 2));
3363 * If there are still bits set in the VLVFB registers
3364 * for the VLAN ID indicated we need to see if the
3365 * caller is requesting that we clear the VFTA entry bit.
3366 * If the caller has requested that we clear the VFTA
3367 * entry bit but there are still pools/VFs using this VLAN
3368 * ID entry then ignore the request. We're not worried
3369 * about the case where we're turning the VFTA VLAN ID
3370 * entry bit on, only when requested to turn it off as
3371 * there may be multiple pools and/or VFs using the
3372 * VLAN ID entry. In that case we cannot clear the
3373 * VFTA bit until all pools/VFs using that VLAN ID have also
3374 * been cleared. This will be indicated by "bits" being
3378 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3379 (IXGBE_VLVF_VIEN | vlan));
3380 if (!vlan_on && (vfta_changed != NULL)) {
3381 /* someone wants to clear the vfta entry
3382 * but some pools/VFs are still using it.
3384 *vfta_changed = false;
3387 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3394 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3395 * @hw: pointer to hardware structure
3397 * Clears the VLAN filer table, and the VMDq index associated with the filter
3399 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3403 for (offset = 0; offset < hw->mac.vft_size; offset++)
3404 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3406 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3407 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3408 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3409 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3416 * ixgbe_check_mac_link_generic - Determine link and speed status
3417 * @hw: pointer to hardware structure
3418 * @speed: pointer to link speed
3419 * @link_up: true when link is up
3420 * @link_up_wait_to_complete: bool used to wait for link up or not
3422 * Reads the links register to determine if link is up and the current speed
3424 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3425 bool *link_up, bool link_up_wait_to_complete)
3427 u32 links_reg, links_orig;
3430 /* clear the old state */
3431 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3433 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3435 if (links_orig != links_reg) {
3436 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3437 links_orig, links_reg);
3440 if (link_up_wait_to_complete) {
3441 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3442 if (links_reg & IXGBE_LINKS_UP) {
3449 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3452 if (links_reg & IXGBE_LINKS_UP)
3458 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3459 IXGBE_LINKS_SPEED_10G_82599)
3460 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3461 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3462 IXGBE_LINKS_SPEED_1G_82599)
3463 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3464 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3465 IXGBE_LINKS_SPEED_100_82599)
3466 *speed = IXGBE_LINK_SPEED_100_FULL;
3468 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3474 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3476 * @hw: pointer to hardware structure
3477 * @wwnn_prefix: the alternative WWNN prefix
3478 * @wwpn_prefix: the alternative WWPN prefix
3480 * This function will read the EEPROM from the alternative SAN MAC address
3481 * block to check the support for the alternative WWNN/WWPN prefix support.
3483 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3487 u16 alt_san_mac_blk_offset;
3489 /* clear output first */
3490 *wwnn_prefix = 0xFFFF;
3491 *wwpn_prefix = 0xFFFF;
3493 /* check if alternative SAN MAC is supported */
3494 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3495 &alt_san_mac_blk_offset);
3497 if ((alt_san_mac_blk_offset == 0) ||
3498 (alt_san_mac_blk_offset == 0xFFFF))
3499 goto wwn_prefix_out;
3501 /* check capability in alternative san mac address block */
3502 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3503 hw->eeprom.ops.read(hw, offset, &caps);
3504 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3505 goto wwn_prefix_out;
3507 /* get the corresponding prefix for WWNN/WWPN */
3508 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3509 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3511 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3512 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3519 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3520 * @hw: pointer to hardware structure
3521 * @bs: the fcoe boot status
3523 * This function will read the FCOE boot status from the iSCSI FCOE block
3525 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3527 u16 offset, caps, flags;
3530 /* clear output first */
3531 *bs = ixgbe_fcoe_bootstatus_unavailable;
3533 /* check if FCOE IBA block is present */
3534 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3535 status = hw->eeprom.ops.read(hw, offset, &caps);
3539 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3542 /* check if iSCSI FCOE block is populated */
3543 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3547 if ((offset == 0) || (offset == 0xFFFF))
3550 /* read fcoe flags in iSCSI FCOE block */
3551 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3552 status = hw->eeprom.ops.read(hw, offset, &flags);
3556 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3557 *bs = ixgbe_fcoe_bootstatus_enabled;
3559 *bs = ixgbe_fcoe_bootstatus_disabled;
3566 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3567 * @hw: pointer to hardware structure
3568 * @enable: enable or disable switch for anti-spoofing
3569 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3572 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3575 int pf_target_reg = pf >> 3;
3576 int pf_target_shift = pf % 8;
3579 if (hw->mac.type == ixgbe_mac_82598EB)
3583 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3586 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3587 * MAC anti-spoof enables in each register array element.
3589 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3590 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3592 /* If not enabling anti-spoofing then done */
3597 * The PF should be allowed to spoof so that it can support
3598 * emulation mode NICs. Reset the bit assigned to the PF
3600 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3601 pfvfspoof ^= (1 << pf_target_shift);
3602 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3606 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3607 * @hw: pointer to hardware structure
3608 * @enable: enable or disable switch for VLAN anti-spoofing
3609 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3612 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3614 int vf_target_reg = vf >> 3;
3615 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3618 if (hw->mac.type == ixgbe_mac_82598EB)
3621 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3623 pfvfspoof |= (1 << vf_target_shift);
3625 pfvfspoof &= ~(1 << vf_target_shift);
3626 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3630 * ixgbe_get_device_caps_generic - Get additional device capabilities
3631 * @hw: pointer to hardware structure
3632 * @device_caps: the EEPROM word with the extra device capabilities
3634 * This function will read the EEPROM location for the device capabilities,
3635 * and return the word through device_caps.
3637 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3639 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3645 * ixgbe_calculate_checksum - Calculate checksum for buffer
3646 * @buffer: pointer to EEPROM
3647 * @length: size of EEPROM to calculate a checksum for
3648 * Calculates the checksum for some buffer on a specified length. The
3649 * checksum calculated is returned.
3651 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3658 for (i = 0; i < length; i++)
3661 return (u8) (0 - sum);
3665 * ixgbe_host_interface_command - Issue command to manageability block
3666 * @hw: pointer to the HW structure
3667 * @buffer: contains the command to write and where the return status will
3669 * @length: length of buffer, must be multiple of 4 bytes
3671 * Communicates with the manageability block. On success return 0
3672 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3674 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3678 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3679 u8 buf_len, dword_len;
3683 if (length == 0 || length & 0x3 ||
3684 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3685 hw_dbg(hw, "Buffer length failure.\n");
3686 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3690 /* Check that the host interface is enabled. */
3691 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3692 if ((hicr & IXGBE_HICR_EN) == 0) {
3693 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3694 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3698 /* Calculate length in DWORDs */
3699 dword_len = length >> 2;
3702 * The device driver writes the relevant command block
3703 * into the ram area.
3705 for (i = 0; i < dword_len; i++)
3706 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3707 i, IXGBE_CPU_TO_LE32(buffer[i]));
3709 /* Setting this bit tells the ARC that a new command is pending. */
3710 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3712 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3713 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3714 if (!(hicr & IXGBE_HICR_C))
3719 /* Check command successful completion. */
3720 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3721 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3722 hw_dbg(hw, "Command has failed with no status valid.\n");
3723 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3727 /* Calculate length in DWORDs */
3728 dword_len = hdr_size >> 2;
3730 /* first pull in the header so we know the buffer length */
3731 for (bi = 0; bi < dword_len; bi++) {
3732 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3733 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3736 /* If there is any thing in data position pull it in */
3737 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3741 if (length < (buf_len + hdr_size)) {
3742 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3743 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3747 /* Calculate length in DWORDs, add 3 for odd lengths */
3748 dword_len = (buf_len + 3) >> 2;
3750 /* Pull in the rest of the buffer (bi is where we left off)*/
3751 for (; bi <= dword_len; bi++) {
3752 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3753 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3761 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3762 * @hw: pointer to the HW structure
3763 * @maj: driver version major number
3764 * @min: driver version minor number
3765 * @build: driver version build number
3766 * @sub: driver version sub build number
3768 * Sends driver version number to firmware through the manageability
3769 * block. On success return 0
3770 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3771 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3773 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3776 struct ixgbe_hic_drv_info fw_cmd;
3780 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
3782 ret_val = IXGBE_ERR_SWFW_SYNC;
3786 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3787 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3788 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3789 fw_cmd.port_num = (u8)hw->bus.func;
3790 fw_cmd.ver_maj = maj;
3791 fw_cmd.ver_min = min;
3792 fw_cmd.ver_build = build;
3793 fw_cmd.ver_sub = sub;
3794 fw_cmd.hdr.checksum = 0;
3795 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3796 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3800 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3801 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3806 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3807 FW_CEM_RESP_STATUS_SUCCESS)
3810 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3815 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3821 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
3822 * @hw: pointer to hardware structure
3823 * @num_pb: number of packet buffers to allocate
3824 * @headroom: reserve n KB of headroom
3825 * @strategy: packet buffer allocation strategy
3827 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
3830 u32 pbsize = hw->mac.rx_pb_size;
3832 u32 rxpktsize, txpktsize, txpbthresh;
3834 /* Reserve headroom */
3840 /* Divide remaining packet buffer space amongst the number of packet
3841 * buffers requested using supplied strategy.
3844 case PBA_STRATEGY_WEIGHTED:
3845 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
3846 * buffer with 5/8 of the packet buffer space.
3848 rxpktsize = (pbsize * 5) / (num_pb * 4);
3849 pbsize -= rxpktsize * (num_pb / 2);
3850 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3851 for (; i < (num_pb / 2); i++)
3852 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3853 /* Fall through to configure remaining packet buffers */
3854 case PBA_STRATEGY_EQUAL:
3855 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3856 for (; i < num_pb; i++)
3857 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3863 /* Only support an equally distributed Tx packet buffer strategy. */
3864 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3865 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3866 for (i = 0; i < num_pb; i++) {
3867 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3868 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3871 /* Clear unused TCs, if any, to zero buffer size*/
3872 for (; i < IXGBE_MAX_PB; i++) {
3873 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3874 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3875 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3880 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3881 * @hw: pointer to the hardware structure
3883 * The 82599 and x540 MACs can experience issues if TX work is still pending
3884 * when a reset occurs. This function prevents this by flushing the PCIe
3885 * buffers on the system.
3887 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3889 u32 gcr_ext, hlreg0;
3892 * If double reset is not requested then all transactions should
3893 * already be clear and as such there is no work to do
3895 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3899 * Set loopback enable to prevent any transmits from being sent
3900 * should the link come up. This assumes that the RXCTRL.RXEN bit
3901 * has already been cleared.
3903 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3904 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3906 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3907 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3908 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3909 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3911 /* Flush all writes and allow 20usec for all transactions to clear */
3912 IXGBE_WRITE_FLUSH(hw);
3915 /* restore previous register values */
3916 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3917 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3920 static const u8 ixgbe_emc_temp_data[4] = {
3921 IXGBE_EMC_INTERNAL_DATA,
3922 IXGBE_EMC_DIODE1_DATA,
3923 IXGBE_EMC_DIODE2_DATA,
3924 IXGBE_EMC_DIODE3_DATA
3926 static const u8 ixgbe_emc_therm_limit[4] = {
3927 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3928 IXGBE_EMC_DIODE1_THERM_LIMIT,
3929 IXGBE_EMC_DIODE2_THERM_LIMIT,
3930 IXGBE_EMC_DIODE3_THERM_LIMIT
3934 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3935 * @hw: pointer to hardware structure
3936 * @data: pointer to the thermal sensor data structure
3938 * Returns the thermal sensor data structure
3940 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3950 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3952 /* Only support thermal sensors attached to 82599 physical port 0 */
3953 if ((hw->mac.type != ixgbe_mac_82599EB) ||
3954 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3955 status = IXGBE_NOT_IMPLEMENTED;
3959 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
3963 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
3964 status = IXGBE_NOT_IMPLEMENTED;
3968 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
3972 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
3973 != IXGBE_ETS_TYPE_EMC) {
3974 status = IXGBE_NOT_IMPLEMENTED;
3978 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3979 if (num_sensors > IXGBE_MAX_SENSORS)
3980 num_sensors = IXGBE_MAX_SENSORS;
3982 for (i = 0; i < num_sensors; i++) {
3983 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3988 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3989 IXGBE_ETS_DATA_INDEX_SHIFT);
3990 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3991 IXGBE_ETS_DATA_LOC_SHIFT);
3993 if (sensor_location != 0) {
3994 status = hw->phy.ops.read_i2c_byte(hw,
3995 ixgbe_emc_temp_data[sensor_index],
3996 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3997 &data->sensor[i].temp);
4007 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4008 * @hw: pointer to hardware structure
4010 * Inits the thermal sensor thresholds according to the NVM map
4011 * and save off the threshold and location values into mac.thermal_sensor_data
4013 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4019 u8 low_thresh_delta;
4025 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4027 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4029 /* Only support thermal sensors attached to 82599 physical port 0 */
4030 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4031 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4032 return IXGBE_NOT_IMPLEMENTED;
4034 hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4035 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4036 return IXGBE_NOT_IMPLEMENTED;
4038 hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4039 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4040 != IXGBE_ETS_TYPE_EMC)
4041 return IXGBE_NOT_IMPLEMENTED;
4043 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4044 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4045 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4047 for (i = 0; i < num_sensors; i++) {
4048 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
4049 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4050 IXGBE_ETS_DATA_INDEX_SHIFT);
4051 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4052 IXGBE_ETS_DATA_LOC_SHIFT);
4053 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4055 hw->phy.ops.write_i2c_byte(hw,
4056 ixgbe_emc_therm_limit[sensor_index],
4057 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4059 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4060 data->sensor[i].location = sensor_location;
4061 data->sensor[i].caution_thresh = therm_limit;
4062 data->sensor[i].max_op_thresh = therm_limit -