1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015 Cavium, Inc
3 * Copyright(c) 2020 Arm Limited
6 #ifndef _RTE_ATOMIC_ARM64_H_
7 #define _RTE_ATOMIC_ARM64_H_
9 #ifndef RTE_FORCE_INTRINSICS
10 # error Platform must be built with RTE_FORCE_INTRINSICS
17 #include "generic/rte_atomic.h"
18 #include <rte_branch_prediction.h>
19 #include <rte_compat.h>
20 #include <rte_debug.h>
22 #define rte_mb() asm volatile("dmb osh" : : : "memory")
24 #define rte_wmb() asm volatile("dmb oshst" : : : "memory")
26 #define rte_rmb() asm volatile("dmb oshld" : : : "memory")
28 #define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
30 #define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
32 #define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
34 #define rte_io_mb() rte_mb()
36 #define rte_io_wmb() rte_wmb()
38 #define rte_io_rmb() rte_rmb()
40 static __rte_always_inline void
41 rte_atomic_thread_fence(int memorder)
43 __atomic_thread_fence(memorder);
46 /*------------------------ 128 bit atomic operations -------------------------*/
48 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
50 #if defined(RTE_CC_CLANG)
51 #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \
52 static __rte_noinline void \
53 cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \
55 /* caspX instructions register pair must start from even-numbered
56 * register at operand 1.
57 * So, specify registers for local variables here.
59 register uint64_t x0 __asm("x0") = (uint64_t)old->val[0]; \
60 register uint64_t x1 __asm("x1") = (uint64_t)old->val[1]; \
61 register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0]; \
62 register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1]; \
64 ".arch armv8-a+lse\n" \
65 op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \
76 #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \
77 static __rte_always_inline void \
78 cas_op_name(rte_int128_t *dst, rte_int128_t *old, rte_int128_t updated) \
81 op_string " %[old], %H[old], %[upd], %H[upd], [%[dst]]" \
82 : [old] "+r"(old->int128) \
83 : [upd] "r"(updated.int128), [dst] "r"(dst) \
88 __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp")
89 __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
90 __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
91 __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
93 #undef __ATOMIC128_CAS_OP
99 rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
100 const rte_int128_t *src, unsigned int weak, int success,
103 /* Always do strong CAS */
105 /* Ignore memory ordering for failure, memory order for
106 * success must be stronger or equal
108 RTE_SET_USED(failure);
109 /* Find invalid memory order */
110 RTE_ASSERT(success == __ATOMIC_RELAXED ||
111 success == __ATOMIC_ACQUIRE ||
112 success == __ATOMIC_RELEASE ||
113 success == __ATOMIC_ACQ_REL ||
114 success == __ATOMIC_SEQ_CST);
116 rte_int128_t expected = *exp;
117 rte_int128_t desired = *src;
120 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
121 if (success == __ATOMIC_RELAXED)
122 __cas_128_relaxed(dst, exp, desired);
123 else if (success == __ATOMIC_ACQUIRE)
124 __cas_128_acquire(dst, exp, desired);
125 else if (success == __ATOMIC_RELEASE)
126 __cas_128_release(dst, exp, desired);
128 __cas_128_acq_rel(dst, exp, desired);
131 #define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) != __ATOMIC_RELEASE)
132 #define __HAS_RLS(mo) ((mo) == __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
133 (mo) == __ATOMIC_SEQ_CST)
135 int ldx_mo = __HAS_ACQ(success) ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED;
136 int stx_mo = __HAS_RLS(success) ? __ATOMIC_RELEASE : __ATOMIC_RELAXED;
143 /* ldx128 can not guarantee atomic,
144 * Must write back src or old to verify atomicity of ldx128;
148 #define __LOAD_128(op_string, src, dst) { \
150 op_string " %0, %1, %2" \
151 : "=&r" (dst.val[0]), \
153 : "Q" (src->val[0]) \
156 if (ldx_mo == __ATOMIC_RELAXED)
157 __LOAD_128("ldxp", dst, old)
159 __LOAD_128("ldaxp", dst, old)
163 #define __STORE_128(op_string, dst, src, ret) { \
165 op_string " %w0, %1, %2, %3" \
167 : "r" (src.val[0]), \
172 if (likely(old.int128 == expected.int128)) {
173 if (stx_mo == __ATOMIC_RELAXED)
174 __STORE_128("stxp", dst, desired, ret)
176 __STORE_128("stlxp", dst, desired, ret)
178 /* In the failure case (since 'weak' is ignored and only
179 * weak == 0 is implemented), expected should contain
180 * the atomically read value of dst. This means, 'old'
181 * needs to be stored back to ensure it was read
184 if (stx_mo == __ATOMIC_RELAXED)
185 __STORE_128("stxp", dst, old, ret)
187 __STORE_128("stlxp", dst, old, ret)
192 } while (unlikely(ret));
194 /* Unconditionally updating the value of exp removes an 'if' statement.
195 * The value of exp should already be in register if not in the cache.
200 return (old.int128 == expected.int128);
207 #endif /* _RTE_ATOMIC_ARM64_H_ */