1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2016 Cavium, Inc
10 * I/O device memory operations
12 * This file defines the generic API for I/O device memory read/write operations
16 #include <rte_common.h>
17 #include <rte_compat.h>
18 #include <rte_atomic.h>
23 * Read a 8-bit value from I/O device memory address *addr*.
25 * The relaxed version does not have additional I/O memory barrier, useful in
26 * accessing the device registers of integrated controllers which implicitly
27 * strongly ordered with respect to memory access.
30 * I/O memory address to read the value from
35 rte_read8_relaxed(const volatile void *addr);
38 * Read a 16-bit value from I/O device memory address *addr*.
40 * The relaxed version does not have additional I/O memory barrier, useful in
41 * accessing the device registers of integrated controllers which implicitly
42 * strongly ordered with respect to memory access.
45 * I/O memory address to read the value from
49 static inline uint16_t
50 rte_read16_relaxed(const volatile void *addr);
53 * Read a 32-bit value from I/O device memory address *addr*.
55 * The relaxed version does not have additional I/O memory barrier, useful in
56 * accessing the device registers of integrated controllers which implicitly
57 * strongly ordered with respect to memory access.
60 * I/O memory address to read the value from
64 static inline uint32_t
65 rte_read32_relaxed(const volatile void *addr);
68 * Read a 64-bit value from I/O device memory address *addr*.
70 * The relaxed version does not have additional I/O memory barrier, useful in
71 * accessing the device registers of integrated controllers which implicitly
72 * strongly ordered with respect to memory access.
75 * I/O memory address to read the value from
79 static inline uint64_t
80 rte_read64_relaxed(const volatile void *addr);
83 * Write a 8-bit value to I/O device memory address *addr*.
85 * The relaxed version does not have additional I/O memory barrier, useful in
86 * accessing the device registers of integrated controllers which implicitly
87 * strongly ordered with respect to memory access.
92 * I/O memory address to write the value to
96 rte_write8_relaxed(uint8_t value, volatile void *addr);
99 * Write a 16-bit value to I/O device memory address *addr*.
101 * The relaxed version does not have additional I/O memory barrier, useful in
102 * accessing the device registers of integrated controllers which implicitly
103 * strongly ordered with respect to memory access.
108 * I/O memory address to write the value to
111 rte_write16_relaxed(uint16_t value, volatile void *addr);
114 * Write a 32-bit value to I/O device memory address *addr*.
116 * The relaxed version does not have additional I/O memory barrier, useful in
117 * accessing the device registers of integrated controllers which implicitly
118 * strongly ordered with respect to memory access.
123 * I/O memory address to write the value to
126 rte_write32_relaxed(uint32_t value, volatile void *addr);
129 * Write a 64-bit value to I/O device memory address *addr*.
131 * The relaxed version does not have additional I/O memory barrier, useful in
132 * accessing the device registers of integrated controllers which implicitly
133 * strongly ordered with respect to memory access.
138 * I/O memory address to write the value to
141 rte_write64_relaxed(uint64_t value, volatile void *addr);
144 * Read a 8-bit value from I/O device memory address *addr*.
147 * I/O memory address to read the value from
151 static inline uint8_t
152 rte_read8(const volatile void *addr);
155 * Read a 16-bit value from I/O device memory address *addr*.
159 * I/O memory address to read the value from
163 static inline uint16_t
164 rte_read16(const volatile void *addr);
167 * Read a 32-bit value from I/O device memory address *addr*.
170 * I/O memory address to read the value from
174 static inline uint32_t
175 rte_read32(const volatile void *addr);
178 * Read a 64-bit value from I/O device memory address *addr*.
181 * I/O memory address to read the value from
185 static inline uint64_t
186 rte_read64(const volatile void *addr);
189 * Write a 8-bit value to I/O device memory address *addr*.
194 * I/O memory address to write the value to
198 rte_write8(uint8_t value, volatile void *addr);
201 * Write a 16-bit value to I/O device memory address *addr*.
206 * I/O memory address to write the value to
209 rte_write16(uint16_t value, volatile void *addr);
212 * Write a 32-bit value to I/O device memory address *addr*.
217 * I/O memory address to write the value to
220 rte_write32(uint32_t value, volatile void *addr);
223 * Write a 64-bit value to I/O device memory address *addr*.
228 * I/O memory address to write the value to
231 rte_write64(uint64_t value, volatile void *addr);
234 * Write a 32-bit value to I/O device memory address addr using write
235 * combining memory write protocol. Depending on the platform write combining
236 * may not be available and/or may be treated as a hint and the behavior may
237 * fallback to a regular store.
242 * I/O memory address to write the value to
246 rte_write32_wc(uint32_t value, volatile void *addr);
249 * Write a 32-bit value to I/O device memory address addr using write
250 * combining memory write protocol. Depending on the platform write combining
251 * may not be available and/or may be treated as a hint and the behavior may
252 * fallback to a regular store.
254 * The relaxed version does not have additional I/O memory barrier, useful in
255 * accessing the device registers of integrated controllers which implicitly
256 * strongly ordered with respect to memory access.
261 * I/O memory address to write the value to
265 rte_write32_wc_relaxed(uint32_t value, volatile void *addr);
267 #endif /* __DOXYGEN__ */
269 #ifndef RTE_OVERRIDE_IO_H
271 static __rte_always_inline uint8_t
272 rte_read8_relaxed(const volatile void *addr)
274 return *(const volatile uint8_t *)addr;
277 static __rte_always_inline uint16_t
278 rte_read16_relaxed(const volatile void *addr)
280 return *(const volatile uint16_t *)addr;
283 static __rte_always_inline uint32_t
284 rte_read32_relaxed(const volatile void *addr)
286 return *(const volatile uint32_t *)addr;
289 static __rte_always_inline uint64_t
290 rte_read64_relaxed(const volatile void *addr)
292 return *(const volatile uint64_t *)addr;
295 static __rte_always_inline void
296 rte_write8_relaxed(uint8_t value, volatile void *addr)
298 *(volatile uint8_t *)addr = value;
301 static __rte_always_inline void
302 rte_write16_relaxed(uint16_t value, volatile void *addr)
304 *(volatile uint16_t *)addr = value;
307 static __rte_always_inline void
308 rte_write32_relaxed(uint32_t value, volatile void *addr)
310 *(volatile uint32_t *)addr = value;
313 static __rte_always_inline void
314 rte_write64_relaxed(uint64_t value, volatile void *addr)
316 *(volatile uint64_t *)addr = value;
319 static __rte_always_inline uint8_t
320 rte_read8(const volatile void *addr)
323 val = rte_read8_relaxed(addr);
328 static __rte_always_inline uint16_t
329 rte_read16(const volatile void *addr)
332 val = rte_read16_relaxed(addr);
337 static __rte_always_inline uint32_t
338 rte_read32(const volatile void *addr)
341 val = rte_read32_relaxed(addr);
346 static __rte_always_inline uint64_t
347 rte_read64(const volatile void *addr)
350 val = rte_read64_relaxed(addr);
355 static __rte_always_inline void
356 rte_write8(uint8_t value, volatile void *addr)
359 rte_write8_relaxed(value, addr);
362 static __rte_always_inline void
363 rte_write16(uint16_t value, volatile void *addr)
366 rte_write16_relaxed(value, addr);
369 static __rte_always_inline void
370 rte_write32(uint32_t value, volatile void *addr)
373 rte_write32_relaxed(value, addr);
376 static __rte_always_inline void
377 rte_write64(uint64_t value, volatile void *addr)
380 rte_write64_relaxed(value, addr);
383 #ifndef RTE_NATIVE_WRITE32_WC
384 static __rte_always_inline void
385 rte_write32_wc(uint32_t value, volatile void *addr)
387 rte_write32(value, addr);
390 static __rte_always_inline void
391 rte_write32_wc_relaxed(uint32_t value, volatile void *addr)
393 rte_write32_relaxed(value, addr);
395 #endif /* RTE_NATIVE_WRITE32_WC */
397 #endif /* RTE_OVERRIDE_IO_H */
399 #endif /* _RTE_IO_H_ */