1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020 Intel Corporation
5 #ifndef _RTE_POWER_INTRINSIC_H_
6 #define _RTE_POWER_INTRINSIC_H_
10 #include <rte_compat.h>
11 #include <rte_spinlock.h>
15 * Advanced power management operations.
17 * This file define APIs for advanced power management,
18 * which are architecture-dependent.
21 /** Size of the opaque data in monitor condition */
22 #define RTE_POWER_MONITOR_OPAQUE_SZ 4
25 * Callback definition for monitoring conditions. Callbacks with this signature
26 * will be used by `rte_power_monitor()` to check if the entering of power
27 * optimized state should be aborted.
30 * The value read from memory.
32 * Callback-specific data.
35 * 0 if entering of power optimized state should proceed
36 * -1 if entering of power optimized state should be aborted
38 typedef int (*rte_power_monitor_clb_t)(const uint64_t val,
39 const uint64_t opaque[RTE_POWER_MONITOR_OPAQUE_SZ]);
41 struct rte_power_monitor_cond {
42 volatile void *addr; /**< Address to monitor for changes */
43 uint8_t size; /**< Data size (in bytes) that will be read from the
44 * monitored memory location (`addr`). Can be 1, 2,
45 * 4, or 8. Supplying any other value will result in
48 rte_power_monitor_clb_t fn; /**< Callback to be used to check if
49 * entering power optimized state should
52 uint64_t opaque[RTE_POWER_MONITOR_OPAQUE_SZ];
53 /**< Callback-specific data */
58 * @b EXPERIMENTAL: this API may change without prior notice.
60 * Monitor specific address for changes. This will cause the CPU to enter an
61 * architecture-defined optimized power state until either the specified
62 * memory address is written to, a certain TSC timestamp is reached, or other
63 * reasons cause the CPU to wake up.
65 * Additionally, an expected value (`pmc->val`), mask (`pmc->mask`), and data
66 * size (`pmc->size`) are provided in the `pmc` power monitoring condition. If
67 * the mask is non-zero, the current value pointed to by the `pmc->addr` pointer
68 * will be read and compared against the expected value, and if they match, the
69 * entering of optimized power state will be aborted. This is intended to
70 * prevent the CPU from entering optimized power state and waiting on a write
71 * that has already happened by the time this API is called.
73 * @warning It is responsibility of the user to check if this function is
74 * supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
77 * The monitoring condition structure.
78 * @param tsc_timestamp
79 * Maximum TSC timestamp to wait for. Note that the wait behavior is
80 * architecture-dependent.
84 * -EINVAL on invalid parameters
85 * -ENOTSUP if unsupported
88 int rte_power_monitor(const struct rte_power_monitor_cond *pmc,
89 const uint64_t tsc_timestamp);
93 * @b EXPERIMENTAL: this API may change without prior notice.
95 * Wake up a specific lcore that is in a power optimized state and is monitoring
98 * @note It is safe to call this function if the lcore in question is not
99 * sleeping. The function will have no effect.
101 * @note This function will *not* wake up a core that is in a power optimized
102 * state due to calling `rte_power_pause`.
105 * Lcore ID of a sleeping thread.
108 int rte_power_monitor_wakeup(const unsigned int lcore_id);
112 * @b EXPERIMENTAL: this API may change without prior notice.
114 * Enter an architecture-defined optimized power state until a certain TSC
115 * timestamp is reached.
117 * @warning It is responsibility of the user to check if this function is
118 * supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
120 * @param tsc_timestamp
121 * Maximum TSC timestamp to wait for. Note that the wait behavior is
122 * architecture-dependent.
126 * -EINVAL on invalid parameters
127 * -ENOTSUP if unsupported
130 int rte_power_pause(const uint64_t tsc_timestamp);
134 * @b EXPERIMENTAL: this API may change without prior notice
136 * Monitor a set of addresses for changes. This will cause the CPU to enter an
137 * architecture-defined optimized power state until either one of the specified
138 * memory addresses is written to, a certain TSC timestamp is reached, or other
139 * reasons cause the CPU to wake up.
141 * Additionally, `expected` 64-bit values and 64-bit masks are provided. If
142 * mask is non-zero, the current value pointed to by the `p` pointer will be
143 * checked against the expected value, and if they do not match, the entering of
144 * optimized power state may be aborted.
146 * @warning It is responsibility of the user to check if this function is
147 * supported at runtime using `rte_cpu_get_intrinsics_support()` API call.
148 * Failing to do so may result in an illegal CPU instruction error.
151 * An array of monitoring condition structures.
153 * Length of the `pmc` array.
154 * @param tsc_timestamp
155 * Maximum TSC timestamp to wait for. Note that the wait behavior is
156 * architecture-dependent.
160 * -EINVAL on invalid parameters
161 * -ENOTSUP if unsupported
164 int rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
165 const uint32_t num, const uint64_t tsc_timestamp);
167 #endif /* _RTE_POWER_INTRINSIC_H_ */