1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
5 #ifndef _RTE_PREFETCH_H_
6 #define _RTE_PREFETCH_H_
8 #include <rte_compat.h>
13 * Prefetch operations.
15 * This file defines an API for prefetch macros / inline-functions,
16 * which are architecture-dependent. Prefetching occurs when a
17 * processor requests an instruction or data from memory to cache
18 * before it is actually needed, potentially speeding up the execution of the
23 * Prefetch a cache line into all cache levels.
27 static inline void rte_prefetch0(const volatile void *p);
30 * Prefetch a cache line into all cache levels except the 0th cache level.
34 static inline void rte_prefetch1(const volatile void *p);
37 * Prefetch a cache line into all cache levels except the 0th and 1th cache
42 static inline void rte_prefetch2(const volatile void *p);
45 * Prefetch a cache line into all cache levels (non-temporal/transient version)
47 * The non-temporal prefetch is intended as a prefetch hint that processor will
48 * use the prefetched data only once or short period, unlike the
49 * rte_prefetch0() function which imply that prefetched data to use repeatedly.
54 static inline void rte_prefetch_non_temporal(const volatile void *p);
58 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
60 * Prefetch a cache line into all cache levels, with intention to write. This
61 * prefetch variant hints to the CPU that the program is expecting to write to
62 * the cache line being prefetched.
64 * @param p Address to prefetch
68 rte_prefetch0_write(const void *p)
70 /* 1 indicates intention to write, 3 sets target cache level to L1. See
71 * GCC docs where these integer constants are described in more detail:
72 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
74 __builtin_prefetch(p, 1, 3);
79 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
81 * Prefetch a cache line into all cache levels, except the 0th, with intention
82 * to write. This prefetch variant hints to the CPU that the program is
83 * expecting to write to the cache line being prefetched.
85 * @param p Address to prefetch
89 rte_prefetch1_write(const void *p)
91 /* 1 indicates intention to write, 2 sets target cache level to L2. See
92 * GCC docs where these integer constants are described in more detail:
93 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
95 __builtin_prefetch(p, 1, 2);
100 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
102 * Prefetch a cache line into all cache levels, except the 0th and 1st, with
103 * intention to write. This prefetch variant hints to the CPU that the program
104 * is expecting to write to the cache line being prefetched.
106 * @param p Address to prefetch
110 rte_prefetch2_write(const void *p)
112 /* 1 indicates intention to write, 1 sets target cache level to L3. See
113 * GCC docs where these integer constants are described in more detail:
114 * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
116 __builtin_prefetch(p, 1, 1);
121 * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
123 * Demote a cache line to a more distant level of cache from the processor.
124 * CLDEMOTE hints to hardware to move (demote) a cache line from the closest to
125 * the processor to a level more distant from the processor. It is a hint and
126 * not guaranteed. rte_cldemote is intended to move the cache line to the more
127 * remote cache, where it expects sharing to be efficient and to indicate that
128 * a line may be accessed by a different core in the future.
135 rte_cldemote(const volatile void *p);
137 #endif /* _RTE_PREFETCH_H_ */