1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2022 Intel Corporation
3 * SFF-8636 standards based QSFP EEPROM Field Definitions
9 /*------------------------------------------------------------------------------
11 * QSFP EEPROM data structures
13 * register info from SFF-8636 Rev 2.7
16 /*------------------------------------------------------------------------------
18 * Lower Memory Page 00h
19 * Measurement, Diagnostic and Control Functions
23 /* Values are defined under SFF_8024_ID_OFFSET */
24 #define SFF_8636_ID_OFFSET 0x00
26 #define SFF_8636_REV_COMPLIANCE_OFFSET 0x01
27 #define SFF_8636_REV_UNSPECIFIED 0x00
28 #define SFF_8636_REV_8436_48 0x01
29 #define SFF_8636_REV_8436_8636 0x02
30 #define SFF_8636_REV_8636_13 0x03
31 #define SFF_8636_REV_8636_14 0x04
32 #define SFF_8636_REV_8636_15 0x05
33 #define SFF_8636_REV_8636_20 0x06
34 #define SFF_8636_REV_8636_27 0x07
36 #define SFF_8636_STATUS_2_OFFSET 0x02
37 /* Flat Memory:0- Paging, 1- Page 0 only */
38 #define SFF_8636_STATUS_PAGE_3_PRESENT RTE_BIT32(2)
39 #define SFF_8636_STATUS_INTL_OUTPUT RTE_BIT32(1)
40 #define SFF_8636_STATUS_DATA_NOT_READY RTE_BIT32(0)
42 /* Channel Status Interrupt Flags - 3-5 */
43 #define SFF_8636_LOS_AW_OFFSET 0x03
44 #define SFF_8636_TX4_LOS_AW RTE_BIT32(7)
45 #define SFF_8636_TX3_LOS_AW RTE_BIT32(6)
46 #define SFF_8636_TX2_LOS_AW RTE_BIT32(5)
47 #define SFF_8636_TX1_LOS_AW RTE_BIT32(4)
48 #define SFF_8636_RX4_LOS_AW RTE_BIT32(3)
49 #define SFF_8636_RX3_LOS_AW RTE_BIT32(2)
50 #define SFF_8636_RX2_LOS_AW RTE_BIT32(1)
51 #define SFF_8636_RX1_LOS_AW RTE_BIT32(0)
53 #define SFF_8636_FAULT_AW_OFFSET 0x04
54 #define SFF_8636_TX4_FAULT_AW RTE_BIT32(3)
55 #define SFF_8636_TX3_FAULT_AW RTE_BIT32(2)
56 #define SFF_8636_TX2_FAULT_AW RTE_BIT32(1)
57 #define SFF_8636_TX1_FAULT_AW RTE_BIT32(0)
59 /* Module Monitor Interrupt Flags - 6-8 */
60 #define SFF_8636_TEMP_AW_OFFSET 0x06
61 #define SFF_8636_TEMP_HALARM_STATUS RTE_BIT32(7)
62 #define SFF_8636_TEMP_LALARM_STATUS RTE_BIT32(6)
63 #define SFF_8636_TEMP_HWARN_STATUS RTE_BIT32(5)
64 #define SFF_8636_TEMP_LWARN_STATUS RTE_BIT32(4)
66 #define SFF_8636_VCC_AW_OFFSET 0x07
67 #define SFF_8636_VCC_HALARM_STATUS RTE_BIT32(7)
68 #define SFF_8636_VCC_LALARM_STATUS RTE_BIT32(6)
69 #define SFF_8636_VCC_HWARN_STATUS RTE_BIT32(5)
70 #define SFF_8636_VCC_LWARN_STATUS RTE_BIT32(4)
72 /* Channel Monitor Interrupt Flags - 9-21 */
73 #define SFF_8636_RX_PWR_12_AW_OFFSET 0x09
74 #define SFF_8636_RX_PWR_1_HALARM RTE_BIT32(7)
75 #define SFF_8636_RX_PWR_1_LALARM RTE_BIT32(6)
76 #define SFF_8636_RX_PWR_1_HWARN RTE_BIT32(5)
77 #define SFF_8636_RX_PWR_1_LWARN RTE_BIT32(4)
78 #define SFF_8636_RX_PWR_2_HALARM RTE_BIT32(3)
79 #define SFF_8636_RX_PWR_2_LALARM RTE_BIT32(2)
80 #define SFF_8636_RX_PWR_2_HWARN RTE_BIT32(1)
81 #define SFF_8636_RX_PWR_2_LWARN RTE_BIT32(0)
83 #define SFF_8636_RX_PWR_34_AW_OFFSET 0x0A
84 #define SFF_8636_RX_PWR_3_HALARM RTE_BIT32(7)
85 #define SFF_8636_RX_PWR_3_LALARM RTE_BIT32(6)
86 #define SFF_8636_RX_PWR_3_HWARN RTE_BIT32(5)
87 #define SFF_8636_RX_PWR_3_LWARN RTE_BIT32(4)
88 #define SFF_8636_RX_PWR_4_HALARM RTE_BIT32(3)
89 #define SFF_8636_RX_PWR_4_LALARM RTE_BIT32(2)
90 #define SFF_8636_RX_PWR_4_HWARN RTE_BIT32(1)
91 #define SFF_8636_RX_PWR_4_LWARN RTE_BIT32(0)
93 #define SFF_8636_TX_BIAS_12_AW_OFFSET 0x0B
94 #define SFF_8636_TX_BIAS_1_HALARM RTE_BIT32(7)
95 #define SFF_8636_TX_BIAS_1_LALARM RTE_BIT32(6)
96 #define SFF_8636_TX_BIAS_1_HWARN RTE_BIT32(5)
97 #define SFF_8636_TX_BIAS_1_LWARN RTE_BIT32(4)
98 #define SFF_8636_TX_BIAS_2_HALARM RTE_BIT32(3)
99 #define SFF_8636_TX_BIAS_2_LALARM RTE_BIT32(2)
100 #define SFF_8636_TX_BIAS_2_HWARN RTE_BIT32(1)
101 #define SFF_8636_TX_BIAS_2_LWARN RTE_BIT32(0)
103 #define SFF_8636_TX_BIAS_34_AW_OFFSET 0xC
104 #define SFF_8636_TX_BIAS_3_HALARM RTE_BIT32(7)
105 #define SFF_8636_TX_BIAS_3_LALARM RTE_BIT32(6)
106 #define SFF_8636_TX_BIAS_3_HWARN RTE_BIT32(5)
107 #define SFF_8636_TX_BIAS_3_LWARN RTE_BIT32(4)
108 #define SFF_8636_TX_BIAS_4_HALARM RTE_BIT32(3)
109 #define SFF_8636_TX_BIAS_4_LALARM RTE_BIT32(2)
110 #define SFF_8636_TX_BIAS_4_HWARN RTE_BIT32(1)
111 #define SFF_8636_TX_BIAS_4_LWARN RTE_BIT32(0)
113 #define SFF_8636_TX_PWR_12_AW_OFFSET 0x0D
114 #define SFF_8636_TX_PWR_1_HALARM RTE_BIT32(7)
115 #define SFF_8636_TX_PWR_1_LALARM RTE_BIT32(6)
116 #define SFF_8636_TX_PWR_1_HWARN RTE_BIT32(5)
117 #define SFF_8636_TX_PWR_1_LWARN RTE_BIT32(4)
118 #define SFF_8636_TX_PWR_2_HALARM RTE_BIT32(3)
119 #define SFF_8636_TX_PWR_2_LALARM RTE_BIT32(2)
120 #define SFF_8636_TX_PWR_2_HWARN RTE_BIT32(1)
121 #define SFF_8636_TX_PWR_2_LWARN RTE_BIT32(0)
123 #define SFF_8636_TX_PWR_34_AW_OFFSET 0x0E
124 #define SFF_8636_TX_PWR_3_HALARM RTE_BIT32(7)
125 #define SFF_8636_TX_PWR_3_LALARM RTE_BIT32(6)
126 #define SFF_8636_TX_PWR_3_HWARN RTE_BIT32(5)
127 #define SFF_8636_TX_PWR_3_LWARN RTE_BIT32(4)
128 #define SFF_8636_TX_PWR_4_HALARM RTE_BIT32(3)
129 #define SFF_8636_TX_PWR_4_LALARM RTE_BIT32(2)
130 #define SFF_8636_TX_PWR_4_HWARN RTE_BIT32(1)
131 #define SFF_8636_TX_PWR_4_LWARN RTE_BIT32(0)
133 /* Module Monitoring Values - 22-33 */
134 #define SFF_8636_TEMP_CURR 0x16
135 #define SFF_8636_TEMP_MSB_OFFSET 0x16
136 #define SFF_8636_TEMP_LSB_OFFSET 0x17
138 #define SFF_8636_VCC_CURR 0x1A
139 #define SFF_8636_VCC_MSB_OFFSET 0x1A
140 #define SFF_8636_VCC_LSB_OFFSET 0x1B
142 /* Channel Monitoring Values - 34-81 */
143 #define SFF_8636_RX_PWR_1_OFFSET 0x22
144 #define SFF_8636_RX_PWR_2_OFFSET 0x24
145 #define SFF_8636_RX_PWR_3_OFFSET 0x26
146 #define SFF_8636_RX_PWR_4_OFFSET 0x28
148 #define SFF_8636_TX_BIAS_1_OFFSET 0x2A
149 #define SFF_8636_TX_BIAS_2_OFFSET 0x2C
150 #define SFF_8636_TX_BIAS_3_OFFSET 0x2E
151 #define SFF_8636_TX_BIAS_4_OFFSET 0x30
153 #define SFF_8636_TX_PWR_1_OFFSET 0x32
154 #define SFF_8636_TX_PWR_2_OFFSET 0x34
155 #define SFF_8636_TX_PWR_3_OFFSET 0x36
156 #define SFF_8636_TX_PWR_4_OFFSET 0x38
158 /* Control Bytes - 86 - 99 */
159 #define SFF_8636_TX_DISABLE_OFFSET 0x56
160 #define SFF_8636_TX_DISABLE_4 RTE_BIT32(3)
161 #define SFF_8636_TX_DISABLE_3 RTE_BIT32(2)
162 #define SFF_8636_TX_DISABLE_2 RTE_BIT32(1)
163 #define SFF_8636_TX_DISABLE_1 RTE_BIT32(0)
165 #define SFF_8636_RX_RATE_SELECT_OFFSET 0x57
166 #define SFF_8636_RX_RATE_SELECT_4_MASK (3 << 6)
167 #define SFF_8636_RX_RATE_SELECT_3_MASK (3 << 4)
168 #define SFF_8636_RX_RATE_SELECT_2_MASK (3 << 2)
169 #define SFF_8636_RX_RATE_SELECT_1_MASK (3 << 0)
171 #define SFF_8636_TX_RATE_SELECT_OFFSET 0x58
172 #define SFF_8636_TX_RATE_SELECT_4_MASK (3 << 6)
173 #define SFF_8636_TX_RATE_SELECT_3_MASK (3 << 4)
174 #define SFF_8636_TX_RATE_SELECT_2_MASK (3 << 2)
175 #define SFF_8636_TX_RATE_SELECT_1_MASK (3 << 0)
177 #define SFF_8636_RX_APP_SELECT_4_OFFSET 0x58
178 #define SFF_8636_RX_APP_SELECT_3_OFFSET 0x59
179 #define SFF_8636_RX_APP_SELECT_2_OFFSET 0x5A
180 #define SFF_8636_RX_APP_SELECT_1_OFFSET 0x5B
182 #define SFF_8636_PWR_MODE_OFFSET 0x5D
183 #define SFF_8636_HIGH_PWR_ENABLE RTE_BIT32(2)
184 #define SFF_8636_LOW_PWR_MODE RTE_BIT32(1)
185 #define SFF_8636_PWR_OVERRIDE RTE_BIT32(0)
187 #define SFF_8636_TX_APP_SELECT_4_OFFSET 0x5E
188 #define SFF_8636_TX_APP_SELECT_3_OFFSET 0x5F
189 #define SFF_8636_TX_APP_SELECT_2_OFFSET 0x60
190 #define SFF_8636_TX_APP_SELECT_1_OFFSET 0x61
192 #define SFF_8636_LOS_MASK_OFFSET 0x64
193 #define SFF_8636_TX_LOS_4_MASK RTE_BIT32(7)
194 #define SFF_8636_TX_LOS_3_MASK RTE_BIT32(6)
195 #define SFF_8636_TX_LOS_2_MASK RTE_BIT32(5)
196 #define SFF_8636_TX_LOS_1_MASK RTE_BIT32(4)
197 #define SFF_8636_RX_LOS_4_MASK RTE_BIT32(3)
198 #define SFF_8636_RX_LOS_3_MASK RTE_BIT32(2)
199 #define SFF_8636_RX_LOS_2_MASK RTE_BIT32(1)
200 #define SFF_8636_RX_LOS_1_MASK RTE_BIT32(0)
202 #define SFF_8636_FAULT_MASK_OFFSET 0x65
203 #define SFF_8636_TX_FAULT_1_MASK RTE_BIT32(3)
204 #define SFF_8636_TX_FAULT_2_MASK RTE_BIT32(2)
205 #define SFF_8636_TX_FAULT_3_MASK RTE_BIT32(1)
206 #define SFF_8636_TX_FAULT_4_MASK RTE_BIT32(0)
208 #define SFF_8636_TEMP_MASK_OFFSET 0x67
209 #define SFF_8636_TEMP_HALARM_MASK RTE_BIT32(7)
210 #define SFF_8636_TEMP_LALARM_MASK RTE_BIT32(6)
211 #define SFF_8636_TEMP_HWARN_MASK RTE_BIT32(5)
212 #define SFF_8636_TEMP_LWARN_MASK RTE_BIT32(4)
214 #define SFF_8636_VCC_MASK_OFFSET 0x68
215 #define SFF_8636_VCC_HALARM_MASK RTE_BIT32(7)
216 #define SFF_8636_VCC_LALARM_MASK RTE_BIT32(6)
217 #define SFF_8636_VCC_HWARN_MASK RTE_BIT32(5)
218 #define SFF_8636_VCC_LWARN_MASK RTE_BIT32(4)
220 /*------------------------------------------------------------------------------
222 * Upper Memory Page 00h
223 * Serial ID - Base ID, Extended ID and Vendor Specific ID fields
226 /* Identifier - 128 */
227 /* Identifier values same as Lower Memory Page 00h */
228 #define SFF_8636_UPPER_PAGE_0_ID_OFFSET 0x80
230 /* Extended Identifier - 128 */
231 #define SFF_8636_EXT_ID_OFFSET 0x81
232 #define SFF_8636_EXT_ID_PWR_CLASS_MASK 0xC0
233 #define SFF_8636_EXT_ID_PWR_CLASS_1 (0 << 6)
234 #define SFF_8636_EXT_ID_PWR_CLASS_2 (1 << 6)
235 #define SFF_8636_EXT_ID_PWR_CLASS_3 (2 << 6)
236 #define SFF_8636_EXT_ID_PWR_CLASS_4 (3 << 6)
237 #define SFF_8636_EXT_ID_CLIE_MASK 0x10
238 #define SFF_8636_EXT_ID_CLIEI_CODE_PRESENT (1 << 4)
239 #define SFF_8636_EXT_ID_CDR_TX_MASK 0x08
240 #define SFF_8636_EXT_ID_CDR_TX_PRESENT (1 << 3)
241 #define SFF_8636_EXT_ID_CDR_RX_MASK 0x04
242 #define SFF_8636_EXT_ID_CDR_RX_PRESENT (1 << 2)
243 #define SFF_8636_EXT_ID_EPWR_CLASS_MASK 0x03
244 #define SFF_8636_EXT_ID_PWR_CLASS_LEGACY 0
245 #define SFF_8636_EXT_ID_PWR_CLASS_5 1
246 #define SFF_8636_EXT_ID_PWR_CLASS_6 2
247 #define SFF_8636_EXT_ID_PWR_CLASS_7 3
249 /* Connector Values offset - 130 */
250 /* Values are defined under SFF_8024_CTOR */
251 #define SFF_8636_CTOR_OFFSET 0x82
252 #define SFF_8636_CTOR_UNKNOWN 0x00
253 #define SFF_8636_CTOR_SC 0x01
254 #define SFF_8636_CTOR_FC_STYLE_1 0x02
255 #define SFF_8636_CTOR_FC_STYLE_2 0x03
256 #define SFF_8636_CTOR_BNC_TNC 0x04
257 #define SFF_8636_CTOR_FC_COAX 0x05
258 #define SFF_8636_CTOR_FIBER_JACK 0x06
259 #define SFF_8636_CTOR_LC 0x07
260 #define SFF_8636_CTOR_MT_RJ 0x08
261 #define SFF_8636_CTOR_MU 0x09
262 #define SFF_8636_CTOR_SG 0x0A
263 #define SFF_8636_CTOR_OPT_PT 0x0B
264 #define SFF_8636_CTOR_MPO 0x0C
265 /* 0D-1Fh --- Reserved */
266 #define SFF_8636_CTOR_HSDC_II 0x20
267 #define SFF_8636_CTOR_COPPER_PT 0x21
268 #define SFF_8636_CTOR_RJ45 0x22
269 #define SFF_8636_CTOR_NO_SEPARABLE 0x23
270 #define SFF_8636_CTOR_MXC_2X16 0x24
272 /* Specification Compliance - 131-138 */
273 /* Ethernet Compliance Codes - 131 */
274 #define SFF_8636_ETHERNET_COMP_OFFSET 0x83
275 #define SFF_8636_ETHERNET_RSRVD RTE_BIT32(7)
276 #define SFF_8636_ETHERNET_10G_LRM RTE_BIT32(6)
277 #define SFF_8636_ETHERNET_10G_LR RTE_BIT32(5)
278 #define SFF_8636_ETHERNET_10G_SR RTE_BIT32(4)
279 #define SFF_8636_ETHERNET_40G_CR4 RTE_BIT32(3)
280 #define SFF_8636_ETHERNET_40G_SR4 RTE_BIT32(2)
281 #define SFF_8636_ETHERNET_40G_LR4 RTE_BIT32(1)
282 #define SFF_8636_ETHERNET_40G_ACTIVE RTE_BIT32(0)
284 /* SONET Compliance Codes - 132 */
285 #define SFF_8636_SONET_COMP_OFFSET 0x84
286 #define SFF_8636_SONET_40G_OTN RTE_BIT32(3)
287 #define SFF_8636_SONET_OC48_LR RTE_BIT32(2)
288 #define SFF_8636_SONET_OC48_IR RTE_BIT32(1)
289 #define SFF_8636_SONET_OC48_SR RTE_BIT32(0)
291 /* SAS/SATA Complaince Codes - 133 */
292 #define SFF_8636_SAS_COMP_OFFSET 0x85
293 #define SFF_8636_SAS_12G RTE_BIT32(6)
294 #define SFF_8636_SAS_6G RTE_BIT32(5)
295 #define SFF_8636_SAS_3G RTE_BIT32(4)
297 /* Gigabit Ethernet Compliance Codes - 134 */
298 #define SFF_8636_GIGE_COMP_OFFSET 0x86
299 #define SFF_8636_GIGE_1000_BASE_T RTE_BIT32(3)
300 #define SFF_8636_GIGE_1000_BASE_CX RTE_BIT32(2)
301 #define SFF_8636_GIGE_1000_BASE_LX RTE_BIT32(1)
302 #define SFF_8636_GIGE_1000_BASE_SX RTE_BIT32(0)
304 /* Fibre Channel Link length/Transmitter Tech. - 135,136 */
305 #define SFF_8636_FC_LEN_OFFSET 0x87
306 #define SFF_8636_FC_LEN_VERY_LONG RTE_BIT32(7)
307 #define SFF_8636_FC_LEN_SHORT RTE_BIT32(6)
308 #define SFF_8636_FC_LEN_INT RTE_BIT32(5)
309 #define SFF_8636_FC_LEN_LONG RTE_BIT32(4)
310 #define SFF_8636_FC_LEN_MED RTE_BIT32(3)
311 #define SFF_8636_FC_TECH_LONG_LC RTE_BIT32(1)
312 #define SFF_8636_FC_TECH_ELEC_INTER RTE_BIT32(0)
314 #define SFF_8636_FC_TECH_OFFSET 0x88
315 #define SFF_8636_FC_TECH_ELEC_INTRA RTE_BIT32(7)
316 #define SFF_8636_FC_TECH_SHORT_WO_OFC RTE_BIT32(6)
317 #define SFF_8636_FC_TECH_SHORT_W_OFC RTE_BIT32(5)
318 #define SFF_8636_FC_TECH_LONG_LL RTE_BIT32(4)
320 /* Fibre Channel Transmitter Media - 137 */
321 #define SFF_8636_FC_TRANS_MEDIA_OFFSET 0x89
322 /* Twin Axial Pair */
323 #define SFF_8636_FC_TRANS_MEDIA_TW RTE_BIT32(7)
324 /* Shielded Twisted Pair */
325 #define SFF_8636_FC_TRANS_MEDIA_TP RTE_BIT32(6)
327 #define SFF_8636_FC_TRANS_MEDIA_MI RTE_BIT32(5)
329 #define SFF_8636_FC_TRANS_MEDIA_TV RTE_BIT32(4)
330 /* Multi-mode 62.5m */
331 #define SFF_8636_FC_TRANS_MEDIA_M6 RTE_BIT32(3)
333 #define SFF_8636_FC_TRANS_MEDIA_M5 RTE_BIT32(2)
334 /* Multi-mode 50um */
335 #define SFF_8636_FC_TRANS_MEDIA_OM3 RTE_BIT32(1)
337 #define SFF_8636_FC_TRANS_MEDIA_SM RTE_BIT32(0)
339 /* Fibre Channel Speed - 138 */
340 #define SFF_8636_FC_SPEED_OFFSET 0x8A
341 #define SFF_8636_FC_SPEED_1200_MBPS RTE_BIT32(7)
342 #define SFF_8636_FC_SPEED_800_MBPS RTE_BIT32(6)
343 #define SFF_8636_FC_SPEED_1600_MBPS RTE_BIT32(5)
344 #define SFF_8636_FC_SPEED_400_MBPS RTE_BIT32(4)
345 #define SFF_8636_FC_SPEED_200_MBPS RTE_BIT32(2)
346 #define SFF_8636_FC_SPEED_100_MBPS RTE_BIT32(0)
349 /* Values are defined under SFF_8024_ENCODING */
350 #define SFF_8636_ENCODING_OFFSET 0x8B
351 #define SFF_8636_ENCODING_MANCHESTER 0x06
352 #define SFF_8636_ENCODING_64B66B 0x05
353 #define SFF_8636_ENCODING_SONET 0x04
354 #define SFF_8636_ENCODING_NRZ 0x03
355 #define SFF_8636_ENCODING_4B5B 0x02
356 #define SFF_8636_ENCODING_8B10B 0x01
357 #define SFF_8636_ENCODING_UNSPEC 0x00
359 /* BR, Nominal - 140 */
360 #define SFF_8636_BR_NOMINAL_OFFSET 0x8C
362 /* Extended RateSelect - 141 */
363 #define SFF_8636_EXT_RS_OFFSET 0x8D
364 #define SFF_8636_EXT_RS_V1 RTE_BIT32(0)
366 /* Length (Standard SM Fiber)-km - 142 */
367 #define SFF_8636_SM_LEN_OFFSET 0x8E
369 /* Length (OM3)-Unit 2m - 143 */
370 #define SFF_8636_OM3_LEN_OFFSET 0x8F
372 /* Length (OM2)-Unit 1m - 144 */
373 #define SFF_8636_OM2_LEN_OFFSET 0x90
375 /* Length (OM1)-Unit 1m - 145 */
376 #define SFF_8636_OM1_LEN_OFFSET 0x91
378 /* Cable Assembly Length -Unit 1m - 146 */
379 #define SFF_8636_CBL_LEN_OFFSET 0x92
381 /* Device Technology - 147 */
382 #define SFF_8636_DEVICE_TECH_OFFSET 0x93
383 /* Transmitter Technology */
384 #define SFF_8636_TRANS_TECH_MASK 0xF0
385 /* Copper cable, linear active equalizers */
386 #define SFF_8636_TRANS_COPPER_LNR_EQUAL (15 << 4)
387 /* Copper cable, near end limiting active equalizers */
388 #define SFF_8636_TRANS_COPPER_NEAR_EQUAL (14 << 4)
389 /* Copper cable, far end limiting active equalizers */
390 #define SFF_8636_TRANS_COPPER_FAR_EQUAL (13 << 4)
391 /* Copper cable, near & far end limiting active equalizers */
392 #define SFF_8636_TRANS_COPPER_LNR_FAR_EQUAL (12 << 4)
393 /* Copper cable, passive equalized */
394 #define SFF_8636_TRANS_COPPER_PAS_EQUAL (11 << 4)
395 /* Copper cable, unequalized */
396 #define SFF_8636_TRANS_COPPER_PAS_UNEQUAL (10 << 4)
398 #define SFF_8636_TRANS_1490_DFB (9 << 4)
400 #define SFF_8636_TRANS_OTHERS (8 << 4)
402 #define SFF_8636_TRANS_1550_EML (7 << 4)
404 #define SFF_8636_TRANS_1310_EML (6 << 4)
406 #define SFF_8636_TRANS_1550_DFB (5 << 4)
408 #define SFF_8636_TRANS_1310_DFB (4 << 4)
410 #define SFF_8636_TRANS_1310_FP (3 << 4)
412 #define SFF_8636_TRANS_1550_VCSEL (2 << 4)
414 #define SFF_8636_TRANS_1310_VCSEL (1 << 4)
416 #define SFF_8636_TRANS_850_VCSEL (0 << 4)
418 /* Active/No wavelength control */
419 #define SFF_8636_DEV_TECH_ACTIVE_WAVE_LEN RTE_BIT32(3)
420 /* Cooled transmitter */
421 #define SFF_8636_DEV_TECH_COOL_TRANS RTE_BIT32(2)
422 /* APD/Pin Detector */
423 #define SFF_8636_DEV_TECH_APD_DETECTOR RTE_BIT32(1)
424 /* Transmitter tunable */
425 #define SFF_8636_DEV_TECH_TUNABLE RTE_BIT32(0)
427 /* Vendor Name - 148-163 */
428 #define SFF_8636_VENDOR_NAME_START_OFFSET 0x94
429 #define SFF_8636_VENDOR_NAME_END_OFFSET 0xA3
431 /* Extended Module Codes - 164 */
432 #define SFF_8636_EXT_MOD_CODE_OFFSET 0xA4
433 #define SFF_8636_EXT_MOD_INFINIBAND_EDR RTE_BIT32(4)
434 #define SFF_8636_EXT_MOD_INFINIBAND_FDR RTE_BIT32(3)
435 #define SFF_8636_EXT_MOD_INFINIBAND_QDR RTE_BIT32(2)
436 #define SFF_8636_EXT_MOD_INFINIBAND_DDR RTE_BIT32(1)
437 #define SFF_8636_EXT_MOD_INFINIBAND_SDR RTE_BIT32(0)
439 /* Vendor OUI - 165-167 */
440 #define SFF_8636_VENDOR_OUI_OFFSET 0xA5
441 #define SFF_8636_VENDOR_OUI_LEN 3
443 /* Vendor OUI - 165-167 */
444 #define SFF_8636_VENDOR_PN_START_OFFSET 0xA8
445 #define SFF_8636_VENDOR_PN_END_OFFSET 0xB7
447 /* Vendor Revision - 184-185 */
448 #define SFF_8636_VENDOR_REV_START_OFFSET 0xB8
449 #define SFF_8636_VENDOR_REV_END_OFFSET 0xB9
451 /* Wavelength - 186-187 */
452 #define SFF_8636_WAVELEN_HIGH_BYTE_OFFSET 0xBA
453 #define SFF_8636_WAVELEN_LOW_BYTE_OFFSET 0xBB
455 /* Wavelength Tolerance- 188-189 */
456 #define SFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET 0xBC
457 #define SFF_8636_WAVE_TOL_LOW_BYTE_OFFSET 0xBD
459 /* Max case temp - Other than 70 C - 190 */
460 #define SFF_8636_MAXCASE_TEMP_OFFSET 0xBE
463 #define SFF_8636_CC_BASE_OFFSET 0xBF
465 /* Option Values - 192-195 */
466 #define SFF_8636_OPTION_1_OFFSET 0xC0
467 #define SFF_8636_ETHERNET_UNSPECIFIED 0x00
468 #define SFF_8636_ETHERNET_100G_AOC 0x01
469 #define SFF_8636_ETHERNET_100G_SR4 0x02
470 #define SFF_8636_ETHERNET_100G_LR4 0x03
471 #define SFF_8636_ETHERNET_100G_ER4 0x04
472 #define SFF_8636_ETHERNET_100G_SR10 0x05
473 #define SFF_8636_ETHERNET_100G_CWDM4_FEC 0x06
474 #define SFF_8636_ETHERNET_100G_PSM4 0x07
475 #define SFF_8636_ETHERNET_100G_ACC 0x08
476 #define SFF_8636_ETHERNET_100G_CWDM4_NO_FEC 0x09
477 #define SFF_8636_ETHERNET_100G_RSVD1 0x0A
478 #define SFF_8636_ETHERNET_100G_CR4 0x0B
479 #define SFF_8636_ETHERNET_25G_CR_CA_S 0x0C
480 #define SFF_8636_ETHERNET_25G_CR_CA_N 0x0D
481 #define SFF_8636_ETHERNET_40G_ER4 0x10
482 #define SFF_8636_ETHERNET_4X10_SR 0x11
483 #define SFF_8636_ETHERNET_40G_PSM4 0x12
484 #define SFF_8636_ETHERNET_G959_P1I1_2D1 0x13
485 #define SFF_8636_ETHERNET_G959_P1S1_2D2 0x14
486 #define SFF_8636_ETHERNET_G959_P1L1_2D2 0x15
487 #define SFF_8636_ETHERNET_10GT_SFI 0x16
488 #define SFF_8636_ETHERNET_100G_CLR4 0x17
489 #define SFF_8636_ETHERNET_100G_AOC2 0x18
490 #define SFF_8636_ETHERNET_100G_ACC2 0x19
492 #define SFF_8636_OPTION_2_OFFSET 0xC1
493 /* Rx output amplitude */
494 #define SFF_8636_O2_RX_OUTPUT_AMP RTE_BIT32(0)
495 #define SFF_8636_OPTION_3_OFFSET 0xC2
496 /* Rx Squelch Disable */
497 #define SFF_8636_O3_RX_SQL_DSBL RTE_BIT32(3)
498 /* Rx Output Disable capable */
499 #define SFF_8636_O3_RX_OUTPUT_DSBL RTE_BIT32(2)
500 /* Tx Squelch Disable */
501 #define SFF_8636_O3_TX_SQL_DSBL RTE_BIT32(1)
502 /* Tx Squelch Impl */
503 #define SFF_8636_O3_TX_SQL_IMPL RTE_BIT32(0)
504 #define SFF_8636_OPTION_4_OFFSET 0xC3
505 /* Memory Page 02 present */
506 #define SFF_8636_O4_PAGE_02_PRESENT RTE_BIT32(7)
507 /* Memory Page 01 present */
508 #define SFF_8636_O4_PAGE_01_PRESENT RTE_BIT32(6)
509 /* Rate Select implemented */
510 #define SFF_8636_O4_RATE_SELECT RTE_BIT32(5)
511 /* Tx_DISABLE implemented */
512 #define SFF_8636_O4_TX_DISABLE RTE_BIT32(4)
513 /* Tx_FAULT implemented */
514 #define SFF_8636_O4_TX_FAULT RTE_BIT32(3)
515 /* Tx Squelch implemented */
516 #define SFF_8636_O4_TX_SQUELCH RTE_BIT32(2)
517 /* Tx Loss of Signal */
518 #define SFF_8636_O4_TX_LOS RTE_BIT32(1)
520 /* Vendor SN - 196-211 */
521 #define SFF_8636_VENDOR_SN_START_OFFSET 0xC4
522 #define SFF_8636_VENDOR_SN_END_OFFSET 0xD3
524 /* Vendor Date - 212-219 */
525 #define SFF_8636_DATE_YEAR_OFFSET 0xD4
526 #define SFF_8636_DATE_YEAR_LEN 2
527 #define SFF_8636_DATE_MONTH_OFFSET 0xD6
528 #define SFF_8636_DATE_MONTH_LEN 2
529 #define SFF_8636_DATE_DAY_OFFSET 0xD8
530 #define SFF_8636_DATE_DAY_LEN 2
531 #define SFF_8636_DATE_VENDOR_LOT_OFFSET 0xDA
532 #define SFF_8636_DATE_VENDOR_LOT_LEN 2
534 /* Diagnostic Monitoring Type - 220 */
535 #define SFF_8636_DIAG_TYPE_OFFSET 0xDC
536 #define SFF_8636_RX_PWR_TYPE_MASK 0x8
537 #define SFF_8636_RX_PWR_TYPE_AVG_PWR RTE_BIT32(3)
538 #define SFF_8636_RX_PWR_TYPE_OMA (0 << 3)
539 #define SFF_8636_TX_PWR_TYPE_MASK 0x4
540 #define SFF_8636_TX_PWR_TYPE_AVG_PWR RTE_BIT32(2)
542 /* Enhanced Options - 221 */
543 #define SFF_8636_ENH_OPTIONS_OFFSET 0xDD
544 #define SFF_8636_RATE_SELECT_EXT_SUPPORT RTE_BIT32(3)
545 #define SFF_8636_RATE_SELECT_APP_TABLE_SUPPORT RTE_BIT32(2)
547 /* Check code - 223 */
548 #define SFF_8636_CC_EXT_OFFSET 0xDF
549 #define SFF_8636_CC_EXT_LEN 1
551 /*------------------------------------------------------------------------------
553 * Upper Memory Page 03h
554 * Contains module thresholds, channel thresholds and masks,
555 * and optional channel controls
557 * Offset - Page Num(3) * PageSize(0x80) + Page offset
560 /* Module Thresholds (48 Bytes) 128-175 */
561 /* MSB at low address, LSB at high address */
562 #define SFF_8636_TEMP_HALRM 0x200
563 #define SFF_8636_TEMP_LALRM 0x202
564 #define SFF_8636_TEMP_HWARN 0x204
565 #define SFF_8636_TEMP_LWARN 0x206
567 #define SFF_8636_VCC_HALRM 0x210
568 #define SFF_8636_VCC_LALRM 0x212
569 #define SFF_8636_VCC_HWARN 0x214
570 #define SFF_8636_VCC_LWARN 0x216
572 #define SFF_8636_RX_PWR_HALRM 0x230
573 #define SFF_8636_RX_PWR_LALRM 0x232
574 #define SFF_8636_RX_PWR_HWARN 0x234
575 #define SFF_8636_RX_PWR_LWARN 0x236
577 #define SFF_8636_TX_BIAS_HALRM 0x238
578 #define SFF_8636_TX_BIAS_LALRM 0x23A
579 #define SFF_8636_TX_BIAS_HWARN 0x23C
580 #define SFF_8636_TX_BIAS_LWARN 0x23E
582 #define SFF_8636_TX_PWR_HALRM 0x240
583 #define SFF_8636_TX_PWR_LALRM 0x242
584 #define SFF_8636_TX_PWR_HWARN 0x244
585 #define SFF_8636_TX_PWR_LWARN 0x246
587 #define ETH_MODULE_SFF_8636_MAX_LEN 640
588 #define ETH_MODULE_SFF_8436_MAX_LEN 640
590 #endif /* _SFF_8636_H_ */