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37 #define BIT_SIZEOF(x) (sizeof(x) * CHAR_BIT)
39 TAILQ_HEAD(rte_acl_list, rte_tailq_entry);
41 static struct rte_tailq_elem rte_acl_tailq = {
44 EAL_REGISTER_TAILQ(rte_acl_tailq)
47 * If the compiler doesn't support AVX2 instructions,
48 * then the dummy one would be used instead for AVX2 classify method.
50 int __attribute__ ((weak))
51 rte_acl_classify_avx2(__rte_unused const struct rte_acl_ctx *ctx,
52 __rte_unused const uint8_t **data,
53 __rte_unused uint32_t *results,
54 __rte_unused uint32_t num,
55 __rte_unused uint32_t categories)
60 static const rte_acl_classify_t classify_fns[] = {
61 [RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,
62 [RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,
63 [RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,
64 [RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,
67 /* by default, use always available scalar code path. */
68 static enum rte_acl_classify_alg rte_acl_default_classify =
69 RTE_ACL_CLASSIFY_SCALAR;
72 rte_acl_set_default_classify(enum rte_acl_classify_alg alg)
74 rte_acl_default_classify = alg;
78 rte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)
80 if (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))
88 * Select highest available classify method as default one.
89 * Note that CLASSIFY_AVX2 should be set as a default only
90 * if both conditions are met:
91 * at build time compiler supports AVX2 and target cpu supports AVX2.
93 static void __attribute__((constructor))
96 enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
98 #ifdef CC_AVX2_SUPPORT
99 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
100 alg = RTE_ACL_CLASSIFY_AVX2;
101 else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
103 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
105 alg = RTE_ACL_CLASSIFY_SSE;
107 rte_acl_set_default_classify(alg);
111 rte_acl_classify_alg(const struct rte_acl_ctx *ctx, const uint8_t **data,
112 uint32_t *results, uint32_t num, uint32_t categories,
113 enum rte_acl_classify_alg alg)
115 if (categories != 1 &&
116 ((RTE_ACL_RESULTS_MULTIPLIER - 1) & categories) != 0)
119 return classify_fns[alg](ctx, data, results, num, categories);
123 rte_acl_classify(const struct rte_acl_ctx *ctx, const uint8_t **data,
124 uint32_t *results, uint32_t num, uint32_t categories)
126 return rte_acl_classify_alg(ctx, data, results, num, categories,
131 rte_acl_find_existing(const char *name)
133 struct rte_acl_ctx *ctx = NULL;
134 struct rte_acl_list *acl_list;
135 struct rte_tailq_entry *te;
137 acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
139 rte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);
140 TAILQ_FOREACH(te, acl_list, next) {
141 ctx = (struct rte_acl_ctx *) te->data;
142 if (strncmp(name, ctx->name, sizeof(ctx->name)) == 0)
145 rte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);
155 rte_acl_free(struct rte_acl_ctx *ctx)
157 struct rte_acl_list *acl_list;
158 struct rte_tailq_entry *te;
163 acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
165 rte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);
167 /* find our tailq entry */
168 TAILQ_FOREACH(te, acl_list, next) {
169 if (te->data == (void *) ctx)
173 rte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);
177 TAILQ_REMOVE(acl_list, te, next);
179 rte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);
187 rte_acl_create(const struct rte_acl_param *param)
190 struct rte_acl_ctx *ctx;
191 struct rte_acl_list *acl_list;
192 struct rte_tailq_entry *te;
193 char name[sizeof(ctx->name)];
195 acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
197 /* check that input parameters are valid. */
198 if (param == NULL || param->name == NULL) {
203 snprintf(name, sizeof(name), "ACL_%s", param->name);
205 /* calculate amount of memory required for pattern set. */
206 sz = sizeof(*ctx) + param->max_rule_num * param->rule_size;
208 /* get EAL TAILQ lock. */
209 rte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);
211 /* if we already have one with that name */
212 TAILQ_FOREACH(te, acl_list, next) {
213 ctx = (struct rte_acl_ctx *) te->data;
214 if (strncmp(param->name, ctx->name, sizeof(ctx->name)) == 0)
218 /* if ACL with such name doesn't exist, then create a new one. */
221 te = rte_zmalloc("ACL_TAILQ_ENTRY", sizeof(*te), 0);
224 RTE_LOG(ERR, ACL, "Cannot allocate tailq entry!\n");
228 ctx = rte_zmalloc_socket(name, sz, RTE_CACHE_LINE_SIZE, param->socket_id);
232 "allocation of %zu bytes on socket %d for %s failed\n",
233 sz, param->socket_id, name);
237 /* init new allocated context. */
238 ctx->rules = ctx + 1;
239 ctx->max_rules = param->max_rule_num;
240 ctx->rule_sz = param->rule_size;
241 ctx->socket_id = param->socket_id;
242 ctx->alg = rte_acl_default_classify;
243 snprintf(ctx->name, sizeof(ctx->name), "%s", param->name);
245 te->data = (void *) ctx;
247 TAILQ_INSERT_TAIL(acl_list, te, next);
251 rte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);
256 acl_add_rules(struct rte_acl_ctx *ctx, const void *rules, uint32_t num)
260 if (num + ctx->num_rules > ctx->max_rules)
264 pos += ctx->rule_sz * ctx->num_rules;
265 memcpy(pos, rules, num * ctx->rule_sz);
266 ctx->num_rules += num;
272 acl_check_rule(const struct rte_acl_rule_data *rd)
274 if ((rd->category_mask & LEN2MASK(RTE_ACL_MAX_CATEGORIES)) == 0 ||
275 rd->priority > RTE_ACL_MAX_PRIORITY ||
276 rd->priority < RTE_ACL_MIN_PRIORITY ||
277 rd->userdata == RTE_ACL_INVALID_USERDATA)
283 rte_acl_add_rules(struct rte_acl_ctx *ctx, const struct rte_acl_rule *rules,
286 const struct rte_acl_rule *rv;
290 if (ctx == NULL || rules == NULL || 0 == ctx->rule_sz)
293 for (i = 0; i != num; i++) {
294 rv = (const struct rte_acl_rule *)
295 ((uintptr_t)rules + i * ctx->rule_sz);
296 rc = acl_check_rule(&rv->data);
298 RTE_LOG(ERR, ACL, "%s(%s): rule #%u is invalid\n",
299 __func__, ctx->name, i + 1);
304 return acl_add_rules(ctx, rules, num);
309 * Note that RT structures are not affected.
312 rte_acl_reset_rules(struct rte_acl_ctx *ctx)
319 * Reset all rules and destroys RT structures.
322 rte_acl_reset(struct rte_acl_ctx *ctx)
325 rte_acl_reset_rules(ctx);
326 rte_acl_build(ctx, &ctx->config);
331 * Dump ACL context to the stdout.
334 rte_acl_dump(const struct rte_acl_ctx *ctx)
338 printf("acl context <%s>@%p\n", ctx->name, ctx);
339 printf(" socket_id=%"PRId32"\n", ctx->socket_id);
340 printf(" alg=%"PRId32"\n", ctx->alg);
341 printf(" max_rules=%"PRIu32"\n", ctx->max_rules);
342 printf(" rule_size=%"PRIu32"\n", ctx->rule_sz);
343 printf(" num_rules=%"PRIu32"\n", ctx->num_rules);
344 printf(" num_categories=%"PRIu32"\n", ctx->num_categories);
345 printf(" num_tries=%"PRIu32"\n", ctx->num_tries);
349 * Dump all ACL contexts to the stdout.
352 rte_acl_list_dump(void)
354 struct rte_acl_ctx *ctx;
355 struct rte_acl_list *acl_list;
356 struct rte_tailq_entry *te;
358 acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
360 rte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);
361 TAILQ_FOREACH(te, acl_list, next) {
362 ctx = (struct rte_acl_ctx *) te->data;
365 rte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);
369 * Support for legacy ipv4vlan rules.
372 RTE_ACL_RULE_DEF(acl_ipv4vlan_rule, RTE_ACL_IPV4VLAN_NUM_FIELDS);
375 acl_ipv4vlan_check_rule(const struct rte_acl_ipv4vlan_rule *rule)
377 if (rule->src_port_low > rule->src_port_high ||
378 rule->dst_port_low > rule->dst_port_high ||
379 rule->src_mask_len > BIT_SIZEOF(rule->src_addr) ||
380 rule->dst_mask_len > BIT_SIZEOF(rule->dst_addr))
383 return acl_check_rule(&rule->data);
387 acl_ipv4vlan_convert_rule(const struct rte_acl_ipv4vlan_rule *ri,
388 struct acl_ipv4vlan_rule *ro)
392 ro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].value.u8 = ri->proto;
393 ro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].value.u16 = ri->vlan;
394 ro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].value.u16 = ri->domain;
395 ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 = ri->src_addr;
396 ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;
397 ro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].value.u16 = ri->src_port_low;
398 ro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].value.u16 = ri->dst_port_low;
400 ro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].mask_range.u8 = ri->proto_mask;
401 ro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].mask_range.u16 = ri->vlan_mask;
402 ro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].mask_range.u16 =
404 ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 =
406 ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;
407 ro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].mask_range.u16 =
409 ro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].mask_range.u16 =
414 rte_acl_ipv4vlan_add_rules(struct rte_acl_ctx *ctx,
415 const struct rte_acl_ipv4vlan_rule *rules,
420 struct acl_ipv4vlan_rule rv;
422 if (ctx == NULL || rules == NULL || ctx->rule_sz != sizeof(rv))
425 /* check input rules. */
426 for (i = 0; i != num; i++) {
427 rc = acl_ipv4vlan_check_rule(rules + i);
429 RTE_LOG(ERR, ACL, "%s(%s): rule #%u is invalid\n",
430 __func__, ctx->name, i + 1);
435 if (num + ctx->num_rules > ctx->max_rules)
438 /* perform conversion to the internal format and add to the context. */
439 for (i = 0, rc = 0; i != num && rc == 0; i++) {
440 acl_ipv4vlan_convert_rule(rules + i, &rv);
441 rc = acl_add_rules(ctx, &rv, 1);
448 acl_ipv4vlan_config(struct rte_acl_config *cfg,
449 const uint32_t layout[RTE_ACL_IPV4VLAN_NUM],
450 uint32_t num_categories)
452 static const struct rte_acl_field_def
453 ipv4_defs[RTE_ACL_IPV4VLAN_NUM_FIELDS] = {
455 .type = RTE_ACL_FIELD_TYPE_BITMASK,
456 .size = sizeof(uint8_t),
457 .field_index = RTE_ACL_IPV4VLAN_PROTO_FIELD,
458 .input_index = RTE_ACL_IPV4VLAN_PROTO,
461 .type = RTE_ACL_FIELD_TYPE_BITMASK,
462 .size = sizeof(uint16_t),
463 .field_index = RTE_ACL_IPV4VLAN_VLAN1_FIELD,
464 .input_index = RTE_ACL_IPV4VLAN_VLAN,
467 .type = RTE_ACL_FIELD_TYPE_BITMASK,
468 .size = sizeof(uint16_t),
469 .field_index = RTE_ACL_IPV4VLAN_VLAN2_FIELD,
470 .input_index = RTE_ACL_IPV4VLAN_VLAN,
473 .type = RTE_ACL_FIELD_TYPE_MASK,
474 .size = sizeof(uint32_t),
475 .field_index = RTE_ACL_IPV4VLAN_SRC_FIELD,
476 .input_index = RTE_ACL_IPV4VLAN_SRC,
479 .type = RTE_ACL_FIELD_TYPE_MASK,
480 .size = sizeof(uint32_t),
481 .field_index = RTE_ACL_IPV4VLAN_DST_FIELD,
482 .input_index = RTE_ACL_IPV4VLAN_DST,
485 .type = RTE_ACL_FIELD_TYPE_RANGE,
486 .size = sizeof(uint16_t),
487 .field_index = RTE_ACL_IPV4VLAN_SRCP_FIELD,
488 .input_index = RTE_ACL_IPV4VLAN_PORTS,
491 .type = RTE_ACL_FIELD_TYPE_RANGE,
492 .size = sizeof(uint16_t),
493 .field_index = RTE_ACL_IPV4VLAN_DSTP_FIELD,
494 .input_index = RTE_ACL_IPV4VLAN_PORTS,
498 memcpy(&cfg->defs, ipv4_defs, sizeof(ipv4_defs));
499 cfg->num_fields = RTE_DIM(ipv4_defs);
501 cfg->defs[RTE_ACL_IPV4VLAN_PROTO_FIELD].offset =
502 layout[RTE_ACL_IPV4VLAN_PROTO];
503 cfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].offset =
504 layout[RTE_ACL_IPV4VLAN_VLAN];
505 cfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].offset =
506 layout[RTE_ACL_IPV4VLAN_VLAN] +
507 cfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].size;
508 cfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].offset =
509 layout[RTE_ACL_IPV4VLAN_SRC];
510 cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =
511 layout[RTE_ACL_IPV4VLAN_DST];
512 cfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].offset =
513 layout[RTE_ACL_IPV4VLAN_PORTS];
514 cfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].offset =
515 layout[RTE_ACL_IPV4VLAN_PORTS] +
516 cfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].size;
518 cfg->num_categories = num_categories;
522 rte_acl_ipv4vlan_build(struct rte_acl_ctx *ctx,
523 const uint32_t layout[RTE_ACL_IPV4VLAN_NUM],
524 uint32_t num_categories)
526 struct rte_acl_config cfg;
528 if (ctx == NULL || layout == NULL)
531 memset(&cfg, 0, sizeof(cfg));
532 acl_ipv4vlan_config(&cfg, layout, num_categories);
533 return rte_acl_build(ctx, &cfg);