1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015 Cavium, Inc
3 * Copyright(c) 2020 Arm Limited
6 #ifndef _RTE_ATOMIC_ARM64_H_
7 #define _RTE_ATOMIC_ARM64_H_
9 #ifndef RTE_FORCE_INTRINSICS
10 # error Platform must be built with RTE_FORCE_INTRINSICS
17 #include "generic/rte_atomic.h"
18 #include <rte_branch_prediction.h>
19 #include <rte_compat.h>
20 #include <rte_debug.h>
22 #define rte_mb() asm volatile("dmb osh" : : : "memory")
24 #define rte_wmb() asm volatile("dmb oshst" : : : "memory")
26 #define rte_rmb() asm volatile("dmb oshld" : : : "memory")
28 #define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
30 #define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
32 #define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
34 #define rte_io_mb() rte_mb()
36 #define rte_io_wmb() rte_wmb()
38 #define rte_io_rmb() rte_rmb()
40 static __rte_always_inline void
41 rte_atomic_thread_fence(int memorder)
43 __atomic_thread_fence(memorder);
46 /*------------------------ 128 bit atomic operations -------------------------*/
48 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
49 #if defined(RTE_CC_CLANG)
50 #define __LSE_PREAMBLE ".arch armv8-a+lse\n"
52 #define __LSE_PREAMBLE ""
55 #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \
56 static __rte_noinline rte_int128_t \
57 cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) \
59 /* caspX instructions register pair must start from even-numbered
60 * register at operand 1.
61 * So, specify registers for local variables here.
63 register uint64_t x0 __asm("x0") = (uint64_t)old.val[0]; \
64 register uint64_t x1 __asm("x1") = (uint64_t)old.val[1]; \
65 register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0]; \
66 register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1]; \
69 op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \
81 __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp")
82 __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
83 __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
84 __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
87 #undef __ATOMIC128_CAS_OP
93 rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
94 const rte_int128_t *src, unsigned int weak, int success,
97 /* Always do strong CAS */
99 /* Ignore memory ordering for failure, memory order for
100 * success must be stronger or equal
102 RTE_SET_USED(failure);
103 /* Find invalid memory order */
104 RTE_ASSERT(success == __ATOMIC_RELAXED ||
105 success == __ATOMIC_ACQUIRE ||
106 success == __ATOMIC_RELEASE ||
107 success == __ATOMIC_ACQ_REL ||
108 success == __ATOMIC_SEQ_CST);
110 rte_int128_t expected = *exp;
111 rte_int128_t desired = *src;
114 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
115 if (success == __ATOMIC_RELAXED)
116 old = __cas_128_relaxed(dst, expected, desired);
117 else if (success == __ATOMIC_ACQUIRE)
118 old = __cas_128_acquire(dst, expected, desired);
119 else if (success == __ATOMIC_RELEASE)
120 old = __cas_128_release(dst, expected, desired);
122 old = __cas_128_acq_rel(dst, expected, desired);
124 #define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) != __ATOMIC_RELEASE)
125 #define __HAS_RLS(mo) ((mo) == __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
126 (mo) == __ATOMIC_SEQ_CST)
128 int ldx_mo = __HAS_ACQ(success) ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED;
129 int stx_mo = __HAS_RLS(success) ? __ATOMIC_RELEASE : __ATOMIC_RELAXED;
136 /* ldx128 can not guarantee atomic,
137 * Must write back src or old to verify atomicity of ldx128;
141 #define __LOAD_128(op_string, src, dst) { \
143 op_string " %0, %1, %2" \
144 : "=&r" (dst.val[0]), \
146 : "Q" (src->val[0]) \
149 if (ldx_mo == __ATOMIC_RELAXED)
150 __LOAD_128("ldxp", dst, old)
152 __LOAD_128("ldaxp", dst, old)
156 #define __STORE_128(op_string, dst, src, ret) { \
158 op_string " %w0, %1, %2, %3" \
160 : "r" (src.val[0]), \
165 if (likely(old.int128 == expected.int128)) {
166 if (stx_mo == __ATOMIC_RELAXED)
167 __STORE_128("stxp", dst, desired, ret)
169 __STORE_128("stlxp", dst, desired, ret)
171 /* In the failure case (since 'weak' is ignored and only
172 * weak == 0 is implemented), expected should contain
173 * the atomically read value of dst. This means, 'old'
174 * needs to be stored back to ensure it was read
177 if (stx_mo == __ATOMIC_RELAXED)
178 __STORE_128("stxp", dst, old, ret)
180 __STORE_128("stlxp", dst, old, ret)
185 } while (unlikely(ret));
188 /* Unconditionally updating expected removes an 'if' statement.
189 * expected should already be in register if not in the cache.
193 return (old.int128 == expected.int128);
200 #endif /* _RTE_ATOMIC_ARM64_H_ */