lib/librte_eal/arm/include/rte_atomic_64.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015 Cavium, Inc
   3  * Copyright(c) 2020 Arm Limited
   4  */
   5
   6 #ifndef _RTE_ATOMIC_ARM64_H_
   7 #define _RTE_ATOMIC_ARM64_H_
   8
   9 #ifndef RTE_FORCE_INTRINSICS
  10 #  error Platform must be built with RTE_FORCE_INTRINSICS
  11 #endif
  12
  13 #ifdef __cplusplus
  14 extern "C" {
  15 #endif
  16
  17 #include "generic/rte_atomic.h"
  18 #include <rte_branch_prediction.h>
  19 #include <rte_compat.h>
  20 #include <rte_debug.h>
  21
  22 #define rte_mb() asm volatile("dmb osh" : : : "memory")
  23
  24 #define rte_wmb() asm volatile("dmb oshst" : : : "memory")
  25
  26 #define rte_rmb() asm volatile("dmb oshld" : : : "memory")
  27
  28 #define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
  29
  30 #define rte_smp_wmb() asm volatile("dmb ishst" : : : "memory")
  31
  32 #define rte_smp_rmb() asm volatile("dmb ishld" : : : "memory")
  33
  34 #define rte_io_mb() rte_mb()
  35
  36 #define rte_io_wmb() rte_wmb()
  37
  38 #define rte_io_rmb() rte_rmb()
  39
  40 static __rte_always_inline void
  41 rte_atomic_thread_fence(int memorder)
  42 {
  43         __atomic_thread_fence(memorder);
  44 }
  45
  46 /*------------------------ 128 bit atomic operations -------------------------*/
  47
  48 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
  49 #define __LSE_PREAMBLE  ".arch armv8-a+lse\n"
  50
  51 #define __ATOMIC128_CAS_OP(cas_op_name, op_string)                          \
  52 static __rte_noinline rte_int128_t                                          \
  53 cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)      \
  54 {                                                                           \
  55         /* caspX instructions register pair must start from even-numbered
  56          * register at operand 1.
  57          * So, specify registers for local variables here.
  58          */                                                                 \
  59         register uint64_t x0 __asm("x0") = (uint64_t)old.val[0];            \
  60         register uint64_t x1 __asm("x1") = (uint64_t)old.val[1];            \
  61         register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0];        \
  62         register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1];        \
  63         asm volatile(                                                       \
  64                 __LSE_PREAMBLE                                              \
  65                 op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]"   \
  66                 : [old0] "+r" (x0),                                         \
  67                 [old1] "+r" (x1)                                            \
  68                 : [upd0] "r" (x2),                                          \
  69                 [upd1] "r" (x3),                                            \
  70                 [dst] "r" (dst)                                             \
  71                 : "memory");                                                \
  72         old.val[0] = x0;                                                    \
  73         old.val[1] = x1;                                                    \
  74         return old;                                                         \
  75 }
  76
  77 __ATOMIC128_CAS_OP(__cas_128_relaxed, "casp")
  78 __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
  79 __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
  80 __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
  81
  82 #undef __LSE_PREAMBLE
  83 #undef __ATOMIC128_CAS_OP
  84
  85 #endif
  86
  87 __rte_experimental
  88 static inline int
  89 rte_atomic128_cmp_exchange(rte_int128_t *dst, rte_int128_t *exp,
  90                 const rte_int128_t *src, unsigned int weak, int success,
  91                 int failure)
  92 {
  93         /* Always do strong CAS */
  94         RTE_SET_USED(weak);
  95         /* Ignore memory ordering for failure, memory order for
  96          * success must be stronger or equal
  97          */
  98         RTE_SET_USED(failure);
  99         /* Find invalid memory order */
 100         RTE_ASSERT(success == __ATOMIC_RELAXED ||
 101                 success == __ATOMIC_ACQUIRE ||
 102                 success == __ATOMIC_RELEASE ||
 103                 success == __ATOMIC_ACQ_REL ||
 104                 success == __ATOMIC_SEQ_CST);
 105
 106         rte_int128_t expected = *exp;
 107         rte_int128_t desired = *src;
 108         rte_int128_t old;
 109
 110 #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
 111         if (success == __ATOMIC_RELAXED)
 112                 old = __cas_128_relaxed(dst, expected, desired);
 113         else if (success == __ATOMIC_ACQUIRE)
 114                 old = __cas_128_acquire(dst, expected, desired);
 115         else if (success == __ATOMIC_RELEASE)
 116                 old = __cas_128_release(dst, expected, desired);
 117         else
 118                 old = __cas_128_acq_rel(dst, expected, desired);
 119 #else
 120 #define __HAS_ACQ(mo) ((mo) != __ATOMIC_RELAXED && (mo) != __ATOMIC_RELEASE)
 121 #define __HAS_RLS(mo) ((mo) == __ATOMIC_RELEASE || (mo) == __ATOMIC_ACQ_REL || \
 122                 (mo) == __ATOMIC_SEQ_CST)
 123
 124         int ldx_mo = __HAS_ACQ(success) ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED;
 125         int stx_mo = __HAS_RLS(success) ? __ATOMIC_RELEASE : __ATOMIC_RELAXED;
 126
 127 #undef __HAS_ACQ
 128 #undef __HAS_RLS
 129
 130         uint32_t ret = 1;
 131
 132         /* ldx128 can not guarantee atomic,
 133          * Must write back src or old to verify atomicity of ldx128;
 134          */
 135         do {
 136
 137 #define __LOAD_128(op_string, src, dst) { \
 138         asm volatile(                     \
 139                 op_string " %0, %1, %2"   \
 140                 : "=&r" (dst.val[0]),     \
 141                   "=&r" (dst.val[1])      \
 142                 : "Q" (src->val[0])       \
 143                 : "memory"); }
 144
 145                 if (ldx_mo == __ATOMIC_RELAXED)
 146                         __LOAD_128("ldxp", dst, old)
 147                 else
 148                         __LOAD_128("ldaxp", dst, old)
 149
 150 #undef __LOAD_128
 151
 152 #define __STORE_128(op_string, dst, src, ret) { \
 153         asm volatile(                           \
 154                 op_string " %w0, %1, %2, %3"    \
 155                 : "=&r" (ret)                   \
 156                 : "r" (src.val[0]),             \
 157                   "r" (src.val[1]),             \
 158                   "Q" (dst->val[0])             \
 159                 : "memory"); }
 160
 161                 if (likely(old.int128 == expected.int128)) {
 162                         if (stx_mo == __ATOMIC_RELAXED)
 163                                 __STORE_128("stxp", dst, desired, ret)
 164                         else
 165                                 __STORE_128("stlxp", dst, desired, ret)
 166                 } else {
 167                         /* In the failure case (since 'weak' is ignored and only
 168                          * weak == 0 is implemented), expected should contain
 169                          * the atomically read value of dst. This means, 'old'
 170                          * needs to be stored back to ensure it was read
 171                          * atomically.
 172                          */
 173                         if (stx_mo == __ATOMIC_RELAXED)
 174                                 __STORE_128("stxp", dst, old, ret)
 175                         else
 176                                 __STORE_128("stlxp", dst, old, ret)
 177                 }
 178
 179 #undef __STORE_128
 180
 181         } while (unlikely(ret));
 182 #endif
 183
 184         /* Unconditionally updating expected removes an 'if' statement.
 185          * expected should already be in register if not in the cache.
 186          */
 187         *exp = old;
 188
 189         return (old.int128 == expected.int128);
 190 }
 191
 192 #ifdef __cplusplus
 193 }
 194 #endif
 195
 196 #endif /* _RTE_ATOMIC_ARM64_H_ */