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33 #include "rte_cpuflags.h"
35 const struct feature_entry rte_cpu_feature_table[] = {
36 FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0)
37 FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1)
38 FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6)
39 FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7)
40 FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8)
41 FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9)
42 FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10)
43 FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11)
44 FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12)
45 FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13)
46 FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14)
47 FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15)
48 FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16)
49 FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17)
50 FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18)
51 FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19)
52 FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20)
53 FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21)
54 FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22)
55 FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23)
56 FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24)
57 FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25)
58 FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26)
59 FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27)
60 FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28)
61 FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29)
62 FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30)
63 FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31)
64 FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26)
65 FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27)
66 FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28)
67 FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29)
68 FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30)
69 FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31)