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33 * version: DPDK.L.1.2.3-3
39 #include <rte_cpuflags.h>
42 * This should prevent use of advanced instruction sets in this file. Otherwise
43 * the check function itself could cause a crash.
45 #ifdef __INTEL_COMPILER
46 #pragma optimize ("", off)
48 #define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
49 #if GCC_VERSION > 404000
50 #pragma GCC optimize ("O0")
55 * Enumeration of CPU registers
65 * Parameters for CPUID instruction
67 struct cpuid_parameters_t {
72 enum cpu_register_t return_register;
75 #define CPU_FLAG_NAME_MAX_LEN 64
78 * Struct to hold a processor feature entry
80 struct feature_entry {
81 enum rte_cpu_flag_t feature; /**< feature name */
82 char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
83 struct cpuid_parameters_t params; /**< cpuid parameters */
84 uint32_t feature_mask; /**< bitmask for feature */
87 #define FEAT_DEF(f) RTE_CPUFLAG_##f, #f
90 * An array that holds feature entries
92 static const struct feature_entry cpu_feature_table[] = {
93 {FEAT_DEF(SSE3), {0x1, 0, 0, 0, REG_ECX}, 0x00000001},
94 {FEAT_DEF(PCLMULQDQ), {0x1, 0, 0, 0, REG_ECX}, 0x00000002},
95 {FEAT_DEF(DTES64), {0x1, 0, 0, 0, REG_ECX}, 0x00000004},
96 {FEAT_DEF(MONITOR), {0x1, 0, 0, 0, REG_ECX}, 0x00000008},
97 {FEAT_DEF(DS_CPL), {0x1, 0, 0, 0, REG_ECX}, 0x00000010},
98 {FEAT_DEF(VMX), {0x1, 0, 0, 0, REG_ECX}, 0x00000020},
99 {FEAT_DEF(SMX), {0x1, 0, 0, 0, REG_ECX}, 0x00000040},
100 {FEAT_DEF(EIST), {0x1, 0, 0, 0, REG_ECX}, 0x00000080},
101 {FEAT_DEF(TM2), {0x1, 0, 0, 0, REG_ECX}, 0x00000100},
102 {FEAT_DEF(SSSE3), {0x1, 0, 0, 0, REG_ECX}, 0x00000200},
103 {FEAT_DEF(CNXT_ID), {0x1, 0, 0, 0, REG_ECX}, 0x00000400},
104 {FEAT_DEF(FMA), {0x1, 0, 0, 0, REG_ECX}, 0x00001000},
105 {FEAT_DEF(CMPXCHG16B), {0x1, 0, 0, 0, REG_ECX}, 0x00002000},
106 {FEAT_DEF(XTPR), {0x1, 0, 0, 0, REG_ECX}, 0x00004000},
107 {FEAT_DEF(PDCM), {0x1, 0, 0, 0, REG_ECX}, 0x00008000},
108 {FEAT_DEF(PCID), {0x1, 0, 0, 0, REG_ECX}, 0x00020000},
109 {FEAT_DEF(DCA), {0x1, 0, 0, 0, REG_ECX}, 0x00040000},
110 {FEAT_DEF(SSE4_1), {0x1, 0, 0, 0, REG_ECX}, 0x00080000},
111 {FEAT_DEF(SSE4_2), {0x1, 0, 0, 0, REG_ECX}, 0x00100000},
112 {FEAT_DEF(X2APIC), {0x1, 0, 0, 0, REG_ECX}, 0x00200000},
113 {FEAT_DEF(MOVBE), {0x1, 0, 0, 0, REG_ECX}, 0x00400000},
114 {FEAT_DEF(POPCNT), {0x1, 0, 0, 0, REG_ECX}, 0x00800000},
115 {FEAT_DEF(TSC_DEADLINE), {0x1, 0, 0, 0, REG_ECX}, 0x01000000},
116 {FEAT_DEF(AES), {0x1, 0, 0, 0, REG_ECX}, 0x02000000},
117 {FEAT_DEF(XSAVE), {0x1, 0, 0, 0, REG_ECX}, 0x04000000},
118 {FEAT_DEF(OSXSAVE), {0x1, 0, 0, 0, REG_ECX}, 0x08000000},
119 {FEAT_DEF(AVX), {0x1, 0, 0, 0, REG_ECX}, 0x10000000},
120 {FEAT_DEF(F16C), {0x1, 0, 0, 0, REG_ECX}, 0x20000000},
121 {FEAT_DEF(RDRAND), {0x1, 0, 0, 0, REG_ECX}, 0x40000000},
123 {FEAT_DEF(FPU), {0x1, 0, 0, 0, REG_EDX}, 0x00000001},
124 {FEAT_DEF(VME), {0x1, 0, 0, 0, REG_EDX}, 0x00000002},
125 {FEAT_DEF(DE), {0x1, 0, 0, 0, REG_EDX}, 0x00000004},
126 {FEAT_DEF(PSE), {0x1, 0, 0, 0, REG_EDX}, 0x00000008},
127 {FEAT_DEF(TSC), {0x1, 0, 0, 0, REG_EDX}, 0x00000010},
128 {FEAT_DEF(MSR), {0x1, 0, 0, 0, REG_EDX}, 0x00000020},
129 {FEAT_DEF(PAE), {0x1, 0, 0, 0, REG_EDX}, 0x00000040},
130 {FEAT_DEF(MCE), {0x1, 0, 0, 0, REG_EDX}, 0x00000080},
131 {FEAT_DEF(CX8), {0x1, 0, 0, 0, REG_EDX}, 0x00000100},
132 {FEAT_DEF(APIC), {0x1, 0, 0, 0, REG_EDX}, 0x00000200},
133 {FEAT_DEF(SEP), {0x1, 0, 0, 0, REG_EDX}, 0x00000800},
134 {FEAT_DEF(MTRR), {0x1, 0, 0, 0, REG_EDX}, 0x00001000},
135 {FEAT_DEF(PGE), {0x1, 0, 0, 0, REG_EDX}, 0x00002000},
136 {FEAT_DEF(MCA), {0x1, 0, 0, 0, REG_EDX}, 0x00004000},
137 {FEAT_DEF(CMOV), {0x1, 0, 0, 0, REG_EDX}, 0x00008000},
138 {FEAT_DEF(PAT), {0x1, 0, 0, 0, REG_EDX}, 0x00010000},
139 {FEAT_DEF(PSE36), {0x1, 0, 0, 0, REG_EDX}, 0x00020000},
140 {FEAT_DEF(PSN), {0x1, 0, 0, 0, REG_EDX}, 0x00040000},
141 {FEAT_DEF(CLFSH), {0x1, 0, 0, 0, REG_EDX}, 0x00080000},
142 {FEAT_DEF(DS), {0x1, 0, 0, 0, REG_EDX}, 0x00200000},
143 {FEAT_DEF(ACPI), {0x1, 0, 0, 0, REG_EDX}, 0x00400000},
144 {FEAT_DEF(MMX), {0x1, 0, 0, 0, REG_EDX}, 0x00800000},
145 {FEAT_DEF(FXSR), {0x1, 0, 0, 0, REG_EDX}, 0x01000000},
146 {FEAT_DEF(SSE), {0x1, 0, 0, 0, REG_EDX}, 0x02000000},
147 {FEAT_DEF(SSE2), {0x1, 0, 0, 0, REG_EDX}, 0x04000000},
148 {FEAT_DEF(SS), {0x1, 0, 0, 0, REG_EDX}, 0x08000000},
149 {FEAT_DEF(HTT), {0x1, 0, 0, 0, REG_EDX}, 0x10000000},
150 {FEAT_DEF(TM), {0x1, 0, 0, 0, REG_EDX}, 0x20000000},
151 {FEAT_DEF(PBE), {0x1, 0, 0, 0, REG_EDX}, 0x80000000},
153 {FEAT_DEF(DIGTEMP), {0x6, 0, 0, 0, REG_EAX}, 0x00000001},
154 {FEAT_DEF(TRBOBST), {0x6, 0, 0, 0, REG_EAX}, 0x00000002},
155 {FEAT_DEF(ARAT), {0x6, 0, 0, 0, REG_EAX}, 0x00000004},
156 {FEAT_DEF(PLN), {0x6, 0, 0, 0, REG_EAX}, 0x00000010},
157 {FEAT_DEF(ECMD), {0x6, 0, 0, 0, REG_EAX}, 0x00000020},
158 {FEAT_DEF(PTM), {0x6, 0, 0, 0, REG_EAX}, 0x00000040},
160 {FEAT_DEF(MPERF_APERF_MSR), {0x6, 0, 0, 0, REG_ECX}, 0x00000001},
161 {FEAT_DEF(ACNT2), {0x6, 0, 0, 0, REG_ECX}, 0x00000002},
162 {FEAT_DEF(ENERGY_EFF), {0x6, 0, 0, 0, REG_ECX}, 0x00000008},
164 {FEAT_DEF(FSGSBASE), {0x7, 0, 0, 0, REG_EBX}, 0x00000001},
165 {FEAT_DEF(BMI1), {0x7, 0, 0, 0, REG_EBX}, 0x00000004},
166 {FEAT_DEF(AVX2), {0x7, 0, 0, 0, REG_EBX}, 0x00000010},
167 {FEAT_DEF(SMEP), {0x7, 0, 0, 0, REG_EBX}, 0x00000040},
168 {FEAT_DEF(BMI2), {0x7, 0, 0, 0, REG_EBX}, 0x00000080},
169 {FEAT_DEF(ERMS), {0x7, 0, 0, 0, REG_EBX}, 0x00000100},
170 {FEAT_DEF(INVPCID), {0x7, 0, 0, 0, REG_EBX}, 0x00000400},
172 {FEAT_DEF(LAHF_SAHF), {0x80000001, 0, 0, 0, REG_ECX}, 0x00000001},
173 {FEAT_DEF(LZCNT), {0x80000001, 0, 0, 0, REG_ECX}, 0x00000010},
175 {FEAT_DEF(SYSCALL), {0x80000001, 0, 0, 0, REG_EDX}, 0x00000800},
176 {FEAT_DEF(XD), {0x80000001, 0, 0, 0, REG_EDX}, 0x00100000},
177 {FEAT_DEF(1GB_PG), {0x80000001, 0, 0, 0, REG_EDX}, 0x04000000},
178 {FEAT_DEF(RDTSCP), {0x80000001, 0, 0, 0, REG_EDX}, 0x08000000},
179 {FEAT_DEF(EM64T), {0x80000001, 0, 0, 0, REG_EDX}, 0x20000000},
181 {FEAT_DEF(INVTSC), {0x80000007, 0, 0, 0, REG_EDX}, 0x00000100},
185 * Execute CPUID instruction and get contents of a specific register
187 * This function, when compiled with GCC, will generate architecture-neutral
188 * code, as per GCC manual.
191 rte_cpu_get_features(struct cpuid_parameters_t params)
193 int eax, ebx, ecx, edx; /* registers */
195 asm volatile ("cpuid"
207 switch (params.return_register) {
222 * Checks if a particular flag is available on current machine.
225 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
229 if (feature >= RTE_CPUFLAG_NUMFLAGS)
230 /* Flag does not match anything in the feature tables */
233 /* get value of the register containing the desired feature */
234 value = rte_cpu_get_features(cpu_feature_table[feature].params);
236 /* check if the feature is enabled */
237 return (cpu_feature_table[feature].feature_mask & value) > 0;
241 * Checks if the machine is adequate for running the binary. If it is not, the
242 * program exits with status 1.
243 * The function attribute forces this function to be called before main(). But
244 * with ICC, the check is generated by the compiler.
246 #ifndef __INTEL_COMPILER
247 static void __attribute__ ((__constructor__))
248 rte_cpu_check_supported(void)
250 /* This is generated at compile-time by the build system */
251 static const enum rte_cpu_flag_t compile_time_flags[] = {
252 RTE_COMPILE_TIME_CPUFLAGS
256 for (i = 0; i < sizeof(compile_time_flags)/sizeof(compile_time_flags[0]); i++)
257 if (rte_cpu_get_flag_enabled(compile_time_flags[i]) < 1) {
259 "ERROR: This system does not support \"%s\".\n"
260 "Please check that RTE_MACHINE is set correctly.\n",
261 cpu_feature_table[compile_time_flags[i]].name);