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37 #include <rte_cpuflags.h>
40 * This should prevent use of advanced instruction sets in this file. Otherwise
41 * the check function itself could cause a crash.
43 #ifdef __INTEL_COMPILER
44 #pragma optimize ("", off)
46 #define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
47 #if GCC_VERSION > 404000
48 #pragma GCC optimize ("O0")
53 * Enumeration of CPU registers
62 typedef uint32_t cpuid_registers_t[4];
64 #define CPU_FLAG_NAME_MAX_LEN 64
67 * Struct to hold a processor feature entry
69 struct feature_entry {
70 uint32_t leaf; /**< cpuid leaf */
71 uint32_t subleaf; /**< cpuid subleaf */
72 uint32_t reg; /**< cpuid register */
73 uint32_t bit; /**< cpuid register bit */
74 char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */
77 #define FEAT_DEF(name, leaf, subleaf, reg, bit) \
78 [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
81 * An array that holds feature entries
83 static const struct feature_entry cpu_feature_table[] = {
84 FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)
85 FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)
86 FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)
87 FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)
88 FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)
89 FEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)
90 FEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)
91 FEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)
92 FEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)
93 FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)
94 FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
95 FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
96 FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
97 FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
98 FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
99 FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
100 FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
101 FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
102 FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
103 FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
104 FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
105 FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
106 FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
107 FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
108 FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
109 FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
110 FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
111 FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
112 FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
114 FEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)
115 FEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)
116 FEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)
117 FEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)
118 FEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)
119 FEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)
120 FEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)
121 FEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)
122 FEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)
123 FEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)
124 FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
125 FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
126 FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
127 FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
128 FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
129 FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
130 FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
131 FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
132 FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
133 FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
134 FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
135 FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
136 FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
137 FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
138 FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
139 FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
140 FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
141 FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
142 FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
144 FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)
145 FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)
146 FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)
147 FEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)
148 FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)
149 FEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)
151 FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)
152 FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)
153 FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)
155 FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)
156 FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)
157 FEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)
158 FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)
159 FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)
160 FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)
161 FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)
162 FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
163 FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
165 FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)
166 FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)
168 FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
169 FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
170 FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
171 FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
172 FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
174 FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)
178 * Execute CPUID instruction and get contents of a specific register
180 * This function, when compiled with GCC, will generate architecture-neutral
181 * code, as per GCC manual.
184 rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
186 #if defined(__i386__) && defined(__PIC__)
187 /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
188 asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
189 : "=r" (out[REG_EBX]),
193 : "a" (leaf), "c" (subleaf));
197 : "=a" (out[REG_EAX]),
201 : "a" (leaf), "c" (subleaf));
207 * Checks if a particular flag is available on current machine.
210 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
212 const struct feature_entry *feat;
213 cpuid_registers_t regs;
216 if (feature >= RTE_CPUFLAG_NUMFLAGS)
217 /* Flag does not match anything in the feature tables */
220 feat = &cpu_feature_table[feature];
223 /* This entry in the table wasn't filled out! */
226 rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
227 if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
228 regs[REG_EAX] < feat->leaf)
231 /* get the cpuid leaf containing the desired feature */
232 rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
234 /* check if the feature is enabled */
235 return (regs[feat->reg] >> feat->bit) & 1;
239 * Checks if the machine is adequate for running the binary. If it is not, the
240 * program exits with status 1.
241 * The function attribute forces this function to be called before main(). But
242 * with ICC, the check is generated by the compiler.
244 #ifndef __INTEL_COMPILER
245 void __attribute__ ((__constructor__))
249 rte_cpu_check_supported(void)
251 /* This is generated at compile-time by the build system */
252 static const enum rte_cpu_flag_t compile_time_flags[] = {
253 RTE_COMPILE_TIME_CPUFLAGS
258 for (i = 0; i < sizeof(compile_time_flags)/sizeof(compile_time_flags[0]); i++) {
259 ret = rte_cpu_get_flag_enabled(compile_time_flags[i]);
263 "ERROR: CPU feature flag lookup failed with error %d\n",
269 "ERROR: This system does not support \"%s\".\n"
270 "Please check that RTE_MACHINE is set correctly.\n",
271 cpu_feature_table[compile_time_flags[i]].name);