4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright(c) 2014 6WIND S.A.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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45 #include <rte_lcore.h>
46 #include <rte_version.h>
47 #include <rte_devargs.h>
48 #include <rte_memcpy.h>
50 #include "eal_internal_cfg.h"
51 #include "eal_options.h"
52 #include "eal_filesystem.h"
54 #define BITS_PER_HEX 4
58 "b:" /* pci-blacklist */
63 "m:" /* memory size */
64 "n:" /* memory channels */
65 "r:" /* memory ranks */
67 "w:" /* pci-whitelist */
71 eal_long_options[] = {
72 {OPT_BASE_VIRTADDR, 1, NULL, OPT_BASE_VIRTADDR_NUM },
73 {OPT_CREATE_UIO_DEV, 0, NULL, OPT_CREATE_UIO_DEV_NUM },
74 {OPT_FILE_PREFIX, 1, NULL, OPT_FILE_PREFIX_NUM },
75 {OPT_HELP, 0, NULL, OPT_HELP_NUM },
76 {OPT_HUGE_DIR, 1, NULL, OPT_HUGE_DIR_NUM },
77 {OPT_LCORES, 1, NULL, OPT_LCORES_NUM },
78 {OPT_LOG_LEVEL, 1, NULL, OPT_LOG_LEVEL_NUM },
79 {OPT_MASTER_LCORE, 1, NULL, OPT_MASTER_LCORE_NUM },
80 {OPT_NO_HPET, 0, NULL, OPT_NO_HPET_NUM },
81 {OPT_NO_HUGE, 0, NULL, OPT_NO_HUGE_NUM },
82 {OPT_NO_PCI, 0, NULL, OPT_NO_PCI_NUM },
83 {OPT_NO_SHCONF, 0, NULL, OPT_NO_SHCONF_NUM },
84 {OPT_PCI_BLACKLIST, 1, NULL, OPT_PCI_BLACKLIST_NUM },
85 {OPT_PCI_WHITELIST, 1, NULL, OPT_PCI_WHITELIST_NUM },
86 {OPT_PROC_TYPE, 1, NULL, OPT_PROC_TYPE_NUM },
87 {OPT_SOCKET_MEM, 1, NULL, OPT_SOCKET_MEM_NUM },
88 {OPT_SYSLOG, 1, NULL, OPT_SYSLOG_NUM },
89 {OPT_VDEV, 1, NULL, OPT_VDEV_NUM },
90 {OPT_VFIO_INTR, 1, NULL, OPT_VFIO_INTR_NUM },
91 {OPT_VMWARE_TSC_MAP, 0, NULL, OPT_VMWARE_TSC_MAP_NUM },
92 {OPT_XEN_DOM0, 0, NULL, OPT_XEN_DOM0_NUM },
96 static int lcores_parsed;
97 static int master_lcore_parsed;
98 static int mem_parsed;
101 eal_reset_internal_config(struct internal_config *internal_cfg)
105 internal_cfg->memory = 0;
106 internal_cfg->force_nrank = 0;
107 internal_cfg->force_nchannel = 0;
108 internal_cfg->hugefile_prefix = HUGEFILE_PREFIX_DEFAULT;
109 internal_cfg->hugepage_dir = NULL;
110 internal_cfg->force_sockets = 0;
111 /* zero out the NUMA config */
112 for (i = 0; i < RTE_MAX_NUMA_NODES; i++)
113 internal_cfg->socket_mem[i] = 0;
114 /* zero out hugedir descriptors */
115 for (i = 0; i < MAX_HUGEPAGE_SIZES; i++)
116 internal_cfg->hugepage_info[i].lock_descriptor = -1;
117 internal_cfg->base_virtaddr = 0;
119 internal_cfg->syslog_facility = LOG_DAEMON;
120 /* default value from build option */
121 internal_cfg->log_level = RTE_LOG_LEVEL;
123 internal_cfg->xen_dom0_support = 0;
125 /* if set to NONE, interrupt mode is determined automatically */
126 internal_cfg->vfio_intr_mode = RTE_INTR_MODE_NONE;
128 #ifdef RTE_LIBEAL_USE_HPET
129 internal_cfg->no_hpet = 0;
131 internal_cfg->no_hpet = 1;
133 internal_cfg->vmware_tsc_map = 0;
134 internal_cfg->create_uio_dev = 0;
138 * Parse the coremask given as argument (hexadecimal string) and fill
139 * the global configuration (core role and core count) with the parsed
142 static int xdigit2val(unsigned char c)
156 eal_parse_coremask(const char *coremask)
158 struct rte_config *cfg = rte_eal_get_configuration();
164 if (coremask == NULL)
166 /* Remove all blank characters ahead and after .
167 * Remove 0x/0X if exists.
169 while (isblank(*coremask))
171 if (coremask[0] == '0' && ((coremask[1] == 'x')
172 || (coremask[1] == 'X')))
174 i = strlen(coremask);
175 while ((i > 0) && isblank(coremask[i - 1]))
180 for (i = i - 1; i >= 0 && idx < RTE_MAX_LCORE; i--) {
182 if (isxdigit(c) == 0) {
183 /* invalid characters */
187 for (j = 0; j < BITS_PER_HEX && idx < RTE_MAX_LCORE; j++, idx++)
189 if ((1 << j) & val) {
190 if (!lcore_config[idx].detected) {
191 RTE_LOG(ERR, EAL, "lcore %u "
192 "unavailable\n", idx);
195 cfg->lcore_role[idx] = ROLE_RTE;
196 lcore_config[idx].core_index = count;
199 cfg->lcore_role[idx] = ROLE_OFF;
200 lcore_config[idx].core_index = -1;
205 if (coremask[i] != '0')
207 for (; idx < RTE_MAX_LCORE; idx++) {
208 cfg->lcore_role[idx] = ROLE_OFF;
209 lcore_config[idx].core_index = -1;
213 /* Update the count of enabled logical cores of the EAL configuration */
214 cfg->lcore_count = count;
220 eal_parse_corelist(const char *corelist)
222 struct rte_config *cfg = rte_eal_get_configuration();
228 if (corelist == NULL)
231 /* Remove all blank characters ahead and after */
232 while (isblank(*corelist))
234 i = strlen(corelist);
235 while ((i > 0) && isblank(corelist[i - 1]))
239 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
240 cfg->lcore_role[idx] = ROLE_OFF;
241 lcore_config[idx].core_index = -1;
244 /* Get list of cores */
247 while (isblank(*corelist))
249 if (*corelist == '\0')
252 idx = strtoul(corelist, &end, 10);
253 if (errno || end == NULL)
255 while (isblank(*end))
259 } else if ((*end == ',') || (*end == '\0')) {
261 if (min == RTE_MAX_LCORE)
263 for (idx = min; idx <= max; idx++) {
264 if (cfg->lcore_role[idx] != ROLE_RTE) {
265 cfg->lcore_role[idx] = ROLE_RTE;
266 lcore_config[idx].core_index = count;
274 } while (*end != '\0');
279 /* Update the count of enabled logical cores of the EAL configuration */
280 cfg->lcore_count = count;
286 /* Changes the lcore id of the master thread */
288 eal_parse_master_lcore(const char *arg)
291 struct rte_config *cfg = rte_eal_get_configuration();
294 cfg->master_lcore = (uint32_t) strtol(arg, &parsing_end, 0);
295 if (errno || parsing_end[0] != 0)
297 if (cfg->master_lcore >= RTE_MAX_LCORE)
299 master_lcore_parsed = 1;
304 * Parse elem, the elem could be single number/range or '(' ')' group
305 * 1) A single number elem, it's just a simple digit. e.g. 9
306 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
307 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
308 * Within group elem, '-' used for a range separator;
309 * ',' used for a single number.
312 eal_parse_set(const char *input, uint16_t set[], unsigned num)
315 const char *str = input;
319 memset(set, 0, num * sizeof(uint16_t));
321 while (isblank(*str))
324 /* only digit or left bracket is qualify for start point */
325 if ((!isdigit(*str) && *str != '(') || *str == '\0')
328 /* process single number or single range of number */
331 idx = strtoul(str, &end, 10);
332 if (errno || end == NULL || idx >= num)
335 while (isblank(*end))
341 /* process single <number>-<number> */
343 while (isblank(*end))
349 idx = strtoul(end, &end, 10);
350 if (errno || end == NULL || idx >= num)
353 while (isblank(*end))
355 if (*end != ',' && *end != '\0')
359 if (*end != ',' && *end != '\0' &&
363 for (idx = RTE_MIN(min, max);
364 idx <= RTE_MAX(min, max); idx++)
371 /* process set within bracket */
373 while (isblank(*str))
381 /* go ahead to the first digit */
382 while (isblank(*str))
387 /* get the digit value */
389 idx = strtoul(str, &end, 10);
390 if (errno || end == NULL || idx >= num)
393 /* go ahead to separator '-',',' and ')' */
394 while (isblank(*end))
397 if (min == RTE_MAX_LCORE)
399 else /* avoid continuous '-' */
401 } else if ((*end == ',') || (*end == ')')) {
403 if (min == RTE_MAX_LCORE)
405 for (idx = RTE_MIN(min, max);
406 idx <= RTE_MAX(min, max); idx++)
414 } while (*end != '\0' && *end != ')');
419 /* convert from set array to cpuset bitmap */
421 convert_to_cpuset(rte_cpuset_t *cpusetp,
422 uint16_t *set, unsigned num)
428 for (idx = 0; idx < num; idx++) {
432 if (!lcore_config[idx].detected) {
433 RTE_LOG(ERR, EAL, "core %u "
434 "unavailable\n", idx);
438 CPU_SET(idx, cpusetp);
445 * The format pattern: --lcores='<lcores[@cpus]>[<,lcores[@cpus]>...]'
446 * lcores, cpus could be a single digit/range or a group.
447 * '(' and ')' are necessary if it's a group.
448 * If not supply '@cpus', the value of cpus uses the same as lcores.
449 * e.g. '1,2@(5-7),(3-5)@(0,2),(0,6),7-8' means start 9 EAL thread as below
450 * lcore 0 runs on cpuset 0x41 (cpu 0,6)
451 * lcore 1 runs on cpuset 0x2 (cpu 1)
452 * lcore 2 runs on cpuset 0xe0 (cpu 5,6,7)
453 * lcore 3,4,5 runs on cpuset 0x5 (cpu 0,2)
454 * lcore 6 runs on cpuset 0x41 (cpu 0,6)
455 * lcore 7 runs on cpuset 0x80 (cpu 7)
456 * lcore 8 runs on cpuset 0x100 (cpu 8)
459 eal_parse_lcores(const char *lcores)
461 struct rte_config *cfg = rte_eal_get_configuration();
462 static uint16_t set[RTE_MAX_LCORE];
466 const char *lcore_start = NULL;
467 const char *end = NULL;
476 /* Remove all blank characters ahead and after */
477 while (isblank(*lcores))
480 while ((i > 0) && isblank(lcores[i - 1]))
485 /* Reset lcore config */
486 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
487 cfg->lcore_role[idx] = ROLE_OFF;
488 lcore_config[idx].core_index = -1;
489 CPU_ZERO(&lcore_config[idx].cpuset);
492 /* Get list of cores */
494 while (isblank(*lcores))
499 /* record lcore_set start point */
500 lcore_start = lcores;
502 /* go across a complete bracket */
503 if (*lcore_start == '(') {
504 lcores += strcspn(lcores, ")");
505 if (*lcores++ == '\0')
509 /* scan the separator '@', ','(next) or '\0'(finish) */
510 lcores += strcspn(lcores, "@,");
512 if (*lcores == '@') {
513 /* explicit assign cpu_set */
514 offset = eal_parse_set(lcores + 1, set, RTE_DIM(set));
518 /* prepare cpu_set and update the end cursor */
519 if (0 > convert_to_cpuset(&cpuset,
522 end = lcores + 1 + offset;
523 } else { /* ',' or '\0' */
524 /* haven't given cpu_set, current loop done */
527 /* go back to check <number>-<number> */
528 offset = strcspn(lcore_start, "(-");
529 if (offset < (end - lcore_start) &&
530 *(lcore_start + offset) != '(')
534 if (*end != ',' && *end != '\0')
537 /* parse lcore_set from start point */
538 if (0 > eal_parse_set(lcore_start, set, RTE_DIM(set)))
541 /* without '@', by default using lcore_set as cpu_set */
542 if (*lcores != '@' &&
543 0 > convert_to_cpuset(&cpuset, set, RTE_DIM(set)))
546 /* start to update lcore_set */
547 for (idx = 0; idx < RTE_MAX_LCORE; idx++) {
551 if (cfg->lcore_role[idx] != ROLE_RTE) {
552 lcore_config[idx].core_index = count;
553 cfg->lcore_role[idx] = ROLE_RTE;
559 CPU_SET(idx, &cpuset);
561 rte_memcpy(&lcore_config[idx].cpuset, &cpuset,
562 sizeof(rte_cpuset_t));
566 } while (*end != '\0');
571 cfg->lcore_count = count;
581 eal_parse_syslog(const char *facility, struct internal_config *conf)
588 { "auth", LOG_AUTH },
589 { "cron", LOG_CRON },
590 { "daemon", LOG_DAEMON },
592 { "kern", LOG_KERN },
594 { "mail", LOG_MAIL },
595 { "news", LOG_NEWS },
596 { "syslog", LOG_SYSLOG },
597 { "user", LOG_USER },
598 { "uucp", LOG_UUCP },
599 { "local0", LOG_LOCAL0 },
600 { "local1", LOG_LOCAL1 },
601 { "local2", LOG_LOCAL2 },
602 { "local3", LOG_LOCAL3 },
603 { "local4", LOG_LOCAL4 },
604 { "local5", LOG_LOCAL5 },
605 { "local6", LOG_LOCAL6 },
606 { "local7", LOG_LOCAL7 },
610 for (i = 0; map[i].name; i++) {
611 if (!strcmp(facility, map[i].name)) {
612 conf->syslog_facility = map[i].value;
620 eal_parse_log_level(const char *level, uint32_t *log_level)
626 tmp = strtoul(level, &end, 0);
628 /* check for errors */
629 if ((errno != 0) || (level[0] == '\0') ||
630 end == NULL || (*end != '\0'))
633 /* log_level is a uint32_t */
634 if (tmp >= UINT32_MAX)
641 static enum rte_proc_type_t
642 eal_parse_proc_type(const char *arg)
644 if (strncasecmp(arg, "primary", sizeof("primary")) == 0)
645 return RTE_PROC_PRIMARY;
646 if (strncasecmp(arg, "secondary", sizeof("secondary")) == 0)
647 return RTE_PROC_SECONDARY;
648 if (strncasecmp(arg, "auto", sizeof("auto")) == 0)
649 return RTE_PROC_AUTO;
651 return RTE_PROC_INVALID;
655 eal_parse_common_option(int opt, const char *optarg,
656 struct internal_config *conf)
661 if (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI,
668 if (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI,
675 if (eal_parse_coremask(optarg) < 0) {
676 RTE_LOG(ERR, EAL, "invalid coremask\n");
682 if (eal_parse_corelist(optarg) < 0) {
683 RTE_LOG(ERR, EAL, "invalid core list\n");
689 conf->memory = atoi(optarg);
690 conf->memory *= 1024ULL;
691 conf->memory *= 1024ULL;
694 /* force number of channels */
696 conf->force_nchannel = atoi(optarg);
697 if (conf->force_nchannel == 0 ||
698 conf->force_nchannel > 4) {
699 RTE_LOG(ERR, EAL, "invalid channel number\n");
703 /* force number of ranks */
705 conf->force_nrank = atoi(optarg);
706 if (conf->force_nrank == 0 ||
707 conf->force_nrank > 16) {
708 RTE_LOG(ERR, EAL, "invalid rank number\n");
713 /* since message is explicitly requested by user, we
714 * write message at highest log level so it can always
716 * even if info or warning messages are disabled */
717 RTE_LOG(CRIT, EAL, "RTE Version: '%s'\n", rte_version());
721 case OPT_NO_HUGE_NUM:
722 conf->no_hugetlbfs = 1;
729 case OPT_NO_HPET_NUM:
733 case OPT_VMWARE_TSC_MAP_NUM:
734 conf->vmware_tsc_map = 1;
737 case OPT_NO_SHCONF_NUM:
741 case OPT_PROC_TYPE_NUM:
742 conf->process_type = eal_parse_proc_type(optarg);
745 case OPT_MASTER_LCORE_NUM:
746 if (eal_parse_master_lcore(optarg) < 0) {
747 RTE_LOG(ERR, EAL, "invalid parameter for --"
748 OPT_MASTER_LCORE "\n");
754 if (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL,
761 if (eal_parse_syslog(optarg, conf) < 0) {
762 RTE_LOG(ERR, EAL, "invalid parameters for --"
768 case OPT_LOG_LEVEL_NUM: {
771 if (eal_parse_log_level(optarg, &log) < 0) {
773 "invalid parameters for --"
777 conf->log_level = log;
781 if (eal_parse_lcores(optarg) < 0) {
782 RTE_LOG(ERR, EAL, "invalid parameter for --"
788 /* don't know what to do, leave this to caller */
798 eal_adjust_config(struct internal_config *internal_cfg)
801 struct rte_config *cfg = rte_eal_get_configuration();
803 if (internal_config.process_type == RTE_PROC_AUTO)
804 internal_config.process_type = eal_proc_type_detect();
806 /* default master lcore is the first one */
807 if (!master_lcore_parsed)
808 cfg->master_lcore = rte_get_next_lcore(-1, 0, 0);
810 /* if no memory amounts were requested, this will result in 0 and
811 * will be overridden later, right after eal_hugepage_info_init() */
812 for (i = 0; i < RTE_MAX_NUMA_NODES; i++)
813 internal_cfg->memory += internal_cfg->socket_mem[i];
819 eal_check_common_options(struct internal_config *internal_cfg)
821 struct rte_config *cfg = rte_eal_get_configuration();
823 if (!lcores_parsed) {
824 RTE_LOG(ERR, EAL, "CPU cores must be enabled with options "
825 "-c, -l or --lcores\n");
828 if (cfg->lcore_role[cfg->master_lcore] != ROLE_RTE) {
829 RTE_LOG(ERR, EAL, "Master lcore is not enabled for DPDK\n");
833 if (internal_cfg->process_type == RTE_PROC_INVALID) {
834 RTE_LOG(ERR, EAL, "Invalid process type specified\n");
837 if (internal_cfg->process_type == RTE_PROC_PRIMARY &&
838 internal_cfg->force_nchannel == 0) {
839 RTE_LOG(ERR, EAL, "Number of memory channels (-n) not "
843 if (index(internal_cfg->hugefile_prefix, '%') != NULL) {
844 RTE_LOG(ERR, EAL, "Invalid char, '%%', in --"OPT_FILE_PREFIX" "
848 if (mem_parsed && internal_cfg->force_sockets == 1) {
849 RTE_LOG(ERR, EAL, "Options -m and --"OPT_SOCKET_MEM" cannot "
850 "be specified at the same time\n");
853 if (internal_cfg->no_hugetlbfs &&
854 (mem_parsed || internal_cfg->force_sockets == 1)) {
855 RTE_LOG(ERR, EAL, "Options -m or --"OPT_SOCKET_MEM" cannot "
856 "be specified together with --"OPT_NO_HUGE"\n");
860 if (rte_eal_devargs_type_count(RTE_DEVTYPE_WHITELISTED_PCI) != 0 &&
861 rte_eal_devargs_type_count(RTE_DEVTYPE_BLACKLISTED_PCI) != 0) {
862 RTE_LOG(ERR, EAL, "Options blacklist (-b) and whitelist (-w) "
863 "cannot be used at the same time\n");
871 eal_common_usage(void)
873 printf("-c COREMASK|-l CORELIST -n CHANNELS [options]\n\n"
874 "EAL common options:\n"
875 " -c COREMASK Hexadecimal bitmask of cores to run on\n"
876 " -l CORELIST List of cores to run on\n"
877 " The argument format is <c1>[-c2][,c3[-c4],...]\n"
878 " where c1, c2, etc are core indexes between 0 and %d\n"
879 " --"OPT_LCORES" COREMAP Map lcore set to physical cpu set\n"
880 " The argument format is\n"
881 " '<lcores[@cpus]>[<,lcores[@cpus]>...]'\n"
882 " lcores and cpus list are grouped by '(' and ')'\n"
883 " Within the group, '-' is used for range separator,\n"
884 " ',' is used for single number separator.\n"
885 " '( )' can be omitted for single element group,\n"
886 " '@' can be omitted if cpus and lcores have the same value\n"
887 " --"OPT_MASTER_LCORE" ID Core ID that is used as master\n"
888 " -n CHANNELS Number of memory channels\n"
889 " -m MB Memory to allocate (see also --"OPT_SOCKET_MEM")\n"
890 " -r RANKS Force number of memory ranks (don't detect)\n"
891 " -b, --"OPT_PCI_BLACKLIST" Add a PCI device in black list.\n"
892 " Prevent EAL from using this PCI device. The argument\n"
893 " format is <domain:bus:devid.func>.\n"
894 " -w, --"OPT_PCI_WHITELIST" Add a PCI device in white list.\n"
895 " Only use the specified PCI devices. The argument format\n"
896 " is <[domain:]bus:devid.func>. This option can be present\n"
897 " several times (once per device).\n"
898 " [NOTE: PCI whitelist cannot be used with -b option]\n"
899 " --"OPT_VDEV" Add a virtual device.\n"
900 " The argument format is <driver><id>[,key=val,...]\n"
901 " (ex: --vdev=eth_pcap0,iface=eth2).\n"
902 " --"OPT_VMWARE_TSC_MAP" Use VMware TSC map instead of native RDTSC\n"
903 " --"OPT_PROC_TYPE" Type of this process (primary|secondary|auto)\n"
904 " --"OPT_SYSLOG" Set syslog facility\n"
905 " --"OPT_LOG_LEVEL" Set default log level\n"
906 " -v Display version information on startup\n"
907 " -h, --help This help\n"
908 "\nEAL options for DEBUG use only:\n"
909 " --"OPT_NO_HUGE" Use malloc instead of hugetlbfs\n"
910 " --"OPT_NO_PCI" Disable PCI\n"
911 " --"OPT_NO_HPET" Disable HPET\n"
912 " --"OPT_NO_SHCONF" No shared config (mmap'd files)\n"
913 "\n", RTE_MAX_LCORE);