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33 #ifndef _RTE_CYCLES_ARM64_H_
34 #define _RTE_CYCLES_ARM64_H_
40 #include "generic/rte_cycles.h"
43 * Read the time base register.
46 * The time base for this lcore.
48 #ifndef RTE_ARM_EAL_RDTSC_USE_PMU
50 * This call is portable to any ARMv8 architecture, however, typically
51 * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
53 static inline uint64_t
58 asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
63 * This is an alternative method to enable rte_rdtsc() with high resolution
64 * PMU cycles counter.The cycle counter runs at cpu frequency and this scheme
65 * uses ARMv8 PMU subsystem to get the cycle counter at userspace, However,
66 * access to PMU cycle counter from user space is not enabled by default in
68 * It is possible to enable cycle counter at user space access by configuring
69 * the PMU from the privileged mode (kernel space).
71 * asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31)));
72 * asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31));
73 * asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2)));
74 * asm volatile("mrs %0, pmcr_el0" : "=r" (val));
75 * val |= (BIT(0) | BIT(2));
77 * asm volatile("msr pmcr_el0, %0" : : "r" (val));
80 static inline uint64_t
85 asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc));
90 static inline uint64_t
91 rte_rdtsc_precise(void)
97 static inline uint64_t
98 rte_get_tsc_cycles(void) { return rte_rdtsc(); }
104 #endif /* _RTE_CYCLES_ARM64_H_ */