4 * Copyright(c) 2015 Cavium, Inc. All rights reserved.
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7 * modification, are permitted provided that the following conditions
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11 * notice, this list of conditions and the following disclaimer.
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #ifndef _RTE_VECT_ARM_H_
34 #define _RTE_VECT_ARM_H_
37 #include "generic/rte_vect.h"
38 #include "rte_debug.h"
45 typedef int32x4_t xmm_t;
47 #define XMM_SIZE (sizeof(xmm_t))
48 #define XMM_MASK (XMM_SIZE - 1)
50 typedef union rte_xmm {
52 uint8_t u8[XMM_SIZE / sizeof(uint8_t)];
53 uint16_t u16[XMM_SIZE / sizeof(uint16_t)];
54 uint32_t u32[XMM_SIZE / sizeof(uint32_t)];
55 uint64_t u64[XMM_SIZE / sizeof(uint64_t)];
56 double pd[XMM_SIZE / sizeof(double)];
57 } __attribute__((aligned(16))) rte_xmm_t;
60 /* NEON intrinsic vqtbl1q_u8() is not supported in ARMv7-A(AArch32) */
61 static __inline uint8x16_t
62 vqtbl1q_u8(uint8x16_t a, uint8x16_t b)
65 rte_xmm_t rte_a, rte_b, rte_ret;
67 vst1q_u8(rte_a.u8, a);
68 vst1q_u8(rte_b.u8, b);
70 for (i = 0; i < 16; i++) {
73 rte_ret.u8[i] = rte_a.u8[pos];
78 return vld1q_u8(rte_ret.u8);
82 #if defined(RTE_TOOLCHAIN_GCC) && (GCC_VERSION < 70000)
83 static inline uint32x4_t
84 vcopyq_laneq_u32(uint32x4_t a, const int lane_a,
85 uint32x4_t b, const int lane_b)
87 return vsetq_lane_u32(vgetq_lane_u32(b, lane_b), a, lane_a);
91 #if defined(RTE_ARCH_ARM64)
92 #if defined(RTE_TOOLCHAIN_GCC) && (GCC_VERSION < 70000)
93 /* NEON intrinsic vreinterpretq_u64_p128() is supported since GCC version 7 */
94 static inline uint64x2_t
95 vreinterpretq_u64_p128(poly128_t x)
100 /* NEON intrinsic vreinterpretq_p64_u64() is supported since GCC version 7 */
101 static inline poly64x2_t
102 vreinterpretq_p64_u64(uint64x2_t x)
104 return (poly64x2_t)x;
107 /* NEON intrinsic vgetq_lane_p64() is supported since GCC version 7 */
108 static inline poly64_t
109 vgetq_lane_p64(poly64x2_t x, const int lane)
111 RTE_ASSERT(lane >= 0 && lane <= 1);
113 poly64_t *p = (poly64_t *)&x;
121 * If (0 <= index <= 15), then call the ASIMD ext intruction on the
122 * 128 bit regs v0 and v1 with the appropriate index.
124 * Else returns a zero vector.
126 static inline uint8x16_t
127 vextract(uint8x16_t v0, uint8x16_t v1, const int index)
130 case 0: return vextq_u8(v0, v1, 0);
131 case 1: return vextq_u8(v0, v1, 1);
132 case 2: return vextq_u8(v0, v1, 2);
133 case 3: return vextq_u8(v0, v1, 3);
134 case 4: return vextq_u8(v0, v1, 4);
135 case 5: return vextq_u8(v0, v1, 5);
136 case 6: return vextq_u8(v0, v1, 6);
137 case 7: return vextq_u8(v0, v1, 7);
138 case 8: return vextq_u8(v0, v1, 8);
139 case 9: return vextq_u8(v0, v1, 9);
140 case 10: return vextq_u8(v0, v1, 10);
141 case 11: return vextq_u8(v0, v1, 11);
142 case 12: return vextq_u8(v0, v1, 12);
143 case 13: return vextq_u8(v0, v1, 13);
144 case 14: return vextq_u8(v0, v1, 14);
145 case 15: return vextq_u8(v0, v1, 15);
147 return vdupq_n_u8(0);
151 * Shifts right 128 bit register by specified number of bytes
153 * Value of shift parameter must be in range 0 - 16
155 static inline uint64x2_t
156 vshift_bytes_right(uint64x2_t reg, const unsigned int shift)
158 return vreinterpretq_u64_u8(vextract(
159 vreinterpretq_u8_u64(reg),
165 * Shifts left 128 bit register by specified number of bytes
167 * Value of shift parameter must be in range 0 - 16
169 static inline uint64x2_t
170 vshift_bytes_left(uint64x2_t reg, const unsigned int shift)
172 return vreinterpretq_u64_u8(vextract(
174 vreinterpretq_u8_u64(reg),