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34 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
35 * Copyright (c) 2008 Marcel Moolenaar
36 * Copyright (c) 2001 Benno Rice
37 * Copyright (c) 2001 David E. O'Brien
38 * Copyright (c) 1998 Doug Rabson
39 * All rights reserved.
42 #ifndef _RTE_ATOMIC_PPC_64_H_
43 #define _RTE_ATOMIC_PPC_64_H_
50 #include "generic/rte_atomic.h"
53 * General memory barrier.
55 * Guarantees that the LOAD and STORE operations generated before the
56 * barrier occur before the LOAD and STORE operations generated after.
58 #define rte_mb() asm volatile("sync" : : : "memory")
61 * Write memory barrier.
63 * Guarantees that the STORE operations generated before the barrier
64 * occur before the STORE operations generated after.
67 #define rte_wmb() asm volatile("lwsync" : : : "memory")
69 #define rte_wmb() asm volatile("sync" : : : "memory")
73 * Read memory barrier.
75 * Guarantees that the LOAD operations generated before the barrier
76 * occur before the LOAD operations generated after.
79 #define rte_rmb() asm volatile("lwsync" : : : "memory")
81 #define rte_rmb() asm volatile("sync" : : : "memory")
84 #define rte_smp_mb() rte_mb()
86 #define rte_smp_wmb() rte_wmb()
88 #define rte_smp_rmb() rte_rmb()
90 #define rte_io_mb() rte_mb()
92 #define rte_io_wmb() rte_wmb()
94 #define rte_io_rmb() rte_rmb()
96 #define rte_cio_wmb() rte_wmb()
98 #define rte_cio_rmb() rte_rmb()
100 /*------------------------- 16 bit atomic operations -------------------------*/
101 /* To be compatible with Power7, use GCC built-in functions for 16 bit
104 #ifndef RTE_FORCE_INTRINSICS
106 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
108 return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
109 __ATOMIC_ACQUIRE) ? 1 : 0;
112 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
114 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
118 rte_atomic16_inc(rte_atomic16_t *v)
120 __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
124 rte_atomic16_dec(rte_atomic16_t *v)
126 __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
129 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
131 return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
134 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
136 return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
139 /*------------------------- 32 bit atomic operations -------------------------*/
142 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
144 unsigned int ret = 0;
148 "1:\tlwarx %[ret], 0, %[dst]\n"
149 "cmplw %[exp], %[ret]\n"
151 "stwcx. %[src], 0, %[dst]\n"
156 "stwcx. %[ret], 0, %[dst]\n"
160 : [ret] "=&r" (ret), "=m" (*dst)
170 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
172 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
176 rte_atomic32_inc(rte_atomic32_t *v)
181 "1: lwarx %[t],0,%[cnt]\n"
182 "addic %[t],%[t],1\n"
183 "stwcx. %[t],0,%[cnt]\n"
185 : [t] "=&r" (t), "=m" (v->cnt)
186 : [cnt] "r" (&v->cnt), "m" (v->cnt)
187 : "cc", "xer", "memory");
191 rte_atomic32_dec(rte_atomic32_t *v)
196 "1: lwarx %[t],0,%[cnt]\n"
197 "addic %[t],%[t],-1\n"
198 "stwcx. %[t],0,%[cnt]\n"
200 : [t] "=&r" (t), "=m" (v->cnt)
201 : [cnt] "r" (&v->cnt), "m" (v->cnt)
202 : "cc", "xer", "memory");
205 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
211 "1: lwarx %[ret],0,%[cnt]\n"
212 "addic %[ret],%[ret],1\n"
213 "stwcx. %[ret],0,%[cnt]\n"
217 : [cnt] "r" (&v->cnt)
218 : "cc", "xer", "memory");
223 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
229 "1: lwarx %[ret],0,%[cnt]\n"
230 "addic %[ret],%[ret],-1\n"
231 "stwcx. %[ret],0,%[cnt]\n"
235 : [cnt] "r" (&v->cnt)
236 : "cc", "xer", "memory");
240 /*------------------------- 64 bit atomic operations -------------------------*/
243 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
245 unsigned int ret = 0;
249 "1: ldarx %[ret], 0, %[dst]\n"
250 "cmpld %[exp], %[ret]\n"
252 "stdcx. %[src], 0, %[dst]\n"
257 "stdcx. %[ret], 0, %[dst]\n"
261 : [ret] "=&r" (ret), "=m" (*dst)
271 rte_atomic64_init(rte_atomic64_t *v)
276 static inline int64_t
277 rte_atomic64_read(rte_atomic64_t *v)
281 asm volatile("ld%U1%X1 %[ret],%[cnt]"
283 : [cnt] "m"(v->cnt));
289 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
291 asm volatile("std%U0%X0 %[new_value],%[cnt]"
293 : [new_value] "r"(new_value));
297 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
302 "1: ldarx %[t],0,%[cnt]\n"
303 "add %[t],%[inc],%[t]\n"
304 "stdcx. %[t],0,%[cnt]\n"
306 : [t] "=&r" (t), "=m" (v->cnt)
307 : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
312 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
317 "1: ldarx %[t],0,%[cnt]\n"
318 "subf %[t],%[dec],%[t]\n"
319 "stdcx. %[t],0,%[cnt]\n"
321 : [t] "=&r" (t), "+m" (v->cnt)
322 : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
327 rte_atomic64_inc(rte_atomic64_t *v)
332 "1: ldarx %[t],0,%[cnt]\n"
333 "addic %[t],%[t],1\n"
334 "stdcx. %[t],0,%[cnt]\n"
336 : [t] "=&r" (t), "+m" (v->cnt)
337 : [cnt] "r" (&v->cnt), "m" (v->cnt)
338 : "cc", "xer", "memory");
342 rte_atomic64_dec(rte_atomic64_t *v)
347 "1: ldarx %[t],0,%[cnt]\n"
348 "addic %[t],%[t],-1\n"
349 "stdcx. %[t],0,%[cnt]\n"
351 : [t] "=&r" (t), "+m" (v->cnt)
352 : [cnt] "r" (&v->cnt), "m" (v->cnt)
353 : "cc", "xer", "memory");
356 static inline int64_t
357 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
363 "1: ldarx %[ret],0,%[cnt]\n"
364 "add %[ret],%[inc],%[ret]\n"
365 "stdcx. %[ret],0,%[cnt]\n"
369 : [inc] "r" (inc), [cnt] "r" (&v->cnt)
375 static inline int64_t
376 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
382 "1: ldarx %[ret],0,%[cnt]\n"
383 "subf %[ret],%[dec],%[ret]\n"
384 "stdcx. %[ret],0,%[cnt]\n"
388 : [dec] "r" (dec), [cnt] "r" (&v->cnt)
394 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
400 "1: ldarx %[ret],0,%[cnt]\n"
401 "addic %[ret],%[ret],1\n"
402 "stdcx. %[ret],0,%[cnt]\n"
406 : [cnt] "r" (&v->cnt)
407 : "cc", "xer", "memory");
412 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
418 "1: ldarx %[ret],0,%[cnt]\n"
419 "addic %[ret],%[ret],-1\n"
420 "stdcx. %[ret],0,%[cnt]\n"
424 : [cnt] "r" (&v->cnt)
425 : "cc", "xer", "memory");
430 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
432 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
436 * Atomically set a 64-bit counter to 0.
439 * A pointer to the atomic counter.
441 static inline void rte_atomic64_clear(rte_atomic64_t *v)
451 #endif /* _RTE_ATOMIC_PPC_64_H_ */