4 * Copyright (C) IBM Corporation 2014.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of IBM Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
35 * Copyright (c) 2008 Marcel Moolenaar
36 * Copyright (c) 2001 Benno Rice
37 * Copyright (c) 2001 David E. O'Brien
38 * Copyright (c) 1998 Doug Rabson
39 * All rights reserved.
42 #ifndef _RTE_ATOMIC_PPC_64_H_
43 #define _RTE_ATOMIC_PPC_64_H_
50 #include "generic/rte_atomic.h"
53 * General memory barrier.
55 * Guarantees that the LOAD and STORE operations generated before the
56 * barrier occur before the LOAD and STORE operations generated after.
58 #define rte_mb() {asm volatile("sync" : : : "memory"); }
61 * Write memory barrier.
63 * Guarantees that the STORE operations generated before the barrier
64 * occur before the STORE operations generated after.
67 #define rte_wmb() {asm volatile("lwsync" : : : "memory"); }
69 #define rte_wmb() {asm volatile("sync" : : : "memory"); }
73 * Read memory barrier.
75 * Guarantees that the LOAD operations generated before the barrier
76 * occur before the LOAD operations generated after.
79 #define rte_rmb() {asm volatile("lwsync" : : : "memory"); }
81 #define rte_rmb() {asm volatile("sync" : : : "memory"); }
84 #define rte_smp_mb() rte_mb()
86 #define rte_smp_wmb() rte_wmb()
88 #define rte_smp_rmb() rte_rmb()
90 #define rte_io_mb() rte_mb()
92 #define rte_io_wmb() rte_wmb()
94 #define rte_io_rmb() rte_rmb()
96 /*------------------------- 16 bit atomic operations -------------------------*/
97 /* To be compatible with Power7, use GCC built-in functions for 16 bit
100 #ifndef RTE_FORCE_INTRINSICS
102 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
104 return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
105 __ATOMIC_ACQUIRE) ? 1 : 0;
108 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
110 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
114 rte_atomic16_inc(rte_atomic16_t *v)
116 __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
120 rte_atomic16_dec(rte_atomic16_t *v)
122 __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
125 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
127 return __atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
130 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
132 return __atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0;
135 /*------------------------- 32 bit atomic operations -------------------------*/
138 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
140 unsigned int ret = 0;
144 "1:\tlwarx %[ret], 0, %[dst]\n"
145 "cmplw %[exp], %[ret]\n"
147 "stwcx. %[src], 0, %[dst]\n"
152 "stwcx. %[ret], 0, %[dst]\n"
156 : [ret] "=&r" (ret), "=m" (*dst)
166 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
168 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
172 rte_atomic32_inc(rte_atomic32_t *v)
177 "1: lwarx %[t],0,%[cnt]\n"
178 "addic %[t],%[t],1\n"
179 "stwcx. %[t],0,%[cnt]\n"
181 : [t] "=&r" (t), "=m" (v->cnt)
182 : [cnt] "r" (&v->cnt), "m" (v->cnt)
183 : "cc", "xer", "memory");
187 rte_atomic32_dec(rte_atomic32_t *v)
192 "1: lwarx %[t],0,%[cnt]\n"
193 "addic %[t],%[t],-1\n"
194 "stwcx. %[t],0,%[cnt]\n"
196 : [t] "=&r" (t), "=m" (v->cnt)
197 : [cnt] "r" (&v->cnt), "m" (v->cnt)
198 : "cc", "xer", "memory");
201 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
207 "1: lwarx %[ret],0,%[cnt]\n"
208 "addic %[ret],%[ret],1\n"
209 "stwcx. %[ret],0,%[cnt]\n"
213 : [cnt] "r" (&v->cnt)
214 : "cc", "xer", "memory");
219 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
225 "1: lwarx %[ret],0,%[cnt]\n"
226 "addic %[ret],%[ret],-1\n"
227 "stwcx. %[ret],0,%[cnt]\n"
231 : [cnt] "r" (&v->cnt)
232 : "cc", "xer", "memory");
236 /*------------------------- 64 bit atomic operations -------------------------*/
239 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
241 unsigned int ret = 0;
245 "1: ldarx %[ret], 0, %[dst]\n"
246 "cmpld %[exp], %[ret]\n"
248 "stdcx. %[src], 0, %[dst]\n"
253 "stdcx. %[ret], 0, %[dst]\n"
257 : [ret] "=&r" (ret), "=m" (*dst)
267 rte_atomic64_init(rte_atomic64_t *v)
272 static inline int64_t
273 rte_atomic64_read(rte_atomic64_t *v)
277 asm volatile("ld%U1%X1 %[ret],%[cnt]"
279 : [cnt] "m"(v->cnt));
285 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
287 asm volatile("std%U0%X0 %[new_value],%[cnt]"
289 : [new_value] "r"(new_value));
293 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
298 "1: ldarx %[t],0,%[cnt]\n"
299 "add %[t],%[inc],%[t]\n"
300 "stdcx. %[t],0,%[cnt]\n"
302 : [t] "=&r" (t), "=m" (v->cnt)
303 : [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
308 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
313 "1: ldarx %[t],0,%[cnt]\n"
314 "subf %[t],%[dec],%[t]\n"
315 "stdcx. %[t],0,%[cnt]\n"
317 : [t] "=&r" (t), "+m" (v->cnt)
318 : [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
323 rte_atomic64_inc(rte_atomic64_t *v)
328 "1: ldarx %[t],0,%[cnt]\n"
329 "addic %[t],%[t],1\n"
330 "stdcx. %[t],0,%[cnt]\n"
332 : [t] "=&r" (t), "+m" (v->cnt)
333 : [cnt] "r" (&v->cnt), "m" (v->cnt)
334 : "cc", "xer", "memory");
338 rte_atomic64_dec(rte_atomic64_t *v)
343 "1: ldarx %[t],0,%[cnt]\n"
344 "addic %[t],%[t],-1\n"
345 "stdcx. %[t],0,%[cnt]\n"
347 : [t] "=&r" (t), "+m" (v->cnt)
348 : [cnt] "r" (&v->cnt), "m" (v->cnt)
349 : "cc", "xer", "memory");
352 static inline int64_t
353 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
359 "1: ldarx %[ret],0,%[cnt]\n"
360 "add %[ret],%[inc],%[ret]\n"
361 "stdcx. %[ret],0,%[cnt]\n"
365 : [inc] "r" (inc), [cnt] "r" (&v->cnt)
371 static inline int64_t
372 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
378 "1: ldarx %[ret],0,%[cnt]\n"
379 "subf %[ret],%[dec],%[ret]\n"
380 "stdcx. %[ret],0,%[cnt]\n"
384 : [dec] "r" (dec), [cnt] "r" (&v->cnt)
390 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
396 "1: ldarx %[ret],0,%[cnt]\n"
397 "addic %[ret],%[ret],1\n"
398 "stdcx. %[ret],0,%[cnt]\n"
402 : [cnt] "r" (&v->cnt)
403 : "cc", "xer", "memory");
408 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
414 "1: ldarx %[ret],0,%[cnt]\n"
415 "addic %[ret],%[ret],-1\n"
416 "stdcx. %[ret],0,%[cnt]\n"
420 : [cnt] "r" (&v->cnt)
421 : "cc", "xer", "memory");
426 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
428 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
432 * Atomically set a 64-bit counter to 0.
435 * A pointer to the atomic counter.
437 static inline void rte_atomic64_clear(rte_atomic64_t *v)
447 #endif /* _RTE_ATOMIC_PPC_64_H_ */