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33 #ifndef _RTE_CPUFLAGS_PPC_64_H_
34 #define _RTE_CPUFLAGS_PPC_64_H_
45 #include "generic/rte_cpuflags.h"
47 /* Symbolic values for the entries in the auxiliary table */
51 /* software based registers */
58 * Enumeration of all CPU features supported
61 RTE_CPUFLAG_PPC_LE = 0,
63 RTE_CPUFLAG_PSERIES_PERFMON_COMPAT,
65 RTE_CPUFLAG_ARCH_2_06,
66 RTE_CPUFLAG_POWER6_EXT,
69 RTE_CPUFLAG_ARCH_2_05,
70 RTE_CPUFLAG_ICACHE_SNOOP,
74 RTE_CPUFLAG_POWER5_PLUS,
78 RTE_CPUFLAG_EFP_DOUBLE,
79 RTE_CPUFLAG_EFP_SINGLE,
81 RTE_CPUFLAG_UNIFIED_CACHE,
94 RTE_CPUFLAG_ARCH_2_07,
96 RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
99 static const struct feature_entry cpu_feature_table[] = {
100 FEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0)
101 FEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1)
102 FEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6)
103 FEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7)
104 FEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8)
105 FEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9)
106 FEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10)
107 FEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11)
108 FEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12)
109 FEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13)
110 FEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14)
111 FEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15)
112 FEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16)
113 FEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17)
114 FEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18)
115 FEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19)
116 FEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20)
117 FEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21)
118 FEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22)
119 FEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23)
120 FEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24)
121 FEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25)
122 FEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26)
123 FEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27)
124 FEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28)
125 FEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29)
126 FEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30)
127 FEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31)
128 FEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26)
129 FEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27)
130 FEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28)
131 FEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29)
132 FEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30)
133 FEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31)
137 * Read AUXV software register and get cpu features for Power
140 rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
141 __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
146 auxv_fd = open("/proc/self/auxv", O_RDONLY);
148 while (read(auxv_fd, &auxv,
149 sizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {
150 if (auxv.a_type == AT_HWCAP)
151 out[REG_HWCAP] = auxv.a_un.a_val;
152 else if (auxv.a_type == AT_HWCAP2)
153 out[REG_HWCAP2] = auxv.a_un.a_val;
158 * Checks if a particular flag is available on current machine.
161 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
163 const struct feature_entry *feat;
164 cpuid_registers_t regs = {0};
166 if (feature >= RTE_CPUFLAG_NUMFLAGS)
167 /* Flag does not match anything in the feature tables */
170 feat = &cpu_feature_table[feature];
173 /* This entry in the table wasn't filled out! */
176 /* get the cpuid leaf containing the desired feature */
177 rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
179 /* check if the feature is enabled */
180 return (regs[feat->reg] >> feat->bit) & 1;
187 #endif /* _RTE_CPUFLAGS_PPC_64_H_ */