4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Inspired from FreeBSD src/sys/amd64/include/atomic.h
36 * Copyright (c) 1998 Doug Rabson
37 * All rights reserved.
40 #ifndef _RTE_ATOMIC_X86_H_
41 #error do not include this file directly, use <rte_atomic.h> instead
44 #ifndef _RTE_ATOMIC_X86_64_H_
45 #define _RTE_ATOMIC_X86_64_H_
48 #include <rte_common.h>
49 #include <rte_atomic.h>
51 /*------------------------- 64 bit atomic operations -------------------------*/
53 #ifndef RTE_FORCE_INTRINSICS
55 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
62 "cmpxchgq %[src], %[dst];"
64 : [res] "=a" (res), /* output */
66 : [src] "r" (src), /* input */
69 : "memory"); /* no-clobber list */
74 static inline uint64_t
75 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
80 : "=r" (val), "=m" (*dst)
81 : "0" (val), "m" (*dst)
82 : "memory"); /* no-clobber list */
87 rte_atomic64_init(rte_atomic64_t *v)
93 rte_atomic64_read(rte_atomic64_t *v)
99 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
105 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
109 "addq %[inc], %[cnt]"
110 : [cnt] "=m" (v->cnt) /* output */
111 : [inc] "ir" (inc), /* input */
117 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
121 "subq %[dec], %[cnt]"
122 : [cnt] "=m" (v->cnt) /* output */
123 : [dec] "ir" (dec), /* input */
129 rte_atomic64_inc(rte_atomic64_t *v)
134 : [cnt] "=m" (v->cnt) /* output */
135 : "m" (v->cnt) /* input */
140 rte_atomic64_dec(rte_atomic64_t *v)
145 : [cnt] "=m" (v->cnt) /* output */
146 : "m" (v->cnt) /* input */
150 static inline int64_t
151 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
157 "xaddq %[prev], %[cnt]"
158 : [prev] "+r" (prev), /* output */
160 : "m" (v->cnt) /* input */
165 static inline int64_t
166 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
168 return rte_atomic64_add_return(v, -dec);
171 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
179 : [cnt] "+m" (v->cnt), /* output */
186 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
194 : [cnt] "+m" (v->cnt), /* output */
200 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
202 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
205 static inline void rte_atomic64_clear(rte_atomic64_t *v)
211 #endif /* _RTE_ATOMIC_X86_64_H_ */