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8 * modification, are permitted provided that the following conditions
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Inspired from FreeBSD src/sys/amd64/include/atomic.h
36 * Copyright (c) 1998 Doug Rabson
37 * Copyright (c) 2019 Intel Corporation
38 * All rights reserved.
41 #ifndef _RTE_ATOMIC_X86_H_
42 #error do not include this file directly, use <rte_atomic.h> instead
45 #ifndef _RTE_ATOMIC_X86_64_H_
46 #define _RTE_ATOMIC_X86_64_H_
49 #include <rte_common.h>
50 #include <rte_compat.h>
51 #include <rte_atomic.h>
53 /*------------------------- 64 bit atomic operations -------------------------*/
55 #ifndef RTE_FORCE_INTRINSICS
57 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
64 "cmpxchgq %[src], %[dst];"
66 : [res] "=a" (res), /* output */
68 : [src] "r" (src), /* input */
71 : "memory"); /* no-clobber list */
76 static inline uint64_t
77 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
82 : "=r" (val), "=m" (*dst)
83 : "0" (val), "m" (*dst)
84 : "memory"); /* no-clobber list */
89 rte_atomic64_init(rte_atomic64_t *v)
95 rte_atomic64_read(rte_atomic64_t *v)
101 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
107 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
111 "addq %[inc], %[cnt]"
112 : [cnt] "=m" (v->cnt) /* output */
113 : [inc] "ir" (inc), /* input */
119 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
123 "subq %[dec], %[cnt]"
124 : [cnt] "=m" (v->cnt) /* output */
125 : [dec] "ir" (dec), /* input */
131 rte_atomic64_inc(rte_atomic64_t *v)
136 : [cnt] "=m" (v->cnt) /* output */
137 : "m" (v->cnt) /* input */
142 rte_atomic64_dec(rte_atomic64_t *v)
147 : [cnt] "=m" (v->cnt) /* output */
148 : "m" (v->cnt) /* input */
152 static inline int64_t
153 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
159 "xaddq %[prev], %[cnt]"
160 : [prev] "+r" (prev), /* output */
162 : "m" (v->cnt) /* input */
167 static inline int64_t
168 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
170 return rte_atomic64_add_return(v, -dec);
173 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
181 : [cnt] "+m" (v->cnt), /* output */
188 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
196 : [cnt] "+m" (v->cnt), /* output */
202 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
204 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
207 static inline void rte_atomic64_clear(rte_atomic64_t *v)
213 /*------------------------ 128 bit atomic operations -------------------------*/
216 * 128-bit integer structure.
225 } __rte_aligned(16) rte_int128_t;
227 static inline int __rte_experimental
228 rte_atomic128_cmp_exchange(rte_int128_t *dst,
230 const rte_int128_t *src,
236 RTE_SET_USED(success);
237 RTE_SET_USED(failure);
244 : [dst] "=m" (dst->val[0]),
258 #endif /* _RTE_ATOMIC_X86_64_H_ */