lib/librte_eal/common/include/arch/x86/rte_cpuflags.h

   1 /*-
   2  *   BSD LICENSE
   3  *
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   5  *   All rights reserved.
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  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _RTE_CPUFLAGS_X86_64_H_
  35 #define _RTE_CPUFLAGS_X86_64_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdlib.h>
  42 #include <stdio.h>
  43 #include <errno.h>
  44 #include <stdint.h>
  45
  46 #include "generic/rte_cpuflags.h"
  47
  48 extern const struct feature_entry rte_cpu_feature_table[];
  49
  50 enum rte_cpu_flag_t {
  51         /* (EAX 01h) ECX features*/
  52         RTE_CPUFLAG_SSE3 = 0,               /**< SSE3 */
  53         RTE_CPUFLAG_PCLMULQDQ,              /**< PCLMULQDQ */
  54         RTE_CPUFLAG_DTES64,                 /**< DTES64 */
  55         RTE_CPUFLAG_MONITOR,                /**< MONITOR */
  56         RTE_CPUFLAG_DS_CPL,                 /**< DS_CPL */
  57         RTE_CPUFLAG_VMX,                    /**< VMX */
  58         RTE_CPUFLAG_SMX,                    /**< SMX */
  59         RTE_CPUFLAG_EIST,                   /**< EIST */
  60         RTE_CPUFLAG_TM2,                    /**< TM2 */
  61         RTE_CPUFLAG_SSSE3,                  /**< SSSE3 */
  62         RTE_CPUFLAG_CNXT_ID,                /**< CNXT_ID */
  63         RTE_CPUFLAG_FMA,                    /**< FMA */
  64         RTE_CPUFLAG_CMPXCHG16B,             /**< CMPXCHG16B */
  65         RTE_CPUFLAG_XTPR,                   /**< XTPR */
  66         RTE_CPUFLAG_PDCM,                   /**< PDCM */
  67         RTE_CPUFLAG_PCID,                   /**< PCID */
  68         RTE_CPUFLAG_DCA,                    /**< DCA */
  69         RTE_CPUFLAG_SSE4_1,                 /**< SSE4_1 */
  70         RTE_CPUFLAG_SSE4_2,                 /**< SSE4_2 */
  71         RTE_CPUFLAG_X2APIC,                 /**< X2APIC */
  72         RTE_CPUFLAG_MOVBE,                  /**< MOVBE */
  73         RTE_CPUFLAG_POPCNT,                 /**< POPCNT */
  74         RTE_CPUFLAG_TSC_DEADLINE,           /**< TSC_DEADLINE */
  75         RTE_CPUFLAG_AES,                    /**< AES */
  76         RTE_CPUFLAG_XSAVE,                  /**< XSAVE */
  77         RTE_CPUFLAG_OSXSAVE,                /**< OSXSAVE */
  78         RTE_CPUFLAG_AVX,                    /**< AVX */
  79         RTE_CPUFLAG_F16C,                   /**< F16C */
  80         RTE_CPUFLAG_RDRAND,                 /**< RDRAND */
  81
  82         /* (EAX 01h) EDX features */
  83         RTE_CPUFLAG_FPU,                    /**< FPU */
  84         RTE_CPUFLAG_VME,                    /**< VME */
  85         RTE_CPUFLAG_DE,                     /**< DE */
  86         RTE_CPUFLAG_PSE,                    /**< PSE */
  87         RTE_CPUFLAG_TSC,                    /**< TSC */
  88         RTE_CPUFLAG_MSR,                    /**< MSR */
  89         RTE_CPUFLAG_PAE,                    /**< PAE */
  90         RTE_CPUFLAG_MCE,                    /**< MCE */
  91         RTE_CPUFLAG_CX8,                    /**< CX8 */
  92         RTE_CPUFLAG_APIC,                   /**< APIC */
  93         RTE_CPUFLAG_SEP,                    /**< SEP */
  94         RTE_CPUFLAG_MTRR,                   /**< MTRR */
  95         RTE_CPUFLAG_PGE,                    /**< PGE */
  96         RTE_CPUFLAG_MCA,                    /**< MCA */
  97         RTE_CPUFLAG_CMOV,                   /**< CMOV */
  98         RTE_CPUFLAG_PAT,                    /**< PAT */
  99         RTE_CPUFLAG_PSE36,                  /**< PSE36 */
 100         RTE_CPUFLAG_PSN,                    /**< PSN */
 101         RTE_CPUFLAG_CLFSH,                  /**< CLFSH */
 102         RTE_CPUFLAG_DS,                     /**< DS */
 103         RTE_CPUFLAG_ACPI,                   /**< ACPI */
 104         RTE_CPUFLAG_MMX,                    /**< MMX */
 105         RTE_CPUFLAG_FXSR,                   /**< FXSR */
 106         RTE_CPUFLAG_SSE,                    /**< SSE */
 107         RTE_CPUFLAG_SSE2,                   /**< SSE2 */
 108         RTE_CPUFLAG_SS,                     /**< SS */
 109         RTE_CPUFLAG_HTT,                    /**< HTT */
 110         RTE_CPUFLAG_TM,                     /**< TM */
 111         RTE_CPUFLAG_PBE,                    /**< PBE */
 112
 113         /* (EAX 06h) EAX features */
 114         RTE_CPUFLAG_DIGTEMP,                /**< DIGTEMP */
 115         RTE_CPUFLAG_TRBOBST,                /**< TRBOBST */
 116         RTE_CPUFLAG_ARAT,                   /**< ARAT */
 117         RTE_CPUFLAG_PLN,                    /**< PLN */
 118         RTE_CPUFLAG_ECMD,                   /**< ECMD */
 119         RTE_CPUFLAG_PTM,                    /**< PTM */
 120
 121         /* (EAX 06h) ECX features */
 122         RTE_CPUFLAG_MPERF_APERF_MSR,        /**< MPERF_APERF_MSR */
 123         RTE_CPUFLAG_ACNT2,                  /**< ACNT2 */
 124         RTE_CPUFLAG_ENERGY_EFF,             /**< ENERGY_EFF */
 125
 126         /* (EAX 07h, ECX 0h) EBX features */
 127         RTE_CPUFLAG_FSGSBASE,               /**< FSGSBASE */
 128         RTE_CPUFLAG_BMI1,                   /**< BMI1 */
 129         RTE_CPUFLAG_HLE,                    /**< Hardware Lock elision */
 130         RTE_CPUFLAG_AVX2,                   /**< AVX2 */
 131         RTE_CPUFLAG_SMEP,                   /**< SMEP */
 132         RTE_CPUFLAG_BMI2,                   /**< BMI2 */
 133         RTE_CPUFLAG_ERMS,                   /**< ERMS */
 134         RTE_CPUFLAG_INVPCID,                /**< INVPCID */
 135         RTE_CPUFLAG_RTM,                    /**< Transactional memory */
 136         RTE_CPUFLAG_AVX512F,                /**< AVX512F */
 137
 138         /* (EAX 80000001h) ECX features */
 139         RTE_CPUFLAG_LAHF_SAHF,              /**< LAHF_SAHF */
 140         RTE_CPUFLAG_LZCNT,                  /**< LZCNT */
 141
 142         /* (EAX 80000001h) EDX features */
 143         RTE_CPUFLAG_SYSCALL,                /**< SYSCALL */
 144         RTE_CPUFLAG_XD,                     /**< XD */
 145         RTE_CPUFLAG_1GB_PG,                 /**< 1GB_PG */
 146         RTE_CPUFLAG_RDTSCP,                 /**< RDTSCP */
 147         RTE_CPUFLAG_EM64T,                  /**< EM64T */
 148
 149         /* (EAX 80000007h) EDX features */
 150         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 151
 152         /* The last item */
 153         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 154 };
 155
 156 enum cpu_register_t {
 157         RTE_REG_EAX = 0,
 158         RTE_REG_EBX,
 159         RTE_REG_ECX,
 160         RTE_REG_EDX,
 161 };
 162
 163 static inline void
 164 rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
 165 {
 166 #if defined(__i386__) && defined(__PIC__)
 167     /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
 168     asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
 169                  : "=r" (out[RTE_REG_EBX]),
 170                    "=a" (out[RTE_REG_EAX]),
 171                    "=c" (out[RTE_REG_ECX]),
 172                    "=d" (out[RTE_REG_EDX])
 173                  : "a" (leaf), "c" (subleaf));
 174 #else
 175
 176     asm volatile("cpuid"
 177                  : "=a" (out[RTE_REG_EAX]),
 178                    "=b" (out[RTE_REG_EBX]),
 179                    "=c" (out[RTE_REG_ECX]),
 180                    "=d" (out[RTE_REG_EDX])
 181                  : "a" (leaf), "c" (subleaf));
 182
 183 #endif
 184 }
 185
 186 static inline int
 187 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 188 {
 189         const struct feature_entry *feat;
 190         cpuid_registers_t regs;
 191
 192
 193         if (feature >= RTE_CPUFLAG_NUMFLAGS)
 194                 /* Flag does not match anything in the feature tables */
 195                 return -ENOENT;
 196
 197         feat = &rte_cpu_feature_table[feature];
 198
 199         if (!feat->leaf)
 200                 /* This entry in the table wasn't filled out! */
 201                 return -EFAULT;
 202
 203         rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
 204         if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
 205               regs[RTE_REG_EAX] < feat->leaf)
 206                 return 0;
 207
 208         /* get the cpuid leaf containing the desired feature */
 209         rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
 210
 211         /* check if the feature is enabled */
 212         return (regs[feat->reg] >> feat->bit) & 1;
 213 }
 214
 215 #ifdef __cplusplus
 216 }
 217 #endif
 218
 219 #endif /* _RTE_CPUFLAGS_X86_64_H_ */