1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
12 * This file defines a generic API for atomic operations.
16 #include <rte_common.h>
20 /** @name Memory Barrier
24 * General memory barrier.
26 * Guarantees that the LOAD and STORE operations generated before the
27 * barrier occur before the LOAD and STORE operations generated after.
28 * This function is architecture dependent.
30 static inline void rte_mb(void);
33 * Write memory barrier.
35 * Guarantees that the STORE operations generated before the barrier
36 * occur before the STORE operations generated after.
37 * This function is architecture dependent.
39 static inline void rte_wmb(void);
42 * Read memory barrier.
44 * Guarantees that the LOAD operations generated before the barrier
45 * occur before the LOAD operations generated after.
46 * This function is architecture dependent.
48 static inline void rte_rmb(void);
51 /** @name SMP Memory Barrier
55 * General memory barrier between lcores
57 * Guarantees that the LOAD and STORE operations that precede the
58 * rte_smp_mb() call are globally visible across the lcores
59 * before the LOAD and STORE operations that follows it.
61 static inline void rte_smp_mb(void);
64 * Write memory barrier between lcores
66 * Guarantees that the STORE operations that precede the
67 * rte_smp_wmb() call are globally visible across the lcores
68 * before the STORE operations that follows it.
70 static inline void rte_smp_wmb(void);
73 * Read memory barrier between lcores
75 * Guarantees that the LOAD operations that precede the
76 * rte_smp_rmb() call are globally visible across the lcores
77 * before the LOAD operations that follows it.
79 static inline void rte_smp_rmb(void);
82 /** @name I/O Memory Barrier
86 * General memory barrier for I/O device
88 * Guarantees that the LOAD and STORE operations that precede the
89 * rte_io_mb() call are visible to I/O device or CPU before the
90 * LOAD and STORE operations that follow it.
92 static inline void rte_io_mb(void);
95 * Write memory barrier for I/O device
97 * Guarantees that the STORE operations that precede the
98 * rte_io_wmb() call are visible to I/O device before the STORE
99 * operations that follow it.
101 static inline void rte_io_wmb(void);
104 * Read memory barrier for IO device
106 * Guarantees that the LOAD operations on I/O device that precede the
107 * rte_io_rmb() call are visible to CPU before the LOAD
108 * operations that follow it.
110 static inline void rte_io_rmb(void);
113 /** @name Coherent I/O Memory Barrier
115 * Coherent I/O memory barrier is a lightweight version of I/O memory
116 * barriers which are system-wide data synchronization barriers. This
117 * is for only coherent memory domain between lcore and I/O device but
118 * it is same as the I/O memory barriers in most of architectures.
119 * However, some architecture provides even lighter barriers which are
120 * somewhere in between I/O memory barriers and SMP memory barriers.
121 * For example, in case of ARMv8, DMB(data memory barrier) instruction
122 * can have different shareability domains - inner-shareable and
123 * outer-shareable. And inner-shareable DMB fits for SMP memory
124 * barriers and outer-shareable DMB for coherent I/O memory barriers,
125 * which acts on coherent memory.
127 * In most cases, I/O memory barriers are safer but if operations are
128 * on coherent memory instead of incoherent MMIO region of a device,
129 * then coherent I/O memory barriers can be used and this could bring
130 * performance gain depending on architectures.
134 * Write memory barrier for coherent memory between lcore and I/O device
136 * Guarantees that the STORE operations on coherent memory that
137 * precede the rte_cio_wmb() call are visible to I/O device before the
138 * STORE operations that follow it.
140 static inline void rte_cio_wmb(void);
143 * Read memory barrier for coherent memory between lcore and I/O device
145 * Guarantees that the LOAD operations on coherent memory updated by
146 * I/O device that precede the rte_cio_rmb() call are visible to CPU
147 * before the LOAD operations that follow it.
149 static inline void rte_cio_rmb(void);
152 #endif /* __DOXYGEN__ */
157 * Guarantees that operation reordering does not occur at compile time
158 * for operations directly before and after the barrier.
160 #define rte_compiler_barrier() do { \
161 asm volatile ("" : : : "memory"); \
164 /*------------------------- 16 bit atomic operations -------------------------*/
167 * Atomic compare and set.
169 * (atomic) equivalent to:
171 * *dst = src (all 16-bit words)
174 * The destination location into which the value will be written.
176 * The expected value.
180 * Non-zero on success; 0 on failure.
183 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);
185 #ifdef RTE_FORCE_INTRINSICS
187 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
189 return __sync_bool_compare_and_swap(dst, exp, src);
196 * (atomic) equivalent to:
202 * The destination location into which the value will be written.
206 * The original value at that location
208 static inline uint16_t
209 rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val);
211 #ifdef RTE_FORCE_INTRINSICS
212 static inline uint16_t
213 rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
215 return __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);
220 * The atomic counter structure.
223 volatile int16_t cnt; /**< An internal counter value. */
227 * Static initializer for an atomic counter.
229 #define RTE_ATOMIC16_INIT(val) { (val) }
232 * Initialize an atomic counter.
235 * A pointer to the atomic counter.
238 rte_atomic16_init(rte_atomic16_t *v)
244 * Atomically read a 16-bit value from a counter.
247 * A pointer to the atomic counter.
249 * The value of the counter.
251 static inline int16_t
252 rte_atomic16_read(const rte_atomic16_t *v)
258 * Atomically set a counter to a 16-bit value.
261 * A pointer to the atomic counter.
263 * The new value for the counter.
266 rte_atomic16_set(rte_atomic16_t *v, int16_t new_value)
272 * Atomically add a 16-bit value to an atomic counter.
275 * A pointer to the atomic counter.
277 * The value to be added to the counter.
280 rte_atomic16_add(rte_atomic16_t *v, int16_t inc)
282 __sync_fetch_and_add(&v->cnt, inc);
286 * Atomically subtract a 16-bit value from an atomic counter.
289 * A pointer to the atomic counter.
291 * The value to be subtracted from the counter.
294 rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
296 __sync_fetch_and_sub(&v->cnt, dec);
300 * Atomically increment a counter by one.
303 * A pointer to the atomic counter.
306 rte_atomic16_inc(rte_atomic16_t *v);
308 #ifdef RTE_FORCE_INTRINSICS
310 rte_atomic16_inc(rte_atomic16_t *v)
312 rte_atomic16_add(v, 1);
317 * Atomically decrement a counter by one.
320 * A pointer to the atomic counter.
323 rte_atomic16_dec(rte_atomic16_t *v);
325 #ifdef RTE_FORCE_INTRINSICS
327 rte_atomic16_dec(rte_atomic16_t *v)
329 rte_atomic16_sub(v, 1);
334 * Atomically add a 16-bit value to a counter and return the result.
336 * Atomically adds the 16-bits value (inc) to the atomic counter (v) and
337 * returns the value of v after addition.
340 * A pointer to the atomic counter.
342 * The value to be added to the counter.
344 * The value of v after the addition.
346 static inline int16_t
347 rte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)
349 return __sync_add_and_fetch(&v->cnt, inc);
353 * Atomically subtract a 16-bit value from a counter and return
356 * Atomically subtracts the 16-bit value (inc) from the atomic counter
357 * (v) and returns the value of v after the subtraction.
360 * A pointer to the atomic counter.
362 * The value to be subtracted from the counter.
364 * The value of v after the subtraction.
366 static inline int16_t
367 rte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)
369 return __sync_sub_and_fetch(&v->cnt, dec);
373 * Atomically increment a 16-bit counter by one and test.
375 * Atomically increments the atomic counter (v) by one and returns true if
376 * the result is 0, or false in all other cases.
379 * A pointer to the atomic counter.
381 * True if the result after the increment operation is 0; false otherwise.
383 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);
385 #ifdef RTE_FORCE_INTRINSICS
386 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
388 return __sync_add_and_fetch(&v->cnt, 1) == 0;
393 * Atomically decrement a 16-bit counter by one and test.
395 * Atomically decrements the atomic counter (v) by one and returns true if
396 * the result is 0, or false in all other cases.
399 * A pointer to the atomic counter.
401 * True if the result after the decrement operation is 0; false otherwise.
403 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);
405 #ifdef RTE_FORCE_INTRINSICS
406 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
408 return __sync_sub_and_fetch(&v->cnt, 1) == 0;
413 * Atomically test and set a 16-bit atomic counter.
415 * If the counter value is already set, return 0 (failed). Otherwise, set
416 * the counter value to 1 and return 1 (success).
419 * A pointer to the atomic counter.
421 * 0 if failed; else 1, success.
423 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v);
425 #ifdef RTE_FORCE_INTRINSICS
426 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
428 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
433 * Atomically set a 16-bit counter to 0.
436 * A pointer to the atomic counter.
438 static inline void rte_atomic16_clear(rte_atomic16_t *v)
443 /*------------------------- 32 bit atomic operations -------------------------*/
446 * Atomic compare and set.
448 * (atomic) equivalent to:
450 * *dst = src (all 32-bit words)
453 * The destination location into which the value will be written.
455 * The expected value.
459 * Non-zero on success; 0 on failure.
462 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);
464 #ifdef RTE_FORCE_INTRINSICS
466 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
468 return __sync_bool_compare_and_swap(dst, exp, src);
475 * (atomic) equivalent to:
481 * The destination location into which the value will be written.
485 * The original value at that location
487 static inline uint32_t
488 rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val);
490 #ifdef RTE_FORCE_INTRINSICS
491 static inline uint32_t
492 rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
494 return __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);
499 * The atomic counter structure.
502 volatile int32_t cnt; /**< An internal counter value. */
506 * Static initializer for an atomic counter.
508 #define RTE_ATOMIC32_INIT(val) { (val) }
511 * Initialize an atomic counter.
514 * A pointer to the atomic counter.
517 rte_atomic32_init(rte_atomic32_t *v)
523 * Atomically read a 32-bit value from a counter.
526 * A pointer to the atomic counter.
528 * The value of the counter.
530 static inline int32_t
531 rte_atomic32_read(const rte_atomic32_t *v)
537 * Atomically set a counter to a 32-bit value.
540 * A pointer to the atomic counter.
542 * The new value for the counter.
545 rte_atomic32_set(rte_atomic32_t *v, int32_t new_value)
551 * Atomically add a 32-bit value to an atomic counter.
554 * A pointer to the atomic counter.
556 * The value to be added to the counter.
559 rte_atomic32_add(rte_atomic32_t *v, int32_t inc)
561 __sync_fetch_and_add(&v->cnt, inc);
565 * Atomically subtract a 32-bit value from an atomic counter.
568 * A pointer to the atomic counter.
570 * The value to be subtracted from the counter.
573 rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
575 __sync_fetch_and_sub(&v->cnt, dec);
579 * Atomically increment a counter by one.
582 * A pointer to the atomic counter.
585 rte_atomic32_inc(rte_atomic32_t *v);
587 #ifdef RTE_FORCE_INTRINSICS
589 rte_atomic32_inc(rte_atomic32_t *v)
591 rte_atomic32_add(v, 1);
596 * Atomically decrement a counter by one.
599 * A pointer to the atomic counter.
602 rte_atomic32_dec(rte_atomic32_t *v);
604 #ifdef RTE_FORCE_INTRINSICS
606 rte_atomic32_dec(rte_atomic32_t *v)
608 rte_atomic32_sub(v,1);
613 * Atomically add a 32-bit value to a counter and return the result.
615 * Atomically adds the 32-bits value (inc) to the atomic counter (v) and
616 * returns the value of v after addition.
619 * A pointer to the atomic counter.
621 * The value to be added to the counter.
623 * The value of v after the addition.
625 static inline int32_t
626 rte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)
628 return __sync_add_and_fetch(&v->cnt, inc);
632 * Atomically subtract a 32-bit value from a counter and return
635 * Atomically subtracts the 32-bit value (inc) from the atomic counter
636 * (v) and returns the value of v after the subtraction.
639 * A pointer to the atomic counter.
641 * The value to be subtracted from the counter.
643 * The value of v after the subtraction.
645 static inline int32_t
646 rte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)
648 return __sync_sub_and_fetch(&v->cnt, dec);
652 * Atomically increment a 32-bit counter by one and test.
654 * Atomically increments the atomic counter (v) by one and returns true if
655 * the result is 0, or false in all other cases.
658 * A pointer to the atomic counter.
660 * True if the result after the increment operation is 0; false otherwise.
662 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);
664 #ifdef RTE_FORCE_INTRINSICS
665 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
667 return __sync_add_and_fetch(&v->cnt, 1) == 0;
672 * Atomically decrement a 32-bit counter by one and test.
674 * Atomically decrements the atomic counter (v) by one and returns true if
675 * the result is 0, or false in all other cases.
678 * A pointer to the atomic counter.
680 * True if the result after the decrement operation is 0; false otherwise.
682 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);
684 #ifdef RTE_FORCE_INTRINSICS
685 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
687 return __sync_sub_and_fetch(&v->cnt, 1) == 0;
692 * Atomically test and set a 32-bit atomic counter.
694 * If the counter value is already set, return 0 (failed). Otherwise, set
695 * the counter value to 1 and return 1 (success).
698 * A pointer to the atomic counter.
700 * 0 if failed; else 1, success.
702 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v);
704 #ifdef RTE_FORCE_INTRINSICS
705 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
707 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
712 * Atomically set a 32-bit counter to 0.
715 * A pointer to the atomic counter.
717 static inline void rte_atomic32_clear(rte_atomic32_t *v)
722 /*------------------------- 64 bit atomic operations -------------------------*/
725 * An atomic compare and set function used by the mutex functions.
726 * (atomic) equivalent to:
728 * *dst = src (all 64-bit words)
731 * The destination into which the value will be written.
733 * The expected value.
737 * Non-zero on success; 0 on failure.
740 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);
742 #ifdef RTE_FORCE_INTRINSICS
744 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
746 return __sync_bool_compare_and_swap(dst, exp, src);
753 * (atomic) equivalent to:
759 * The destination location into which the value will be written.
763 * The original value at that location
765 static inline uint64_t
766 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val);
768 #ifdef RTE_FORCE_INTRINSICS
769 static inline uint64_t
770 rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
772 return __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);
777 * The atomic counter structure.
780 volatile int64_t cnt; /**< Internal counter value. */
784 * Static initializer for an atomic counter.
786 #define RTE_ATOMIC64_INIT(val) { (val) }
789 * Initialize the atomic counter.
792 * A pointer to the atomic counter.
795 rte_atomic64_init(rte_atomic64_t *v);
797 #ifdef RTE_FORCE_INTRINSICS
799 rte_atomic64_init(rte_atomic64_t *v)
807 while (success == 0) {
809 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
817 * Atomically read a 64-bit counter.
820 * A pointer to the atomic counter.
822 * The value of the counter.
824 static inline int64_t
825 rte_atomic64_read(rte_atomic64_t *v);
827 #ifdef RTE_FORCE_INTRINSICS
828 static inline int64_t
829 rte_atomic64_read(rte_atomic64_t *v)
837 while (success == 0) {
839 /* replace the value by itself */
840 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
849 * Atomically set a 64-bit counter.
852 * A pointer to the atomic counter.
854 * The new value of the counter.
857 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value);
859 #ifdef RTE_FORCE_INTRINSICS
861 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
869 while (success == 0) {
871 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
879 * Atomically add a 64-bit value to a counter.
882 * A pointer to the atomic counter.
884 * The value to be added to the counter.
887 rte_atomic64_add(rte_atomic64_t *v, int64_t inc);
889 #ifdef RTE_FORCE_INTRINSICS
891 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
893 __sync_fetch_and_add(&v->cnt, inc);
898 * Atomically subtract a 64-bit value from a counter.
901 * A pointer to the atomic counter.
903 * The value to be subtracted from the counter.
906 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec);
908 #ifdef RTE_FORCE_INTRINSICS
910 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
912 __sync_fetch_and_sub(&v->cnt, dec);
917 * Atomically increment a 64-bit counter by one and test.
920 * A pointer to the atomic counter.
923 rte_atomic64_inc(rte_atomic64_t *v);
925 #ifdef RTE_FORCE_INTRINSICS
927 rte_atomic64_inc(rte_atomic64_t *v)
929 rte_atomic64_add(v, 1);
934 * Atomically decrement a 64-bit counter by one and test.
937 * A pointer to the atomic counter.
940 rte_atomic64_dec(rte_atomic64_t *v);
942 #ifdef RTE_FORCE_INTRINSICS
944 rte_atomic64_dec(rte_atomic64_t *v)
946 rte_atomic64_sub(v, 1);
951 * Add a 64-bit value to an atomic counter and return the result.
953 * Atomically adds the 64-bit value (inc) to the atomic counter (v) and
954 * returns the value of v after the addition.
957 * A pointer to the atomic counter.
959 * The value to be added to the counter.
961 * The value of v after the addition.
963 static inline int64_t
964 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);
966 #ifdef RTE_FORCE_INTRINSICS
967 static inline int64_t
968 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
970 return __sync_add_and_fetch(&v->cnt, inc);
975 * Subtract a 64-bit value from an atomic counter and return the result.
977 * Atomically subtracts the 64-bit value (dec) from the atomic counter (v)
978 * and returns the value of v after the subtraction.
981 * A pointer to the atomic counter.
983 * The value to be subtracted from the counter.
985 * The value of v after the subtraction.
987 static inline int64_t
988 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);
990 #ifdef RTE_FORCE_INTRINSICS
991 static inline int64_t
992 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
994 return __sync_sub_and_fetch(&v->cnt, dec);
999 * Atomically increment a 64-bit counter by one and test.
1001 * Atomically increments the atomic counter (v) by one and returns
1002 * true if the result is 0, or false in all other cases.
1005 * A pointer to the atomic counter.
1007 * True if the result after the addition is 0; false otherwise.
1009 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);
1011 #ifdef RTE_FORCE_INTRINSICS
1012 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
1014 return rte_atomic64_add_return(v, 1) == 0;
1019 * Atomically decrement a 64-bit counter by one and test.
1021 * Atomically decrements the atomic counter (v) by one and returns true if
1022 * the result is 0, or false in all other cases.
1025 * A pointer to the atomic counter.
1027 * True if the result after subtraction is 0; false otherwise.
1029 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);
1031 #ifdef RTE_FORCE_INTRINSICS
1032 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
1034 return rte_atomic64_sub_return(v, 1) == 0;
1039 * Atomically test and set a 64-bit atomic counter.
1041 * If the counter value is already set, return 0 (failed). Otherwise, set
1042 * the counter value to 1 and return 1 (success).
1045 * A pointer to the atomic counter.
1047 * 0 if failed; else 1, success.
1049 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v);
1051 #ifdef RTE_FORCE_INTRINSICS
1052 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
1054 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
1059 * Atomically set a 64-bit counter to 0.
1062 * A pointer to the atomic counter.
1064 static inline void rte_atomic64_clear(rte_atomic64_t *v);
1066 #ifdef RTE_FORCE_INTRINSICS
1067 static inline void rte_atomic64_clear(rte_atomic64_t *v)
1069 rte_atomic64_set(v, 0);
1073 #endif /* _RTE_ATOMIC_H_ */