1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
12 * This file defines a generic API for atomic operations.
16 #include <rte_common.h>
20 /** @name Memory Barrier
24 * General memory barrier.
26 * Guarantees that the LOAD and STORE operations generated before the
27 * barrier occur before the LOAD and STORE operations generated after.
28 * This function is architecture dependent.
30 static inline void rte_mb(void);
33 * Write memory barrier.
35 * Guarantees that the STORE operations generated before the barrier
36 * occur before the STORE operations generated after.
37 * This function is architecture dependent.
39 static inline void rte_wmb(void);
42 * Read memory barrier.
44 * Guarantees that the LOAD operations generated before the barrier
45 * occur before the LOAD operations generated after.
46 * This function is architecture dependent.
48 static inline void rte_rmb(void);
51 /** @name SMP Memory Barrier
55 * General memory barrier between lcores
57 * Guarantees that the LOAD and STORE operations that precede the
58 * rte_smp_mb() call are globally visible across the lcores
59 * before the LOAD and STORE operations that follows it.
61 static inline void rte_smp_mb(void);
64 * Write memory barrier between lcores
66 * Guarantees that the STORE operations that precede the
67 * rte_smp_wmb() call are globally visible across the lcores
68 * before the STORE operations that follows it.
70 static inline void rte_smp_wmb(void);
73 * Read memory barrier between lcores
75 * Guarantees that the LOAD operations that precede the
76 * rte_smp_rmb() call are globally visible across the lcores
77 * before the LOAD operations that follows it.
79 static inline void rte_smp_rmb(void);
82 /** @name I/O Memory Barrier
86 * General memory barrier for I/O device
88 * Guarantees that the LOAD and STORE operations that precede the
89 * rte_io_mb() call are visible to I/O device or CPU before the
90 * LOAD and STORE operations that follow it.
92 static inline void rte_io_mb(void);
95 * Write memory barrier for I/O device
97 * Guarantees that the STORE operations that precede the
98 * rte_io_wmb() call are visible to I/O device before the STORE
99 * operations that follow it.
101 static inline void rte_io_wmb(void);
104 * Read memory barrier for IO device
106 * Guarantees that the LOAD operations on I/O device that precede the
107 * rte_io_rmb() call are visible to CPU before the LOAD
108 * operations that follow it.
110 static inline void rte_io_rmb(void);
113 /** @name Coherent I/O Memory Barrier
115 * Coherent I/O memory barrier is a lightweight version of I/O memory
116 * barriers which are system-wide data synchronization barriers. This
117 * is for only coherent memory domain between lcore and I/O device but
118 * it is same as the I/O memory barriers in most of architectures.
119 * However, some architecture provides even lighter barriers which are
120 * somewhere in between I/O memory barriers and SMP memory barriers.
121 * For example, in case of ARMv8, DMB(data memory barrier) instruction
122 * can have different shareability domains - inner-shareable and
123 * outer-shareable. And inner-shareable DMB fits for SMP memory
124 * barriers and outer-shareable DMB for coherent I/O memory barriers,
125 * which acts on coherent memory.
127 * In most cases, I/O memory barriers are safer but if operations are
128 * on coherent memory instead of incoherent MMIO region of a device,
129 * then coherent I/O memory barriers can be used and this could bring
130 * performance gain depending on architectures.
134 * Write memory barrier for coherent memory between lcore and I/O device
136 * Guarantees that the STORE operations on coherent memory that
137 * precede the rte_cio_wmb() call are visible to I/O device before the
138 * STORE operations that follow it.
140 static inline void rte_cio_wmb(void);
143 * Read memory barrier for coherent memory between lcore and I/O device
145 * Guarantees that the LOAD operations on coherent memory updated by
146 * I/O device that precede the rte_cio_rmb() call are visible to CPU
147 * before the LOAD operations that follow it.
149 static inline void rte_cio_rmb(void);
152 #endif /* __DOXYGEN__ */
157 * Guarantees that operation reordering does not occur at compile time
158 * for operations directly before and after the barrier.
160 #define rte_compiler_barrier() do { \
161 asm volatile ("" : : : "memory"); \
164 /*------------------------- 16 bit atomic operations -------------------------*/
167 * Atomic compare and set.
169 * (atomic) equivalent to:
171 * *dst = src (all 16-bit words)
174 * The destination location into which the value will be written.
176 * The expected value.
180 * Non-zero on success; 0 on failure.
183 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);
185 #ifdef RTE_FORCE_INTRINSICS
187 rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
189 return __sync_bool_compare_and_swap(dst, exp, src);
194 * The atomic counter structure.
197 volatile int16_t cnt; /**< An internal counter value. */
201 * Static initializer for an atomic counter.
203 #define RTE_ATOMIC16_INIT(val) { (val) }
206 * Initialize an atomic counter.
209 * A pointer to the atomic counter.
212 rte_atomic16_init(rte_atomic16_t *v)
218 * Atomically read a 16-bit value from a counter.
221 * A pointer to the atomic counter.
223 * The value of the counter.
225 static inline int16_t
226 rte_atomic16_read(const rte_atomic16_t *v)
232 * Atomically set a counter to a 16-bit value.
235 * A pointer to the atomic counter.
237 * The new value for the counter.
240 rte_atomic16_set(rte_atomic16_t *v, int16_t new_value)
246 * Atomically add a 16-bit value to an atomic counter.
249 * A pointer to the atomic counter.
251 * The value to be added to the counter.
254 rte_atomic16_add(rte_atomic16_t *v, int16_t inc)
256 __sync_fetch_and_add(&v->cnt, inc);
260 * Atomically subtract a 16-bit value from an atomic counter.
263 * A pointer to the atomic counter.
265 * The value to be subtracted from the counter.
268 rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
270 __sync_fetch_and_sub(&v->cnt, dec);
274 * Atomically increment a counter by one.
277 * A pointer to the atomic counter.
280 rte_atomic16_inc(rte_atomic16_t *v);
282 #ifdef RTE_FORCE_INTRINSICS
284 rte_atomic16_inc(rte_atomic16_t *v)
286 rte_atomic16_add(v, 1);
291 * Atomically decrement a counter by one.
294 * A pointer to the atomic counter.
297 rte_atomic16_dec(rte_atomic16_t *v);
299 #ifdef RTE_FORCE_INTRINSICS
301 rte_atomic16_dec(rte_atomic16_t *v)
303 rte_atomic16_sub(v, 1);
308 * Atomically add a 16-bit value to a counter and return the result.
310 * Atomically adds the 16-bits value (inc) to the atomic counter (v) and
311 * returns the value of v after addition.
314 * A pointer to the atomic counter.
316 * The value to be added to the counter.
318 * The value of v after the addition.
320 static inline int16_t
321 rte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)
323 return __sync_add_and_fetch(&v->cnt, inc);
327 * Atomically subtract a 16-bit value from a counter and return
330 * Atomically subtracts the 16-bit value (inc) from the atomic counter
331 * (v) and returns the value of v after the subtraction.
334 * A pointer to the atomic counter.
336 * The value to be subtracted from the counter.
338 * The value of v after the subtraction.
340 static inline int16_t
341 rte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)
343 return __sync_sub_and_fetch(&v->cnt, dec);
347 * Atomically increment a 16-bit counter by one and test.
349 * Atomically increments the atomic counter (v) by one and returns true if
350 * the result is 0, or false in all other cases.
353 * A pointer to the atomic counter.
355 * True if the result after the increment operation is 0; false otherwise.
357 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);
359 #ifdef RTE_FORCE_INTRINSICS
360 static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
362 return __sync_add_and_fetch(&v->cnt, 1) == 0;
367 * Atomically decrement a 16-bit counter by one and test.
369 * Atomically decrements the atomic counter (v) by one and returns true if
370 * the result is 0, or false in all other cases.
373 * A pointer to the atomic counter.
375 * True if the result after the decrement operation is 0; false otherwise.
377 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);
379 #ifdef RTE_FORCE_INTRINSICS
380 static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
382 return __sync_sub_and_fetch(&v->cnt, 1) == 0;
387 * Atomically test and set a 16-bit atomic counter.
389 * If the counter value is already set, return 0 (failed). Otherwise, set
390 * the counter value to 1 and return 1 (success).
393 * A pointer to the atomic counter.
395 * 0 if failed; else 1, success.
397 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v);
399 #ifdef RTE_FORCE_INTRINSICS
400 static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
402 return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
407 * Atomically set a 16-bit counter to 0.
410 * A pointer to the atomic counter.
412 static inline void rte_atomic16_clear(rte_atomic16_t *v)
417 /*------------------------- 32 bit atomic operations -------------------------*/
420 * Atomic compare and set.
422 * (atomic) equivalent to:
424 * *dst = src (all 32-bit words)
427 * The destination location into which the value will be written.
429 * The expected value.
433 * Non-zero on success; 0 on failure.
436 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);
438 #ifdef RTE_FORCE_INTRINSICS
440 rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
442 return __sync_bool_compare_and_swap(dst, exp, src);
447 * The atomic counter structure.
450 volatile int32_t cnt; /**< An internal counter value. */
454 * Static initializer for an atomic counter.
456 #define RTE_ATOMIC32_INIT(val) { (val) }
459 * Initialize an atomic counter.
462 * A pointer to the atomic counter.
465 rte_atomic32_init(rte_atomic32_t *v)
471 * Atomically read a 32-bit value from a counter.
474 * A pointer to the atomic counter.
476 * The value of the counter.
478 static inline int32_t
479 rte_atomic32_read(const rte_atomic32_t *v)
485 * Atomically set a counter to a 32-bit value.
488 * A pointer to the atomic counter.
490 * The new value for the counter.
493 rte_atomic32_set(rte_atomic32_t *v, int32_t new_value)
499 * Atomically add a 32-bit value to an atomic counter.
502 * A pointer to the atomic counter.
504 * The value to be added to the counter.
507 rte_atomic32_add(rte_atomic32_t *v, int32_t inc)
509 __sync_fetch_and_add(&v->cnt, inc);
513 * Atomically subtract a 32-bit value from an atomic counter.
516 * A pointer to the atomic counter.
518 * The value to be subtracted from the counter.
521 rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
523 __sync_fetch_and_sub(&v->cnt, dec);
527 * Atomically increment a counter by one.
530 * A pointer to the atomic counter.
533 rte_atomic32_inc(rte_atomic32_t *v);
535 #ifdef RTE_FORCE_INTRINSICS
537 rte_atomic32_inc(rte_atomic32_t *v)
539 rte_atomic32_add(v, 1);
544 * Atomically decrement a counter by one.
547 * A pointer to the atomic counter.
550 rte_atomic32_dec(rte_atomic32_t *v);
552 #ifdef RTE_FORCE_INTRINSICS
554 rte_atomic32_dec(rte_atomic32_t *v)
556 rte_atomic32_sub(v,1);
561 * Atomically add a 32-bit value to a counter and return the result.
563 * Atomically adds the 32-bits value (inc) to the atomic counter (v) and
564 * returns the value of v after addition.
567 * A pointer to the atomic counter.
569 * The value to be added to the counter.
571 * The value of v after the addition.
573 static inline int32_t
574 rte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)
576 return __sync_add_and_fetch(&v->cnt, inc);
580 * Atomically subtract a 32-bit value from a counter and return
583 * Atomically subtracts the 32-bit value (inc) from the atomic counter
584 * (v) and returns the value of v after the subtraction.
587 * A pointer to the atomic counter.
589 * The value to be subtracted from the counter.
591 * The value of v after the subtraction.
593 static inline int32_t
594 rte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)
596 return __sync_sub_and_fetch(&v->cnt, dec);
600 * Atomically increment a 32-bit counter by one and test.
602 * Atomically increments the atomic counter (v) by one and returns true if
603 * the result is 0, or false in all other cases.
606 * A pointer to the atomic counter.
608 * True if the result after the increment operation is 0; false otherwise.
610 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);
612 #ifdef RTE_FORCE_INTRINSICS
613 static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
615 return __sync_add_and_fetch(&v->cnt, 1) == 0;
620 * Atomically decrement a 32-bit counter by one and test.
622 * Atomically decrements the atomic counter (v) by one and returns true if
623 * the result is 0, or false in all other cases.
626 * A pointer to the atomic counter.
628 * True if the result after the decrement operation is 0; false otherwise.
630 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);
632 #ifdef RTE_FORCE_INTRINSICS
633 static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
635 return __sync_sub_and_fetch(&v->cnt, 1) == 0;
640 * Atomically test and set a 32-bit atomic counter.
642 * If the counter value is already set, return 0 (failed). Otherwise, set
643 * the counter value to 1 and return 1 (success).
646 * A pointer to the atomic counter.
648 * 0 if failed; else 1, success.
650 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v);
652 #ifdef RTE_FORCE_INTRINSICS
653 static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
655 return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
660 * Atomically set a 32-bit counter to 0.
663 * A pointer to the atomic counter.
665 static inline void rte_atomic32_clear(rte_atomic32_t *v)
670 /*------------------------- 64 bit atomic operations -------------------------*/
673 * An atomic compare and set function used by the mutex functions.
674 * (atomic) equivalent to:
676 * *dst = src (all 64-bit words)
679 * The destination into which the value will be written.
681 * The expected value.
685 * Non-zero on success; 0 on failure.
688 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);
690 #ifdef RTE_FORCE_INTRINSICS
692 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
694 return __sync_bool_compare_and_swap(dst, exp, src);
699 * The atomic counter structure.
702 volatile int64_t cnt; /**< Internal counter value. */
706 * Static initializer for an atomic counter.
708 #define RTE_ATOMIC64_INIT(val) { (val) }
711 * Initialize the atomic counter.
714 * A pointer to the atomic counter.
717 rte_atomic64_init(rte_atomic64_t *v);
719 #ifdef RTE_FORCE_INTRINSICS
721 rte_atomic64_init(rte_atomic64_t *v)
729 while (success == 0) {
731 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
739 * Atomically read a 64-bit counter.
742 * A pointer to the atomic counter.
744 * The value of the counter.
746 static inline int64_t
747 rte_atomic64_read(rte_atomic64_t *v);
749 #ifdef RTE_FORCE_INTRINSICS
750 static inline int64_t
751 rte_atomic64_read(rte_atomic64_t *v)
759 while (success == 0) {
761 /* replace the value by itself */
762 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
771 * Atomically set a 64-bit counter.
774 * A pointer to the atomic counter.
776 * The new value of the counter.
779 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value);
781 #ifdef RTE_FORCE_INTRINSICS
783 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
791 while (success == 0) {
793 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
801 * Atomically add a 64-bit value to a counter.
804 * A pointer to the atomic counter.
806 * The value to be added to the counter.
809 rte_atomic64_add(rte_atomic64_t *v, int64_t inc);
811 #ifdef RTE_FORCE_INTRINSICS
813 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
815 __sync_fetch_and_add(&v->cnt, inc);
820 * Atomically subtract a 64-bit value from a counter.
823 * A pointer to the atomic counter.
825 * The value to be subtracted from the counter.
828 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec);
830 #ifdef RTE_FORCE_INTRINSICS
832 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
834 __sync_fetch_and_sub(&v->cnt, dec);
839 * Atomically increment a 64-bit counter by one and test.
842 * A pointer to the atomic counter.
845 rte_atomic64_inc(rte_atomic64_t *v);
847 #ifdef RTE_FORCE_INTRINSICS
849 rte_atomic64_inc(rte_atomic64_t *v)
851 rte_atomic64_add(v, 1);
856 * Atomically decrement a 64-bit counter by one and test.
859 * A pointer to the atomic counter.
862 rte_atomic64_dec(rte_atomic64_t *v);
864 #ifdef RTE_FORCE_INTRINSICS
866 rte_atomic64_dec(rte_atomic64_t *v)
868 rte_atomic64_sub(v, 1);
873 * Add a 64-bit value to an atomic counter and return the result.
875 * Atomically adds the 64-bit value (inc) to the atomic counter (v) and
876 * returns the value of v after the addition.
879 * A pointer to the atomic counter.
881 * The value to be added to the counter.
883 * The value of v after the addition.
885 static inline int64_t
886 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);
888 #ifdef RTE_FORCE_INTRINSICS
889 static inline int64_t
890 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
892 return __sync_add_and_fetch(&v->cnt, inc);
897 * Subtract a 64-bit value from an atomic counter and return the result.
899 * Atomically subtracts the 64-bit value (dec) from the atomic counter (v)
900 * and returns the value of v after the subtraction.
903 * A pointer to the atomic counter.
905 * The value to be subtracted from the counter.
907 * The value of v after the subtraction.
909 static inline int64_t
910 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);
912 #ifdef RTE_FORCE_INTRINSICS
913 static inline int64_t
914 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
916 return __sync_sub_and_fetch(&v->cnt, dec);
921 * Atomically increment a 64-bit counter by one and test.
923 * Atomically increments the atomic counter (v) by one and returns
924 * true if the result is 0, or false in all other cases.
927 * A pointer to the atomic counter.
929 * True if the result after the addition is 0; false otherwise.
931 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);
933 #ifdef RTE_FORCE_INTRINSICS
934 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
936 return rte_atomic64_add_return(v, 1) == 0;
941 * Atomically decrement a 64-bit counter by one and test.
943 * Atomically decrements the atomic counter (v) by one and returns true if
944 * the result is 0, or false in all other cases.
947 * A pointer to the atomic counter.
949 * True if the result after subtraction is 0; false otherwise.
951 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);
953 #ifdef RTE_FORCE_INTRINSICS
954 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
956 return rte_atomic64_sub_return(v, 1) == 0;
961 * Atomically test and set a 64-bit atomic counter.
963 * If the counter value is already set, return 0 (failed). Otherwise, set
964 * the counter value to 1 and return 1 (success).
967 * A pointer to the atomic counter.
969 * 0 if failed; else 1, success.
971 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v);
973 #ifdef RTE_FORCE_INTRINSICS
974 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
976 return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
981 * Atomically set a 64-bit counter to 0.
984 * A pointer to the atomic counter.
986 static inline void rte_atomic64_clear(rte_atomic64_t *v);
988 #ifdef RTE_FORCE_INTRINSICS
989 static inline void rte_atomic64_clear(rte_atomic64_t *v)
991 rte_atomic64_set(v, 0);
995 #endif /* _RTE_ATOMIC_H_ */