4 * Copyright(c) 2016 Cavium networks. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium networks nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_atomic.h>
41 * I/O device memory operations
43 * This file defines the generic API for I/O device memory read/write operations
47 #include <rte_common.h>
48 #include <rte_atomic.h>
53 * Read a 8-bit value from I/O device memory address *addr*.
55 * The relaxed version does not have additional I/O memory barrier, useful in
56 * accessing the device registers of integrated controllers which implicitly
57 * strongly ordered with respect to memory access.
60 * I/O memory address to read the value from
65 rte_read8_relaxed(const volatile void *addr);
68 * Read a 16-bit value from I/O device memory address *addr*.
70 * The relaxed version does not have additional I/O memory barrier, useful in
71 * accessing the device registers of integrated controllers which implicitly
72 * strongly ordered with respect to memory access.
75 * I/O memory address to read the value from
79 static inline uint16_t
80 rte_read16_relaxed(const volatile void *addr);
83 * Read a 32-bit value from I/O device memory address *addr*.
85 * The relaxed version does not have additional I/O memory barrier, useful in
86 * accessing the device registers of integrated controllers which implicitly
87 * strongly ordered with respect to memory access.
90 * I/O memory address to read the value from
94 static inline uint32_t
95 rte_read32_relaxed(const volatile void *addr);
98 * Read a 64-bit value from I/O device memory address *addr*.
100 * The relaxed version does not have additional I/O memory barrier, useful in
101 * accessing the device registers of integrated controllers which implicitly
102 * strongly ordered with respect to memory access.
105 * I/O memory address to read the value from
109 static inline uint64_t
110 rte_read64_relaxed(const volatile void *addr);
113 * Write a 8-bit value to I/O device memory address *addr*.
115 * The relaxed version does not have additional I/O memory barrier, useful in
116 * accessing the device registers of integrated controllers which implicitly
117 * strongly ordered with respect to memory access.
122 * I/O memory address to write the value to
126 rte_write8_relaxed(uint8_t value, volatile void *addr);
129 * Write a 16-bit value to I/O device memory address *addr*.
131 * The relaxed version does not have additional I/O memory barrier, useful in
132 * accessing the device registers of integrated controllers which implicitly
133 * strongly ordered with respect to memory access.
138 * I/O memory address to write the value to
141 rte_write16_relaxed(uint16_t value, volatile void *addr);
144 * Write a 32-bit value to I/O device memory address *addr*.
146 * The relaxed version does not have additional I/O memory barrier, useful in
147 * accessing the device registers of integrated controllers which implicitly
148 * strongly ordered with respect to memory access.
153 * I/O memory address to write the value to
156 rte_write32_relaxed(uint32_t value, volatile void *addr);
159 * Write a 64-bit value to I/O device memory address *addr*.
161 * The relaxed version does not have additional I/O memory barrier, useful in
162 * accessing the device registers of integrated controllers which implicitly
163 * strongly ordered with respect to memory access.
168 * I/O memory address to write the value to
171 rte_write64_relaxed(uint64_t value, volatile void *addr);
174 * Read a 8-bit value from I/O device memory address *addr*.
177 * I/O memory address to read the value from
181 static inline uint8_t
182 rte_read8(const volatile void *addr);
185 * Read a 16-bit value from I/O device memory address *addr*.
189 * I/O memory address to read the value from
193 static inline uint16_t
194 rte_read16(const volatile void *addr);
197 * Read a 32-bit value from I/O device memory address *addr*.
200 * I/O memory address to read the value from
204 static inline uint32_t
205 rte_read32(const volatile void *addr);
208 * Read a 64-bit value from I/O device memory address *addr*.
211 * I/O memory address to read the value from
215 static inline uint64_t
216 rte_read64(const volatile void *addr);
219 * Write a 8-bit value to I/O device memory address *addr*.
224 * I/O memory address to write the value to
228 rte_write8(uint8_t value, volatile void *addr);
231 * Write a 16-bit value to I/O device memory address *addr*.
236 * I/O memory address to write the value to
239 rte_write16(uint16_t value, volatile void *addr);
242 * Write a 32-bit value to I/O device memory address *addr*.
247 * I/O memory address to write the value to
250 rte_write32(uint32_t value, volatile void *addr);
253 * Write a 64-bit value to I/O device memory address *addr*.
258 * I/O memory address to write the value to
261 rte_write64(uint64_t value, volatile void *addr);
263 #endif /* __DOXYGEN__ */
265 #ifndef RTE_OVERRIDE_IO_H
267 static inline uint8_t __attribute__((always_inline))
268 rte_read8_relaxed(const volatile void *addr)
270 return *(const volatile uint8_t *)addr;
273 static inline uint16_t __attribute__((always_inline))
274 rte_read16_relaxed(const volatile void *addr)
276 return *(const volatile uint16_t *)addr;
279 static inline uint32_t __attribute__((always_inline))
280 rte_read32_relaxed(const volatile void *addr)
282 return *(const volatile uint32_t *)addr;
285 static inline uint64_t __attribute__((always_inline))
286 rte_read64_relaxed(const volatile void *addr)
288 return *(const volatile uint64_t *)addr;
291 static inline void __attribute__((always_inline))
292 rte_write8_relaxed(uint8_t value, volatile void *addr)
294 *(volatile uint8_t *)addr = value;
297 static inline void __attribute__((always_inline))
298 rte_write16_relaxed(uint16_t value, volatile void *addr)
300 *(volatile uint16_t *)addr = value;
303 static inline void __attribute__((always_inline))
304 rte_write32_relaxed(uint32_t value, volatile void *addr)
306 *(volatile uint32_t *)addr = value;
309 static inline void __attribute__((always_inline))
310 rte_write64_relaxed(uint64_t value, volatile void *addr)
312 *(volatile uint64_t *)addr = value;
315 static inline uint8_t __attribute__((always_inline))
316 rte_read8(const volatile void *addr)
319 val = rte_read8_relaxed(addr);
324 static inline uint16_t __attribute__((always_inline))
325 rte_read16(const volatile void *addr)
328 val = rte_read16_relaxed(addr);
333 static inline uint32_t __attribute__((always_inline))
334 rte_read32(const volatile void *addr)
337 val = rte_read32_relaxed(addr);
342 static inline uint64_t __attribute__((always_inline))
343 rte_read64(const volatile void *addr)
346 val = rte_read64_relaxed(addr);
351 static inline void __attribute__((always_inline))
352 rte_write8(uint8_t value, volatile void *addr)
355 rte_write8_relaxed(value, addr);
358 static inline void __attribute__((always_inline))
359 rte_write16(uint16_t value, volatile void *addr)
362 rte_write16_relaxed(value, addr);
365 static inline void __attribute__((always_inline))
366 rte_write32(uint32_t value, volatile void *addr)
369 rte_write32_relaxed(value, addr);
372 static inline void __attribute__((always_inline))
373 rte_write64(uint64_t value, volatile void *addr)
376 rte_write64_relaxed(value, addr);
379 #endif /* RTE_OVERRIDE_IO_H */
381 #endif /* _RTE_IO_H_ */