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34 #ifndef _RTE_CPUFLAGS_H_
35 #define _RTE_CPUFLAGS_H_
39 * Simple API to determine available CPU features at runtime.
48 * Enumeration of all CPU features supported
51 /* (EAX 01h) ECX features*/
52 RTE_CPUFLAG_SSE3 = 0, /**< SSE3 */
53 RTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */
54 RTE_CPUFLAG_DTES64, /**< DTES64 */
55 RTE_CPUFLAG_MONITOR, /**< MONITOR */
56 RTE_CPUFLAG_DS_CPL, /**< DS_CPL */
57 RTE_CPUFLAG_VMX, /**< VMX */
58 RTE_CPUFLAG_SMX, /**< SMX */
59 RTE_CPUFLAG_EIST, /**< EIST */
60 RTE_CPUFLAG_TM2, /**< TM2 */
61 RTE_CPUFLAG_SSSE3, /**< SSSE3 */
62 RTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */
63 RTE_CPUFLAG_FMA, /**< FMA */
64 RTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */
65 RTE_CPUFLAG_XTPR, /**< XTPR */
66 RTE_CPUFLAG_PDCM, /**< PDCM */
67 RTE_CPUFLAG_PCID, /**< PCID */
68 RTE_CPUFLAG_DCA, /**< DCA */
69 RTE_CPUFLAG_SSE4_1, /**< SSE4_1 */
70 RTE_CPUFLAG_SSE4_2, /**< SSE4_2 */
71 RTE_CPUFLAG_X2APIC, /**< X2APIC */
72 RTE_CPUFLAG_MOVBE, /**< MOVBE */
73 RTE_CPUFLAG_POPCNT, /**< POPCNT */
74 RTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */
75 RTE_CPUFLAG_AES, /**< AES */
76 RTE_CPUFLAG_XSAVE, /**< XSAVE */
77 RTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */
78 RTE_CPUFLAG_AVX, /**< AVX */
79 RTE_CPUFLAG_F16C, /**< F16C */
80 RTE_CPUFLAG_RDRAND, /**< RDRAND */
82 /* (EAX 01h) EDX features */
83 RTE_CPUFLAG_FPU, /**< FPU */
84 RTE_CPUFLAG_VME, /**< VME */
85 RTE_CPUFLAG_DE, /**< DE */
86 RTE_CPUFLAG_PSE, /**< PSE */
87 RTE_CPUFLAG_TSC, /**< TSC */
88 RTE_CPUFLAG_MSR, /**< MSR */
89 RTE_CPUFLAG_PAE, /**< PAE */
90 RTE_CPUFLAG_MCE, /**< MCE */
91 RTE_CPUFLAG_CX8, /**< CX8 */
92 RTE_CPUFLAG_APIC, /**< APIC */
93 RTE_CPUFLAG_SEP, /**< SEP */
94 RTE_CPUFLAG_MTRR, /**< MTRR */
95 RTE_CPUFLAG_PGE, /**< PGE */
96 RTE_CPUFLAG_MCA, /**< MCA */
97 RTE_CPUFLAG_CMOV, /**< CMOV */
98 RTE_CPUFLAG_PAT, /**< PAT */
99 RTE_CPUFLAG_PSE36, /**< PSE36 */
100 RTE_CPUFLAG_PSN, /**< PSN */
101 RTE_CPUFLAG_CLFSH, /**< CLFSH */
102 RTE_CPUFLAG_DS, /**< DS */
103 RTE_CPUFLAG_ACPI, /**< ACPI */
104 RTE_CPUFLAG_MMX, /**< MMX */
105 RTE_CPUFLAG_FXSR, /**< FXSR */
106 RTE_CPUFLAG_SSE, /**< SSE */
107 RTE_CPUFLAG_SSE2, /**< SSE2 */
108 RTE_CPUFLAG_SS, /**< SS */
109 RTE_CPUFLAG_HTT, /**< HTT */
110 RTE_CPUFLAG_TM, /**< TM */
111 RTE_CPUFLAG_PBE, /**< PBE */
113 /* (EAX 06h) EAX features */
114 RTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */
115 RTE_CPUFLAG_TRBOBST, /**< TRBOBST */
116 RTE_CPUFLAG_ARAT, /**< ARAT */
117 RTE_CPUFLAG_PLN, /**< PLN */
118 RTE_CPUFLAG_ECMD, /**< ECMD */
119 RTE_CPUFLAG_PTM, /**< PTM */
121 /* (EAX 06h) ECX features */
122 RTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */
123 RTE_CPUFLAG_ACNT2, /**< ACNT2 */
124 RTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */
126 /* (EAX 07h, ECX 0h) EBX features */
127 RTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */
128 RTE_CPUFLAG_BMI1, /**< BMI1 */
129 RTE_CPUFLAG_HLE, /**< Hardware Lock elision */
130 RTE_CPUFLAG_AVX2, /**< AVX2 */
131 RTE_CPUFLAG_SMEP, /**< SMEP */
132 RTE_CPUFLAG_BMI2, /**< BMI2 */
133 RTE_CPUFLAG_ERMS, /**< ERMS */
134 RTE_CPUFLAG_INVPCID, /**< INVPCID */
135 RTE_CPUFLAG_RTM, /**< Transactional memory */
137 /* (EAX 80000001h) ECX features */
138 RTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */
139 RTE_CPUFLAG_LZCNT, /**< LZCNT */
141 /* (EAX 80000001h) EDX features */
142 RTE_CPUFLAG_SYSCALL, /**< SYSCALL */
143 RTE_CPUFLAG_XD, /**< XD */
144 RTE_CPUFLAG_1GB_PG, /**< 1GB_PG */
145 RTE_CPUFLAG_RDTSCP, /**< RDTSCP */
146 RTE_CPUFLAG_EM64T, /**< EM64T */
148 /* (EAX 80000007h) EDX features */
149 RTE_CPUFLAG_INVTSC, /**< INVTSC */
152 RTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */
157 * Function for checking a CPU flag availability
160 * CPU flag to query CPU for
162 * 1 if flag is available
163 * 0 if flag is not available
164 * -ENOENT if flag is invalid
167 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t flag);
170 * This function checks that the currently used CPU supports the CPU features
171 * that were specified at compile time. It is called automatically within the
172 * EAL, so does not need to be used by applications.
175 rte_cpu_check_supported(void);
182 #endif /* _RTE_CPUFLAGS_H_ */